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IS80C51 |
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ISSI |
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IS80C31 |
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® |
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IS80C31 |
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CMOS SINGLE CHIP |
NOVEMBER 1998 |
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8-BIT MICROCONTROLLER |
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FEATURES
•80C51 based architecture
•4K x 8 ROM (IS80C51 only)
•128 x 8 RAM
•Two 16-bit Timer/Counters
•Full duplex serial channel
•Boolean processor
•Four 8-bit I/O ports, 32 I/O lines
•Memory addressing capability
–64K ROM and 64K RAM
•Power save modes:
–Idle and power-down
•Six interrupt sources
•Most instructions execute in 0.3 μs
•CMOS and TTL compatible
•Maximum speed: 40 MHz @ Vcc = 5V
•Industrial temperature available
•Packages available:
–40-pin DIP
–44-pin PLCC
–44-pin PQFP
GENERAL DESCRIPTION
The ISSI IS80C51 and IS80C31 are high-performance microcontrollers fabricated using high-density CMOS technology. The CMOS IS80C51/31 is functionally compatible with the industry standard 80C51 microcontrollers.
The IS80C51/31 is designed with 4K x 8 ROM (IS80C51 only); 128 x 8 RAM; 32 programmable I/O lines; a serial I/O port for either multiprocessor communications, I/O expansion or full duplex UART; two 16-bit timer/counters; a six-source, two-priority-level, nested interrupt structure; and an on-chip oscillator and clock circuit. The IS80C51/31 can be expanded using standard TTL compatible memory.
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P1.0 |
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1 |
40 |
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VCC |
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P1.1 |
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39 |
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P0.0/AD0 |
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2 |
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P1.2 |
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38 |
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P0.1/AD1 |
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3 |
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P1.3 |
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37 |
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P0.2/AD2 |
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4 |
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P1.4 |
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36 |
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P0.3/AD3 |
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5 |
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P1.5 |
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35 |
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P0.4/AD4 |
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6 |
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P1.6 |
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34 |
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P0.5/AD5 |
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7 |
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P1.7 |
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8 |
33 |
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P0.6/AD6 |
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RST |
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32 |
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P0.7/AD7 |
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9 |
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RxD/P3.0 |
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31 |
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10 |
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EA/VPP |
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TxD/P3.1 |
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30 |
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11 |
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ALE/PROG |
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29 |
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INT0/P3.2 |
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12 |
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PSEN |
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13 |
28 |
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P2.7/A15 |
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INT1/P3.3 |
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T0/P3.4 |
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14 |
27 |
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P2.6/A14 |
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T1/P3.5 |
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15 |
26 |
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P2.5/A13 |
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16 |
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P2.4/A12 |
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WR/P3.6 |
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17 |
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P2.3/A11 |
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RD/P3.7 |
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XTAL2 |
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P2.2/A10 |
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XTAL1 |
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P2.1/A9 |
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GND |
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P2.0/A8 |
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Figure 1. IS80C51/31 Pin Configuration: 40-pin PDIP
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
1 |
MC003-1D 11/19/98
IS80C51
IS80C31
INDEX
P1.5 7
P1.6 8
P1.7 9
RST 10
RxD/P3.0 11
NC 12
TxD/P3.1 13
INT0/P3.2 14
INT1/P3.3 15
T0/P3.4 16
T1/P3.5 17
P1.4 |
P1.3 |
P1.2 |
P1.1 |
P1.0 |
NC |
VCC |
P0.0/AD0 |
P0.1/AD1 |
P0.2/AD2 |
P0.3/AD3 |
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6 |
5 |
4 |
3 |
2 |
1 |
44 |
43 |
42 |
41 |
40 |
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39 |
P0.4/AD4 |
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38 |
P0.5/AD5 |
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37 |
P0.6/AD6 |
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36 |
P0.7/AD7 |
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35 |
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EA/VPP |
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TOP VIEW |
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34 |
NC |
33 ALE/PROG
32 PSEN
31 P2.7/A15
30 P2.6/A14
29 P2.5/A13
18 |
19 |
20 |
21 |
22 |
23 |
24 |
25 |
26 |
27 |
28 |
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WR/P3.6 |
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RD/P3.7 |
XTAL2 |
XTAL1 |
GND |
NC |
A8/P2.0 |
A9/P2.1 |
A10/P2.2 |
A11/P2.3 |
A12/P2.4 |
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Figure 2. IS80C51/31 Pin Configuration: 44-pin PLCC
2 |
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
MC003-1D 11/19/98
IS80C51 |
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IS80C31 |
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P1.4 |
P1.3 |
P1.2 |
P1.1 |
P1.0 |
NC |
VCC |
P0.0/AD0 |
P0.1/AD1 |
P0.2/AD2 |
P0.3/AD3 |
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44 |
43 |
42 |
41 |
40 |
39 |
38 |
37 |
36 |
35 |
34 |
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P1.5 |
1 |
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33 |
P0.4/AD4 |
P1.6 |
2 |
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32 |
P0.5/AD5 |
P1.7 |
3 |
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31 |
P0.6/AD6 |
RST |
4 |
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30 |
P0.7/AD7 |
RxD/P3.0 |
5 |
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29 |
EA/VPP |
NC |
6 |
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28 |
NC |
TxD/P3.1 |
7 |
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27 |
ALE/PROG |
INT0/P3.2 |
8 |
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26 |
PSEN |
INT1/P3.3 |
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25 |
P2.7/A15 |
T0/P3.4 |
10 |
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24 |
P2.6/A14 |
T1/P3.5 |
11 |
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23 |
P2.5/A13 |
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12 |
13 |
14 |
15 |
16 |
17 |
18 |
19 |
20 |
21 |
22 |
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WR/P3.6 |
RD/P3.7 |
XTAL2 |
XTAL1 |
GND |
NC |
A8/P2.0 |
A9/P2.1 |
A10/P2.2 |
A11/P2.3 |
A12/P2.4 |
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Figure 3. IS80C51/31 Pin Configuration: 44-pin PQFP
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
3 |
MC003-1D 11/19/98
IS80C51
IS80C31
P2.0-P2.7 |
P0.0-P0.7 |
VCC
PSEN ALE RST
EA
RAM ADDR
REGISTER
B
REGISTER
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TIMING |
INSTRUCTION REGISTER |
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AND |
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CONTROL |
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OSCILLATOR |
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P2
DRIVERS
ADDRESS |
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DECODER |
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& 128 |
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P2 |
BYTES RAM |
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LATCH |
STACK
POINT
PCON SCON TMOD TCON
TH0 TL0 TH1
TL1
SBUF IE IP
INTERRUPT BLOCK
SERIAL PORT BLOCK
TIMER BLOCK
XTAL1 |
XTAL2 |
P0
DRIVERS
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ADDRESS |
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DECODER |
P0 |
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& |
LATCH |
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4K ROM |
ACC
TMP2 TMP1
ALU
PSW
P3 |
P1 |
LATCH |
LATCH |
P3 |
P1 |
DRIVERS |
DRIVERS |
PROGRAM
ADDRESS
REGISTER
PROGRAM
COUNTER
PC
INCREMENTER
BUFFER
DPTR
P3.0-P3.7 |
P1.0-P1.7 |
Figure 4. IS80C51/31 Block Diagram
4 |
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
MC003-1D 11/19/98
IS80C51
IS80C31
Table 1. Detailed Pin Description
Symbol |
PDIP |
PLCC |
PQFP |
I/O |
Name and Function |
ALE |
30 |
33 |
27 |
I/O |
Address Latch Enable: Output pulse for latching the low byte |
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of the address during an address to the external memory. In |
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normal operation, ALE is emitted at a constant rate of 1/6 the |
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oscillator frequency, and can be used for external timing or |
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clocking. Note that one ALE pulse is skipped during each |
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access to external data memory. |
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EA |
31 |
35 |
29 |
I |
External Access enable: EA must be externally held low to |
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enable the device to fetch code from external program memory |
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locations 0000H to FFFFH. If EA is held high, the device |
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executes from internal program memory unless the program |
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counter contains an address greater than 0FFFH. |
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P0.0-P0.7 |
39-32 |
43-36 |
37-30 |
I/O |
Port 0: Port 0 is an 8-bit open-drain, bidirectional I/O port. Port |
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0 pins that have 1s written to them float and can be used as high- |
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impedance inputs. Port 0 is also the multiplexed low-order |
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address and data bus during accesses to external program and |
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data memory. In this application, it uses strong internal pullups |
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when emitting 1s. |
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P1.0-P1.7 |
1-8 |
2-9 |
40-44 |
I/O |
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal |
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1-3 |
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pullups. Port 1 pins that have 1s written to them are pulled high |
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by the internal pullups and can be used as inputs. As inputs, |
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Port 1 pins that are externally pulled low will source current |
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because of the internal pullups. (See DC Characteristics: IIL). |
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The Port 1 output buffers can sink/source four TTL inputs. |
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Port 1 also receives the low-order address byte during ROM |
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verification. |
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P2.0-P2.7 |
21-28 |
24-31 |
18-25 |
I/O |
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal |
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pullups. Port 2 pins that have 1s written to them are pulled high |
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by the internal pullups and can be used as inputs. As inputs, |
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Port 2 pins that are externally pulled low will source current |
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because of the internal pullups. (See DC Characteristics: IIL). |
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Port 2 emits the high order address byte during fetches from |
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external program memory and during accesses to external data |
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memory that used 16-bit addresses (MOVX @ DPTR). In this |
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application, Port 2 uses strong internal pullups when emitting |
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1s. During accesses to external data memory that use 8-bit |
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addresses (MOVX @ Ri [i = 0, 1]), Port 2 emits the contents of |
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the P2 Special Function Register. |
Port 2 also receives the high-order bits and some control signals during ROM verification.
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
5 |
MC003-1D 11/19/98
IS80C51
IS80C31
Table 1. Detailed Pin Description (continued)
Symbol |
PDIP |
PLCC |
PQFP |
I/O |
Name and Function |
P3.0-P3.7 |
10-17 |
11, 13-19 |
5, 7-13 |
I/O |
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal |
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pullups. Port 3 pins that have 1s written to them are pulled high |
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by the internal pullups and can be used as inputs. As inputs, |
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Port 3 pins that are externally pulled low will source current |
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because of the internal pullups. (See DC Characteristics: IIL). |
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Port 3 also serves the special features of the IS80LV51/31, as |
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listed below: |
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10 |
11 |
5 |
I |
RxD (P3.0): Serial input port. |
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11 |
13 |
7 |
O |
TxD (P3.1): Serial output port. |
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12 |
14 |
8 |
I |
INT0 (P3.2): External interrupt 0. |
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13 |
15 |
9 |
I |
INT1 (P3.3): External interrupt 1. |
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14 |
16 |
10 |
I |
T0 (P3.4): Timer 0 external input. |
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15 |
17 |
11 |
I |
T1 (P3.5): Timer 1 external input. |
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16 |
18 |
12 |
O |
WR (P3.6): External data memory write strobe. |
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17 |
19 |
13 |
O |
RD (P3.7): External data memory read strobe. |
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PSEN |
29 |
32 |
26 |
O |
Program Store Enable: The read strobe to external program |
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memory. When the device is executing code from the external |
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program memory, PSEN is activated twice each machine cycle |
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except that two PSEN activations are skipped during each |
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access to external data memory. PSEN is not activated during |
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fetches from internal program memory. |
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RST |
9 |
10 |
4 |
I |
Reset: A high on this pin for two machine cycles while the |
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oscillator is running, resets the device. An internal MOS resistor |
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to GND permits a power-on reset using only an external |
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capacitor connected to Vcc. |
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XTAL 1 |
19 |
21 |
15 |
I |
Crystal 1: Input to the inverting oscillator amplifier and input |
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to the internal clock generator circuits. |
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XTAL 2 |
18 |
20 |
14 |
O |
Crystal 2: Output from the inverting oscillator amplifier. |
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GND |
20 |
22 |
16 |
I |
Ground: 0V reference. |
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Vcc |
40 |
44 |
38 |
I |
Power Supply: This is the power supply voltage for operation. |
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6 |
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
MC003-1D 11/19/98
IS80C51
IS80C31
OPERATING DESCRIPTION
The detail description of the IS80C51/31 included in this description are:
•Memory Map and Registers
•Timer/Counters
•Serial Interface
•Interrupt System
•Other Information
MEMORY MAP AND REGISTERS
addressing. Figure 6 shows internal data memory organization and SFR Memory Map.
The lower 128 bytes of RAM can be divided into three segments as listed below and shown in Figure 7.
1.Register Banks 0-3: locations 00H through 1FH (32 bytes). The device after reset defaults to register bank 0. To use the other register banks, the user must select them in software. Each register bank contains eight 1-byte registers R0-R7. Reset initializes the stack point to location 07H, and is incremented once to start from 08H, which is the first register of the second register bank.
Memory
The IS80C51/31 has separate address spaces for program and data memory. The program and data memory can be up to 64K bytes long. The lower 4K program memory can reside on-chip. (IS80C51 only) Figure 5 shows a map of the IS80C51/31 program and data memory.
The IS80C51/31 has 128 bytes of on-chip RAM, plus numbers of special function registers. The lower 128 bytes can be accessed either by direct addressing or by indirect
2.Bit Addressable Area: 16 bytes have been assigned for this segment 20H-2FH. Each one of the 128 bits of this segment can be directly addressed (0- 7FH). Each of the 16 bytes in this segment can also be addressed as a byte.
3.Scratch Pad Area: 30H-7FH are available to the user as data RAM. However, if the data pointer has been initialized to this area, enough bytes should be left aside to prevent SP data destruction.
Program Memory |
Data Memory |
(Read Only) |
(Read/Write) |
FFFFH: |
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FFFFH |
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64K |
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External |
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External |
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0FFFH: |
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Internal |
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FFH |
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4K |
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EA = 0 |
EA = 1 |
7FH |
80H |
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External |
Internal |
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0000 |
00 |
0000 |
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PSEN |
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RD WR |
Figure 5. IS80C51/31 Program and Data Memory Structure
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
7 |
MC003-1D 11/19/98
IS80C51
IS80C31
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFR's) are located in upper 128 Bytes direct addressing area. The SFR Memory Map in Figure 6 shows that.
Not all of the addresses are occupied. Unoccupied addresses are not implemented on the chip. Read accesses to these addresses in general return random data, and write accesses have no effect.
User software should not write 1s to these unimplemented locations, since they may be used in future microcontrollers to invoke new features. In that case, the reset or inactive values of the new bits will always be 0, and their active values will be 1.
The functions of the SFRs are outlined in the following sections, and detailed in Table 2.
Accumulator (ACC)
ACC is the Accumulator register. The mnemonics for Accumulator-specific instructions, however, refer to the Accumulator simply as A.
B Register (B)
The B register is used during multiply and divide operations. For other instructions it can be treated as another scratch pad register.
Program Status Word (PSW). The PSW register contains program status information.
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FFH |
F8 |
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FF |
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F0 |
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B |
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F7 |
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E8 |
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EF |
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Not Available |
Accessible |
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E0 |
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ACC |
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E7 |
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Upper |
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D8 |
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DF |
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in |
by Direct |
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128 |
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D0 |
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PSW |
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D7 |
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IS80C51/31 |
Addressing |
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C8 |
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CF |
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C0 |
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C7 |
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B8 |
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IP |
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BF |
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80H |
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80H |
B0 |
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P3 |
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B7 |
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A8 |
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IE |
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AF |
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7FH |
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A0 |
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P2 |
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A7 |
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98 |
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SCON |
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SBUF |
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9F |
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Accessible |
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90 |
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P1 |
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97 |
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Lower |
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Ports, |
88 |
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TCON |
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TMOD |
TL0 |
TL1 |
TH0 |
TH1 |
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8F |
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by Direct |
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Status and |
80 |
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P0 |
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SP |
DPL |
DPH |
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PCON |
87 |
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128 |
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and Indirect |
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Special |
Control Bits, |
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Addressing |
Timer, |
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Function |
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Registers, |
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Bit |
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Registers |
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Stack Pointer, |
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Addressable |
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0 |
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Accumulator |
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(Etc.) |
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Figure 6. Internal Data Memory and SFR Memory Map
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8 BYTES |
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78 |
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7F |
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70 |
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77 |
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68 |
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6F |
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60 |
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67 |
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58 |
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5F |
SCRATCH |
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50 |
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57 |
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PAD |
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48 |
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4F |
AREA |
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40 |
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47 |
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38 |
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3F |
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30 |
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37 |
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28 |
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...7F |
2F |
BIT |
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ADDRESSABLE |
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20 |
0 ... |
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27 |
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SEGMENT |
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BANK3 |
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18 |
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1F |
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10 |
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BANK2 |
17 |
REGISTER |
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08 |
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BANK 1 |
0F |
BANKS |
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00 |
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BANK 0 |
07 |
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Figure 7. Lower 128 Bytes of Internal RAM |
8 |
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
MC003-1D 11/19/98
IS80C51
IS80C31
SPECIAL FUNCTION REGISTERS
(Continued)
Stack Pointer (SP)
The Stack Pointer Register is eight bits wide. It is incremented before data is stored during PUSH and CALL executions. While the stack may reside anywhere in onchip RAM, the Stack Pointer is initialized to 07H after a reset. This causes the stack to begin at location 08H.
Data Pointer (DPTR)
The Data Pointer consists of a high byte (DPH) and a low byte (DPL). Its function is to hold a 16-bit address. It may be manipulated as a 16-bit register or as two independent 8-bit registers.
Ports 0 To 3
P0, P1, P2, and P3 are the SFR latches of Ports 0, 1, 2, and 3, respectively.
Serial Data Buffer (SBUF)
The Serial Data Buffer is actually two separate registers, a transmit buffer and a receive buffer register. When data is moved to SBUF, it goes to the transmit buffer, where it is held for serial transmission. (Moving a byte to SBUF initiates the transmission.) When data is moved from SBUF, it comes from the receive buffer.
Timer Registers
Register pairs (TH0, TL0) and (TH1, TL1) are the 16-bit Counter registers for Timer/Counters 0 and 1, respectively.
Control Registers
Special Function Registers IP, IE, TMOD, TCON, SCON, and PCON contain control and status bits for the interrupt system, the Timer/Counters, and the serial port. They are described in later sections of this chapter.
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
9 |
MC003-1D 11/19/98
IS80C51
IS80C31
Table 2. Special Function Register
Symbol |
Description |
Direct Address |
Bit Address, Symbol, or Alternative Port Function |
Reset Value |
||||||||
ACC(1) |
Accumulator |
|
E0H |
E7 |
E6 |
E5 |
E4 |
E3 |
E2 |
E1 |
E0 |
00H |
B(1) |
B register |
|
F0H |
F7 |
F6 |
F5 |
F4 |
F3 |
F2 |
F1 |
F0 |
00H |
DPH |
Data pointer (DPTR) high |
83H |
|
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|
00H |
|
DPL |
Data pointer (DPTR) low |
|
82H |
|
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|
00H |
|
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|
AF |
AE |
AD |
AC |
AB |
AA |
A9 |
A8 |
|
IE(1) |
Interrupt enable |
|
A8H |
EA |
— |
— |
ES |
ET1 |
EX1 |
ET0 |
EX0 |
0XX00000B |
|
|
|
|
BF |
BE |
BD |
BC |
BB |
BA |
B9 |
B8 |
|
IP(1) |
Interrupt priority |
|
B8H |
— |
— |
— |
PS |
PT1 |
PX1 |
PT0 |
PX0 |
XXX00000B |
|
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|
87 |
86 |
85 |
84 |
83 |
82 |
81 |
80 |
|
P0(1) |
Port 0 |
|
80H |
P0.7 |
P0.6 |
P0.5 |
P0.4 |
P0.3 |
P0.2 |
P0.1 |
P0.0 |
FFH |
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AD7 |
AD6 |
AD5 |
AD4 |
AD3 |
AD2 |
AD1 |
AD0 |
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97 |
96 |
95 |
94 |
93 |
92 |
91 |
90 |
|
P1(1) |
Port 1 |
|
90H |
P1.7 |
P1.6 |
P1.5 |
P1.4 |
P1.3 |
P1.2 |
P1.1 |
P1.0 |
FFH |
|
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|
A7 |
A6 |
A5 |
A4 |
A3 |
A2 |
A1 |
A0 |
|
P2(1) |
Port 2 |
|
A0H |
P2.7 |
P2.6 |
P2.5 |
P2.4 |
P2.3 |
P2.2 |
P2.1 |
P2.0 |
FFH |
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AD15 |
AD14 |
AD13 |
AD12 |
AD11 |
AD10 |
AD9 |
AD8 |
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B7 |
B6 |
B5 |
B4 |
B3 |
B2 |
B1 |
B0 |
|
P3(1) |
Port 3 |
|
B0H |
P3.7 |
P3.6 |
P3.5 |
P3.4 |
P3.3 |
P3.2 |
P3.1 |
P3.0 |
FFH |
|
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|
RD |
WR |
T1 |
T0 |
INT1 |
INT0 |
TXD |
RXD |
|
PCON |
Power control |
|
87H |
SMOD |
— |
— |
— |
GF1 |
GF0 |
PD |
IDL |
0XXX0000B |
|
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|
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
|
PSW(1) |
Program status word |
|
D0H |
CY |
AC |
F0 |
RS1 |
RS0 |
OV |
— |
P |
00H |
SBUF |
Serial data buffer |
|
99H |
|
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|
XXXXXXXXB |
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|
9F |
9E |
9D |
9C |
9B |
9A |
99 |
98 |
|
SCON(1) |
Serial controller |
|
98H |
SM0 |
SM1 |
SM2 |
REN |
TB8 |
RB8 |
TI |
RI |
00H |
SP |
Stack pointer |
|
81H |
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07H |
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|
8F |
8E |
8D |
8C |
8B |
8A |
89 |
88 |
|
TCON(1) |
Timer control |
|
88H |
TF1 |
TR1 |
TF0 |
TR0 |
IE1 |
IT1 |
IE0 |
IT0 |
00H |
TMOD |
Timer mode |
|
89H |
GATE |
C/T |
M1 |
M0 |
GATE |
C/T |
M1 |
M0 |
00H |
TH0 |
Timer high 0 |
|
8CH |
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|
00H |
TH1 |
Timer high 1 |
|
8DH |
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|
00H |
TL0 |
Timer low 0 |
|
8AH |
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|
00H |
TL1 |
Timer low 1 |
|
8BH |
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00H |
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Note:
1. Denotes bit addressable.
10 |
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
MC003-1D 11/19/98
IS80C51
IS80C31
The detail description of each bit is as follows:
PSW:
Program Status Word. Bit Addressable.
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
CY |
AC |
F0 |
RS1 |
RS0 |
OV |
— |
P |
Register Description: |
|
|
|
|
|||
CY |
PSW.7 |
|
Carry flag. |
|
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AC |
PSW.6 |
|
Auxiliary carry flag. |
|
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|
||||
F0 |
PSW.5 |
|
Flag 0 available to the user for general |
||||
|
|
|
purpose. |
|
|
|
|
RS1 |
PSW.4 |
|
Register bank selector bit 1.(1) |
|
|||
RS0 |
PSW.3 |
|
Register bank selector bit 0.(1) |
|
|||
OV |
PSW.2 |
|
Overflow flag. |
|
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|
||||
— |
PSW.1 |
|
Usable as a general purpose flag |
||||
|
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|
||||
P |
PSW.0 |
|
Parity flag. Set/Clear by hardware each |
||||
|
|
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instruction cycle to indicate an odd/even |
||||
|
|
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number of “1” bits in the accumulator. |
||||
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|
|
Note:
1.The value presented by RS0 and RS1 selects the corresponding register bank.
RS1 |
RS0 |
Register Bank |
Address |
0 |
0 |
0 |
00H-07H |
|
|
|
|
0 |
1 |
1 |
08H-0FH |
|
|
|
|
1 |
0 |
2 |
10H-17H |
|
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|
1 |
1 |
3 |
18H-1FH |
|
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|
|
PCON:
Power Control Register. Not Bit Addressable.
7 |
6 |
|
5 |
4 |
3 |
2 |
1 |
0 |
SMOD — |
— |
— |
GF1 |
GF0 |
PD |
IDL |
|
|
Register |
|
Description: |
|
|
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|
||
|
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|
||||||
SMOD |
|
Double baud rate bit. If Timer 1 is used to generate |
||||||
|
|
baud rate and SMOD=1, the baud rate is doubled |
||||||
|
|
when the serial port is used in modes 1, 2, or 3. |
||||||
|
|
|
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|
|
—Not implemented, reserve for future use.(1)
—Not implemented, reserve for future use.(1)
—Not implemented, reserve for future use.(1)
GF1 |
General purpose flag bit. |
GF0 |
General purpose flag bit. |
|
|
PD |
Power-down bit. Setting this bit activates power- |
|
down mode. |
|
|
IDL |
Idle mode bit. Setting this bit activates idle mode. |
|
If 1s are written to PD and IDL at the same time, |
|
PD takes precedence. |
|
|
IE:
Interrupt Enable Register. Bit Addressable.
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
EA |
— |
— |
ES |
ET1 |
EX1 ET0 |
|
EX0 |
Register Description: |
|
|
|
|
|||
EA |
IE.7 |
|
Disable all interrupts. If EA=0, no |
||||
|
|
|
interrupt will be acknowledged. If EA=1, |
||||
|
|
|
each interrupt source is individually |
||||
|
|
|
enabled or disabled by setting or |
||||
|
|
|
clearing its enable bit. |
|
|
||
— |
IE.6 |
|
Not implemented, reserve for future |
||||
|
|
|
use.(5) |
|
|
|
|
— |
IE.5 |
|
Not implemented, reserve for future |
||||
|
|
|
use.(5) |
|
|
|
|
ES |
IE.4 |
|
Enable or disable the serial port |
||||
|
|
|
interrupt. |
|
|
|
|
ET1 |
IE.3 |
|
Enable or disable the timer 1 overflow |
||||
|
|
|
interrupt. |
|
|
|
|
EX1 |
IE.2 |
|
Enable or disable external interrupt 1. |
||||
ET0 |
IE.1 |
|
Enable or disable the timer 0 overflow |
||||
|
|
|
interrupt. |
|
|
|
|
EX0 |
IE.0 |
|
Enable or disable external interrupt 0. |
||||
|
|
|
|
|
|
|
|
Note: To use any of the interrupts in the 80C51 Family, the following three steps must be taken:
1.Set the EA (enable all) bit in the IE register to 1.
2.Set the coresponding individual interrupt enable bit in the IE register to 1.
3.Begin the interrupt service routine at the corresponding Vector Address of that interrupt (see below).
Interrupt Source |
Vector Address |
IE0 |
0003H |
|
|
TF0 |
000BH |
|
|
IE1 |
0013H |
|
|
TF1 |
001BH |
|
|
RI & TI |
0023H |
4.In addition, for external interrupts, pins INT0 and INT1 (P3.2 and P3.3) must be set to 1, and depending on whether the interrupt is to be level or transition activated, bits IT0 or IT1 in the TCON register may need to be set to 0 or 1.
ITX = 0 level activated (X = 0, 1) ITX = 1 transition activated
5.User software should not write 1s to reserved bits. These bits may be used in future products to invoke new features.
Note:
1.User software should not write 1s to reserved bits. These bits may be used in future products to invoke new features.
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
11 |
MC003-1D 11/19/98
IS80C51
IS80C31
IP:
Interrupt Priority Register. Bit Addressable.
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
—— — PS PT1 PX1 PT0 PX0
Register Description:
— |
IP.7 |
Not implemented, reserve for future use(3) |
— |
IP.6 |
Not implemented, reserve for future use(3) |
— |
IP.5 |
Not implemented, reserve for future use(3) |
PS |
IP.4 |
Defines Serial Port interrupt priority level |
PT1 |
IP.3 |
Defines Timer 1 interrupt priority level |
PX1 |
IP.2 |
Defines External Interrupt 1 priority level |
PT0 |
IP.1 |
Defines Timer 0 interrupt priority level |
PX0 |
IP.0 |
Defines External Interrupt 0 priority level |
|
|
|
Notes:
1.In order to assign higher priority to an interrupt the coresponding bit in the IP register must be set to 1. While an interrupt service is in progress, it cannot be interrupted by a lower or same level interrupt.
2.Priority within level is only to resolve simultaneous requests of the same priority level. From high to low, interrupt sources are listed below:
IE0
TF0
IE1
TF1
RI or TI
3.User software should not write 1s to reserved bits. These bits may be used in future products to invoke new features.
TCON:
Timer/Counter Control Register. Bit Addressable
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
TF1 |
TR1 |
TF0 |
TR0 |
IE1 |
IT1 |
IE0 |
IT0 |
Register Description: |
|
|
|
|
|||
|
|
|
|||||
TF1 |
TCON.7 |
Timer 1 overflow flag. Set by hardware |
|||||
|
|
|
when the Timer/Counter 1 overflows. |
||||
|
|
|
Cleared by hardware as processor |
||||
|
|
|
vectors to the interrupt service routine. |
||||
|
|
|
|||||
TR1 |
TCON.6 |
Timer 1 run control bit. Set/Cleared by |
|||||
|
|
|
software to turn Timer/Counter 1 ON/ |
||||
|
|
|
OFF. |
|
|
|
|
|
|
|
|||||
TF0 |
TCON.5 |
Timer 0 overflow flag. Set by hardware |
|||||
|
|
|
when the Timer/Counter 0 overflows. |
||||
|
|
|
Cleared by hardware as processor |
||||
|
|
|
vectors to the interrupt service routine. |
||||
|
|
|
|||||
TR0 |
TCON.4 |
Timer 0 run control bit. Set/Cleared by |
|||||
|
|
|
software to turn Timer/Counter 0 ON/ |
||||
|
|
|
OFF. |
|
|
|
|
|
|
|
|||||
IE1 |
TCON.3 |
External Interrupt 1 edge flag. Set by |
|||||
|
|
|
hardware when the External Interrupt |
||||
|
|
|
edge is detected. Cleared by hardware |
||||
|
|
|
when interrupt is processed. |
|
|||
|
|
|
|||||
IT1 |
TCON.2 |
Interrupt 1 type control bit. Set/Cleared |
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by software specify falling edge/low level |
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triggered External Interrupt. |
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IE0 |
TCON.1 |
External Interrupt 0 edge flag. Set by |
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hardware when the External Interrupt |
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edge is detected. Cleared by hardware |
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when interrupt is processed. |
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IT0 |
TCON.0 |
Interrupt 0 type control bit. Set/Cleared |
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by software specify falling edge/low level |
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triggered External Interrupt. |
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12 |
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
MC003-1D 11/19/98
IS80C51
IS80C31
TMOD:
Timer/Counter Mode Control Register.
Not Bit Addressable.
Timer 1 |
Timer 0 |
GATE C/T M1 M0 |
GATE C/T M1 M0 |
GATE When TRx (in TCON) is set and GATE=1, TIMER/ COUNTERx will run only while INTx pin is high (hardware control). When GATE=0, TIMER/ COUNTERx will run only while TRx=1 (software control).
C/T Timer or Counter selector. Cleared for Timer operation (input from internal system clock). Set for Counter operation (input from Tx input pin).
M1 Mode selector bit.(1)
M0 Mode selector bit.(1)
Note 1:
M1 |
M0 |
Operating mode |
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0 |
0 |
Mode 0. |
(13-bit Timer) |
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0 |
1 |
Mode 1. |
(16-bit Timer/Counter) |
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1 |
0 |
Mode 2. |
(8-bit auto-load Timer/Counter) |
11 Mode 3. (Splits Timer 0 into TL0 and TH0. TL0 is an 8-bit Timer/Counter controller by the standard Timer 0 control bits. TH0 is an 8-bit Timer and is controlled by Timer 1 control bits.)
1 |
1 |
Mode 3. (Timer/Counter 1 stopped). |
SCON:
Serial Port Control Register. Bit Addressable.
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
SM0 SM1 |
SM2 |
REN |
TB8 |
RB8 |
TI |
RI |
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Register Description: |
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SM0 |
SCON.7 |
Serial port mode specifier.(1) |
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SM1 |
SCON.6 |
Serial port mode specifier.(1) |
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SM2 |
SCON.5 |
Enable the multiprocessor com- |
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munication feature in mode 2 and 3. In |
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mode 2 or 3, if SM2 is set to 1 then RI will |
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not be activated if the received 9th data |
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bit (RB8) is 0. In mode 1, if SM2=1 then |
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RI will not be activated if valid stop bit |
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was not received. In mode 0, SM2 should |
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be 0. |
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REN |
SCON.4 |
Set/Cleared by software to Enable/ |
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Disable reception. |
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TB8 |
SCON.3 |
The 9th bit that will be transmitted in |
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mode 2 and 3. Set/Cleared by software. |
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RB8 |
SCON.2 |
In modes 2 and 3, RB8 is the 9th data bit |
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that was received. In mode 1, if SM2=0, |
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RB8 is the stop bit that was received. In |
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mode 0, RB8 is not used. |
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TI |
SCON.1 |
Transmit interrupt flag. Set by hardware |
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at the end of the 8th bit time in mode 0, |
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or at the beginning of the stop bit in the |
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other modes. Must be cleared by |
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software. |
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RI |
SCON.0 |
Receive interrupt flag. Set by hardware |
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at the end of the 8th bit time in mode 0, |
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or halfway through the stop bit time in |
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the other modes (except see SM2). Must |
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be cleared by software. |
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Note: |
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SM0 |
SM1 MODE |
Description |
Baud rate |
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0 |
0 |
0 |
Shift register |
Fosc/12 |
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0 |
1 |
1 |
8-bit UART |
Variable |
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1 |
0 |
2 |
9-bit UART |
Fosc/64 or Fosc/32 |
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1 |
1 |
3 |
9-bit UART |
Variable |
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Integrated Silicon Solution, Inc. — 1-800-379-4774 |
13 |
MC003-1D 11/19/98