ISSI IS62U6416LL-20BI, IS62U6416LL-20B, IS62U6416LL-20TI, IS62U6416LL-20T, IS62U6416LL-20KI Datasheet

IS62U6416LL				®
IS62U6416LL		ISSI

64K x 16 LOW VOLTAGE,

ULTRA-LOW POWER CMOS STATIC RAM

ADVANCE INFORMATION

DECEMBER 1998

FEATURES

•Access time: 200 ns

•CMOS low power operation

–40 mW (typical) operating

–90 μW (typical) standby

•TTL compatible interface levels

•Single 1.8V-2.7V power supply

•Fully static operation: no clock or refresh required

•Three state outputs

•Data control for upper and lower bytes

•Industrial temperature available

•Available in Jedec Std 44-pin SOJ package, 44-pin TSOP (Type II), and 48-pin mini BGA

DESCRIPTION

The ISSI IS62U6416LL is an ultra-low power, 1,048,576-bit static RAM organized as 65,536 words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques yields access times as fast as 200 ns with low power consumption.

When CEis HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels.

Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access.

FUNCTIONAL BLOCK DIAGRAM

A0-A15

DECODER

64K x 16

MEMORY ARRAY

VCC

GND

I/O0-I/O7

I/O

Lower Byte

COLUMN I/O

DATA

I/O8-I/O15

CIRCUIT

Upper Byte

CE

OE

CONTROL

WE

CIRCUIT

UB

LB

The specification contains ADVANCE INFORMATION. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.

Integrated Silicon Solution, Inc. — 1-800-379-4774

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ADVANCE INFORMATION SR034-0C 12/09/98

IS62U6416LL

PIN CONFIGURATIONS

44-Pin SOJ 44-Pin TSOP

						44		A5
		A4			1
		A3				43		A6
					2
		A2				42		A7
					3
		A1				41
					4					OE
		A0				40
					5				UB
		CE			6	39		LB
I/O0						38		I/O15
					7
I/O1					8	37		I/O14
I/O2						36		I/O13
					9
I/O3						35		I/O12
					10
Vcc						34		GND
					11
GND						33		Vcc
					12
I/O4						32		I/O11
					13
I/O5					14	31		I/O10
I/O6					15	30		I/O9
I/O7					16	29		I/O8
					17	28		NC
	WE
A15					18	27		A8
A14					19	26		A9
A13					20	25		A10
A12					21	24		A11
	NC				22	23		NC

	A4			1	44		A5
	A3			2	43		A6
	A2			3	42		A7
	A1			4	41
								OE
	A0			5	40
								UB
	CE			6	39
								LB
I/O0				7	38		I/O15
I/O1				8	37		I/O14
I/O2				9	36		I/O13
I/O3				10	35		I/O12
	Vcc			11	34		GND
GND				12	33		Vcc
I/O4				13	32		I/O11
I/O5				14	31		I/O10
I/O6				15	30		I/O9
I/O7				16	29		I/O8
				17	28		NC
	WE
A15				18	27		A8
A14				19	26		A9
A13				20	25		A10
A12				21	24		A11
	NC			22	23		NC

	48-Pin mini BGA (Top View)							PIN DESCRIPTIONS
		1	2	3	4	5	6	A0-A15	Address Inputs
								I/O0-I/O15	Data Inputs/Outputs
								CE	Chip Enable Input
	A							OE	Output Enable Input
		LB	OE	A0	A1	A2	N/C	WE	Write Enable Input
		I/O					I/O
	B		UB	A3	A4	CE			Lower-byte Control (I/O0-I/O7)
		8					0	LB
	C	I/O	I/O	A5	A6	I/O	I/O		Upper-byte Control (I/O8-I/O15)
		9	10			1	2	UB
	D	GND	I/O	NC	A7	I/O	Vcc	NC	No Connection
			11			3
	E	Vcc	I/O	NC	NC	I/O	GND	Vcc	Power
			12			4
	F	I/O	I/O	A14	A15	I/O	I/O	GND	Ground
		14	13			5	6
	G	I/O	NC	A12	A13	WE	I/O
		15					7
	H	NC	A8	A9	A10	A11	NC

2 Integrated Silicon Solution, Inc. — 1-800-379-4774

ADVANCE INFORMATION SR034-0C 12/09/98

IS62U6416LL

TRUTH TABLE

						I/O Pin
Mode	WE	CE	OE	LB	UB	I/O0-I/O7	I/O8-I/O15	Vcc Current
Not Selected	X	H	X	X	X	High-Z	High-Z	ISB1, ISB2
Output Disabled	H	L	H	X	X	High-Z	High-Z	ICC
	X	L	X	H	H	High-Z	High-Z
Read	H	L	L	L	H	DOUT	High-Z	ICC
	H	L	L	H	L	High-Z	DOUT
	H	L	L	L	L	DOUT	DOUT
Write	L	L	X	L	H	DIN	High-Z	ICC
	L	L	X	H	L	High-Z	DIN
	L	L	X	L	L	DIN	DIN

AC TEST CONDITIONS

	Parameter	Unit
	Input Pulse Level	0.4 to 1.8V(1)
	Input Rise and Fall Times	5 ns
	Input and Output Timing and Reference Level	0.9V(1)
	Output Load	See Figures 1 and 2
AC TEST LOADS

3070 Ω	3070 Ω	THEVENIN EQUIVALENT
1.8V	1.8V		1554 Ω
		OUTPUT	0.91V
OUTPUT	OUTPUT

100 pF

3150 Ω

30 pF

3150 Ω

Figure 3.

Including

Including

jig and

jig and

scope

scope

Figure 1.

Figure 2.

Integrated Silicon Solution, Inc. — 1-800-379-4774

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ADVANCE INFORMATION SR034-0C 12/09/98