ISSI IS62LV5128LL-85BI, IS62LV5128LL-70B, IS62LV5128LL-85B, IS62LV5128LL-70BI Datasheet

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IS62LV5128LL

ISSI®

512K x 8 LOW POWER and LOW Vcc CMOS STATIC RAM

MAY 2001

FEATURES

•Access times of 70, 85 ns

•CMOS low power operation:

—135 mW (typical) operating

—16.5 µW (typical) standby

•Low data retention voltage: 2V (min.)

DESCRIPTION

The ISSI IS62LV5128LL is a low voltage, 524,288 words by 8 bits, CMOS SRAM. It is fabricated using ISSI’s low voltage, sixtransistor(6T),CMOS technology. The deviceis targeted to satisfy the demands of the state-of-the-art technologies such as cell phones and pagers.

•Output Enable (OE) and Chip Enable (CE) inputs for ease in applications

•TTL compatible inputs and outputs

•Fully static operation:

— No clock or refresh required

•Single2.7V(min)to3.15V(max)VCCpowersupply

•Availablein36-pinminiBGA

FUNCTIONAL BLOCK DIAGRAM

When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Additionally, easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory.

The IS62LV5128LL is available in a 36-pin mini BGA package (8mm x 10mm).

A0-A18		512K x 8
	DECODER	512K x 8
	DECODER	MEMORY ARRAY
		MEMORY ARRAY

VCC

GND

I/O

I/O0-I/O7 DATA COLUMN I/O

CIRCUIT

OE CONTROL

CIRCUIT

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. D

05/04/01

IS62LV5128LL

ISSI®

PIN CONFIGURATION

36-pin mini BGA (B)

A	A0	A1	NC	A3	A6	A8
B	I/O4	A2	WE	A4	A7	I/O0
C	I/O5		NC	A5		I/O1
D	GND					Vcc
E	Vcc					GND
F	I/O6		A18	A17		I/O2
G	I/O7	OE	CE	A16	A15	I/O3
H	A9	A10	A11	A12	A13	A14

PIN DESCRIPTIONS

A0-A18	Address Inputs

CE	Chip Enable Input

OE	Output Enable Input

WE	Write Enable Input

I/O0-I/O7	Input/Output

NC	No Connection

Vcc	Power

GND	Ground

TRUTH TABLE

Mode	WE	CE	OE	I/O Operation	Vcc Current

Not Selected	X	H	X	High-Z	ISB1, ISB2

Output Disabled	H	L	H	High-Z	ICC
Read	H	L	L	DOUT	ICC

Write	L	L	X	DIN	ICC

OPERATING RANGE

Range	Ambient Temperature	VCC Min.	VCC Max.
Commercial	0°C to +70°C	2.7V	3.15V

Industrial	–40°C to +85°C	2.7V	3.15V

2 Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. D

05/04/01

IS62LV5128LL				ISSI®
ABSOLUTE MAXIMUM RATINGS(1)

Symbol	Parameter	Value	Unit
VTERM	Terminal Voltage with Respect to GND	–0.5 to Vcc + 0.3	V

VCC	Vcc related to GND	–0.3 to +3.3	V

TBIAS	Temperature Under Bias	–40 to +85	°C

TSTG	Storage Temperature	–65 to +150	°C

PT	Power Dissipation	1	W
Note:

1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

CAPACITANCE(1,2)

Symbol	Parameter	Conditions	Max.	Unit
CIN	Input Capacitance	VIN = 0V	6	pF

COUT	Output Capacitance	VOUT = 0V	8	pF

Notes:

1.Tested initially and after any design or process changes that may affect these parameters.

2.Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.0V.

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol	Parameter	Test Conditions	Min.	Max.	Unit
VOH	Output HIGH Voltage	VCC = 3.0V, IOH = –1.0 mA	2.2	—	V

VOL	Output LOW Voltage	VCC = 3.0V, IOL = 2.1 mA	—	0.4	V
VIH	Input HIGH Voltage		2.2	VCC + 0.3	V

VIL	Input LOW Voltage(1)		–0.2	0.4	V
ILI	Input Leakage	GND ≤ VIN ≤ VCC	–1	1	µA
ILO	Output Leakage	GND ≤ VOUT ≤ VCC, OUTPUTS Disabled	–1	1	µA

Note:

1. VIL = –2.0V for pulse width less than 10 ns.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. D

05/04/01

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