ISSI IS62LV2568ALL-85T, IS62LV2568ALL-85HI, IS62LV2568ALL-85H, IS62LV2568ALL-85BI, IS62LV2568ALL-70T Datasheet

IS62LV2568ALL

ISSI ®

256K x 8 LOW POWER and LOW Vcc CMOS STATIC RAM

AUGUST 2001

FEATURES

•Access times of 70 and 85 ns

•CMOS low power operation:

—120 mW (typical) operating

—6 µW (typical) standby

•Low data retention voltage: 2V (min.)

•Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications

•TTL compatible inputs and outputs

•Fully static operation:

—No clock or refresh required

•Single 2.5V (min.) to 3.3V (max.) power supply

•Available in 32-pin TSOP (Type I), STSOP (Type I), and 36-pin mini BGA

DESCRIPTION

The ISSI IS62LV2568ALL is a low voltage, 262,144 words by 8 bits, CMOS SRAM. It is fabricated using ISSI'’s low voltage, six transistor (6T), CMOS technology. The device is targeted to satisfy the demands of the state-of-the-art technologies such as cell phones and pagers.

When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipationcan be reduced down with CMOS input levels. Additionally, easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory.

The IS62LV2568ALL is available in 32-pin TSOP (Type I), STSOP (Type I), and 36-pin mini BGA.

FUNCTIONAL BLOCK DIAGRAM

A0-A17	DECODER		256K x 8
			MEMORY ARRAY

VCC

GND

I/O

I/O0-I/O7 DATA COLUMN I/O

CIRCUIT

CE1

CONTROL

CE2

CIRCUIT

OE

WE

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.

Integrated Silicon Solution, Inc. — 1-800-379-4774

1

Rev. B

08/01/01

IS62LV2568ALL	ISSI®
PIN CONFIGURATION
36-pin mini BGA (B)	PIN DESCRIPTIONS

1

2

3

4

5

6

A	A0	A1	CE2	A3	A6	A8
B	I/O4	A2	WE	A4	A7	I/O0
C	I/O5		NC	A5		I/O1
D	GND					Vcc
E	Vcc					GND
F	I/O6		NC	A17		I/O2
G	I/O7	OE	CE1	A16	A15	I/O3
H	A9	A10	A11	A12	A13	A14

A0-A17	Address Inputs
CE1	Chip Enable 1 Input
CE2	Chip Enable 2 Input
OE	Output Enable Input
WE	Write Enable Input
I/O0-I/O7	Input/Output
NC	No Connection
Vcc	Power
GND	Ground

32-Pin TSOP (Type I), STSOP (Type I)

A11	1		32		OE
A9		2	31		A10
A8		3	30
						CE1
A13		4	29		I/O7
WE		5	28		I/O6
CE2		6	27		I/O5
A15		7	26		I/O4
VCC		8	25		I/O3
A17		9	24		GND
A16		10	23		I/O2
A14			22		I/O1
		11
A12			21		I/O0
		12
A7		13	20		A0
A6		14	19		A1
A5		15	18		A2
A4		16	17		A3

2 Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

08/01/01

IS62LV2568ALL

ISSI®

TRUTH TABLE

Mode	WE	CE1	CE2	OE	I/O Operation	Vcc Current
Not Selected	X	H	X	X	High-Z	ISB1, ISB2
(Power-down)	X	X	L	X	High-Z	ISB1, ISB2
Output Disabled	H	L	H	H	High-Z	ICC
Read	H	L	H	L	DOUT	ICC
Write	L	L	H	X	DIN	ICC

OPERATING RANGE

Range	Ambient Temperature	VCC MIN.	VCC MAX.
Commercial	0°C to +70°C	2.5V	3.3V
Industrial	–40°C to +85°C	2.5V	3.3V

ABSOLUTE MAXIMUM RATINGS(1)

Symbol	Parameter	Value	Unit
VTERM	Terminal Voltage with Respect to GND	–0.5 to Vcc + 0.5	V
VCC	Vcc related to GND	–0.3 to +3.6	V
TBIAS	Temperature Under Bias	–40 to +85	°C
TSTG	Storage Temperature	–65 to +150	°C
PT	Power Dissipation	0.7	W

Note:

1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

CAPACITANCE(1,2)

Symbol	Parameter	Conditions	Max.	Unit
CIN	Input Capacitance	VIN = 0V	6	pF
COUT	Output Capacitance	VOUT = 0V	8	pF

Notes:

1.Tested initially and after any design or process changes that may affect these parameters.

2.Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.0V.

Integrated Silicon Solution, Inc. — 1-800-379-4774

3

Rev. B

08/01/01