ISSI IS62LV1288LL-70TI, IS62LV1288LL-70Q, IS62LV1288LL-70HI, IS62LV1288LL-70H, IS62LV1288LL-55TI Datasheet

IS62LV1288LL

ISSI®

128K x 8 LOW POWER and LOW Vcc CMOS STATIC RAM

FEBUARY 2001

FEATURES

•Access times of 45, 55, and 70 ns

•Low active power: 60 mW (typical)

•Low standby power: 15 µW (typical) CMOS standby

•Low data retention voltage: 2V (min.)

•Ultra Low Power

•Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications

•TTL compatible inputs and outputs

•Single 2.5V (min.) to 3.45V (max.) power supply

•Industrial temperature available

•Available in 32-pin TSOP (Type I), 32-pin STSOP, and 450-mil SOP

DESCRIPTION

The ISSI IS62LV1288LL is a low power and low Vcc,131,072-word by 8-bit CMOS static RAM. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices.

When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels.

Easy memory expansion is provided by using two Chip Enable inputs, CE1and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory.

The IS62LV1288LL is available in 32-pin TSOP (Type I), STSOP (8 x 13.4mm), and 450-mil plastic SOP (525-mil pin to pin) packages.

FUNCTIONAL BLOCK DIAGRAM

A0-A16	DECODER		512 X 2048
			MEMORY ARRAY

VCC

GND

I/O

I/O0-I/O7 DATA COLUMN I/O

CIRCUIT

CE1
						CONTROL
CE2
OE						CIRCUIT
WE

This document contISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.

Integrated Silicon Solution, Inc. — 1-800-379-4774

1

Rev. A

03/22/01

IS62LV1288LL

ISSI®

PIN CONFIGURATION

32-Pin SOP (Q)

			32			VCC
NC		1
A16				31		A15
		2
A14				30		CE2
		3
A12				29
		4					WE
A7				28		A13
		5
A6			27			A8
		6
A5			26			A9
		7
A4		8	25			A11
A3			24
		9						OE
A2			23			A10
		10
A1			22
		11						CE1
A0			21			I/O7
		12
I/O0			20			I/O6
		13
I/O1			19			I/O5
		14
I/O2		15	18			I/O4
GND		16	17			I/O3

PIN DESCRIPTIONS

A0-A16	Address Inputs
CE1	Chip Enable 1 Input
CE2	Chip Enable 2 Input
OE	Output Enable Input
WE	Write Enable Input
I/O0-I/O7	Input/Output
NC	No Connection
Vcc	Power
GND	Ground

PIN CONFIGURATION

32-Pin TSOP (Type I) (T) and STSOP (Type 1) (H)

A11	1		32		OE
A9		2	31		A10
A8		3	30
						CE1
A13		4	29		I/O7
WE		5	28		I/O6
CE2		6	27		I/O5
A15		7	26		I/O4
VCC		8	25		I/O3
NC		9	24		GND
A16		10	23		I/O2
A14		11	22		I/O1
A12		12	21		I/O0
A7		13	20		A0
A6		14	19		A1
A5		15	18		A2
A4		16	17		A3

OPERATING RANGE

Range	Ambient Temperature	Speed	VCC MIN.	VCC MAX.
Commercial	0°C to +70°C	-45 ns	2.85V	3.15V
		-55 ns	2.5V	3.45V
		-70 ns	2.5V	3.45V
Industrial	–40°C to +85°C	-45 ns	2.85V	3.15V
		-55 ns	2.5V	3.45V
		-70 ns	2.5V	3.45V

2 Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

03/22/01

IS62LV1288LL							ISSI®
TRUTH TABLE
Mode	WE	CE1	CE2	OE	I/O Operation	Vcc Current
Not Selected	X	H	X	X	High-Z	ISB1, ISB2
(Power-down)	X	X	L	X	High-Z	ISB1, ISB2
Output Disabled	H	L	H	H	High-Z	ICC
Read	H	L	H	L	DOUT	ICC
Write	L	L	H	X	DIN	ICC

ABSOLUTE MAXIMUM RATINGS(1)

Symbol	Parameter	Value	Unit
VTERM	Terminal Voltage with Respect to GND	–0.5 to Vcc + 0.5	V
VCC	Vcc related to GND	–0.3 to +3.6	V
TBIAS	Temperature Under Bias	–40 to +85	°C
TSTG	Storage Temperature	–65 to +150	°C
PT	Power Dissipation	0.7	W

Notes:

1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

CAPACITANCE(1,2)

Symbol	Parameter	Conditions	Max.	Unit
CIN	Input Capacitance	VIN = 0V	6	pF
COUT	Output Capacitance	VOUT = 0V	8	pF

Notes:

1.Tested initially and after any design or process changes that may affect these parameters.

2.Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.0V.

Integrated Silicon Solution, Inc. — 1-800-379-4774

3

Rev. A

03/22/01