IS62LV1024LL |
ISSI® |
128K x 8 LOW POWER and LOW Vcc CMOS STATIC RAM
JANUARY 2001
FEATURES
•Access times of 45, 55, and 70 ns
•Low active power: 60 mW (typical)
•Low standby power: 15 µW (typical) CMOS standby
•Low data retention voltage: 2V (min.)
•Ultra Low Power
•Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications
•TTL compatible inputs and outputs
•Single 2.5V to 3.3V
•Industrial temperature available
•Available in 32-pin TSOP (Type I), 32-pin STSOP, and 450-mil SOP
DESCRIPTION
The ISSI IS62LV1024LL is a low power and low Vcc,131,072-word by 8-bit CMOS static RAM. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices.
When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip Enable inputs, CE1and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory.
The IS62LV1024LL is available in 32-pin TSOP (Type I), STSOP (8 x 13.4mm), and 450-mil plastic SOP (525-mil pin to pin) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A16 |
DECODER |
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512 X 2048 |
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MEMORY ARRAY |
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VCC
GND
I/O
I/O0-I/O7 DATA COLUMN I/O
CIRCUIT
CE1 |
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CONTROL |
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CE2 |
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OE |
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CIRCUIT |
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WE |
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This document contISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
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Rev. H
01/31/01
IS62LV1024LL |
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ISSI® |
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PIN CONFIGURATION |
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PIN CONFIGURATION |
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32-Pin SOP (Q) |
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32-Pin TSOP (Type I) (T) and STSOP (Type 1) (H) |
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NC |
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1 |
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32 |
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VCC |
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A11 |
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1 |
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OE |
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A16 |
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2 |
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31 |
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A15 |
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A9 |
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2 |
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A10 |
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A14 |
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3 |
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30 |
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CE2 |
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A8 |
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3 |
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CE1 |
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A12 |
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4 |
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29 |
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A13 |
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4 |
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I/O7 |
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WE |
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A7 |
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5 |
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28 |
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A13 |
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WE |
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5 |
28 |
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I/O6 |
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A6 |
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6 |
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27 |
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A8 |
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CE2 |
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6 |
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I/O5 |
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A5 |
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7 |
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A9 |
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A15 |
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7 |
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I/O4 |
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A4 |
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8 |
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25 |
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A11 |
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VCC |
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8 |
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I/O3 |
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A3 |
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NC |
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GND |
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OE |
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A2 |
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23 |
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A10 |
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A16 |
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I/O2 |
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A1 |
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A14 |
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I/O1 |
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CE1 |
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A0 |
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I/O7 |
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A12 |
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I/O0 |
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I/O0 |
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I/O6 |
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A7 |
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A0 |
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I/O1 |
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I/O5 |
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A6 |
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A1 |
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I/O2 |
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I/O4 |
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A5 |
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A2 |
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GND |
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I/O3 |
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A4 |
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A3 |
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PIN DESCRIPTIONS
A0-A16 |
Address Inputs |
CE1 |
Chip Enable 1 Input |
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CE2 |
Chip Enable 2 Input |
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OE |
Output Enable Input |
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WE |
Write Enable Input |
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I/O0-I/O7 |
Input/Output |
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NC |
No Connection |
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Vcc |
Power |
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GND |
Ground |
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OPERATING RANGE
Range |
Ambient Temperature |
Speed |
VCC |
Commercial |
0°C to +70°C |
-45 ns |
2.85V to 3.15V |
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-55 ns |
2.5V to 3.3V |
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-70 ns |
2.5V to 3.3V |
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Industrial |
–40°C to +85°C |
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2.5V to 3.3V |
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2 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. H
01/31/01
IS62LV1024LL |
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ISSI® |
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TRUTH TABLE |
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Mode |
WE |
CE1 |
CE2 |
OE |
I/O Operation |
Vcc Current |
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Not Selected |
X |
H |
X |
X |
High-Z |
ISB1, ISB2 |
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(Power-down) |
X |
X |
L |
X |
High-Z |
ISB1, ISB2 |
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Output Disabled |
H |
L |
H |
H |
High-Z |
ICC |
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Read |
H |
L |
H |
L |
DOUT |
ICC |
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Write |
L |
L |
H |
X |
DIN |
ICC |
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ABSOLUTE MAXIMUM RATINGS(1)
Symbol |
Parameter |
Value |
Unit |
VTERM |
Terminal Voltage with Respect to GND |
–0.5 to Vcc + 0.5 |
V |
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VCC |
Vcc related to GND |
–0.3 to +3.6 |
V |
TBIAS |
Temperature Under Bias |
–40 to +85 |
°C |
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TSTG |
Storage Temperature |
–65 to +150 |
°C |
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PT |
Power Dissipation |
0.7 |
W |
Notes:
1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol |
Parameter |
Conditions |
Max. |
Unit |
CIN |
Input Capacitance |
VIN = 0V |
6 |
pF |
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COUT |
Output Capacitance |
VOUT = 0V |
8 |
pF |
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Notes:
1.Tested initially and after any design or process changes that may affect these parameters.
2.Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.0V.
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
3 |
Rev. H
01/31/01