ISSI IS62C1024-70T, IS62C1024-70QI, IS62C1024-70Q, IS62C1024-55TI, IS62C1024-55T Datasheet

IS62C1024	ISSI®
128K x 8 HIGH-SPEED CMOS STATIC RAM	JANUARY 2000

FEATURES

•High-speed access time: 35, 45, 55, 70 ns

•Low active power: 450 mW (typical)

•Low standby power: 500 µW (typical) CMOS standby

•Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications

•Fully static operation: no clock or refresh required

•TTL compatible inputs and outputs

•Single 5V (±10%) power supply

DESCRIPTION

The ISSI IS62C1024 is a low power,131,072-word by 8-bit CMOS static RAM. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices.

When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels.

Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory.

The IS62C1024 is available in 32-pin 525-mil plastic SOP and TSOP (type 1) packages.

FUNCTIONAL BLOCK DIAGRAM

A0-A16			512 X 2048
	DECODER
			MEMORY ARRAY

VCC

GND

I/O

I/O0-I/O7 DATA COLUMN I/O

CIRCUIT

CE1

CONTROL

CE2

CIRCUIT

OE

WE

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.

Integrated Silicon Solution, Inc. — 1-800-379-4774

1

Rev. G

01/14/00

IS62C1024

ISSI®

PIN CONFIGURATION

32-Pin SOP

				32		VCC
NC		1
A16				31		A15
		2
A14				30		CE2
		3
A12				29
		4					WE
A7			ISSI	28		A13
		5
A6			62C1024	27		A8
		6
A5				26		A9
		7
A4		8		25		A11
A3				24
		9						OE
A2				23		A10
		10
A1				22
		11						CE1
A0				21		I/O7
		12
I/O0				20		I/O6
		13
I/O1		14		19		I/O5
I/O2		15		18		I/O4
GND		16		17		I/O3

PIN DESCRIPTIONS

A0-A16	Address Inputs
CE1	Chip Enable 1 Input
CE2	Chip Enable 2 Input
OE	Output Enable Input
WE	Write Enable Input
I/O0-I/O7	Input/Output
Vcc	Power
GND	Ground

32-Pin TSOP (Type 1)

A11	1		32		OE
A9		2	31		A10
A8		3	30
						CE1
A13		4	29		I/O7
WE		5	28		I/O6
CE2		6	27		I/O5
A15		7	26		I/O4
VCC		8	25		I/O3
NC		9	24		GND
A16		10	23		I/O2
A14		11	22		I/O1
A12		12	21		I/O0
A7		13	20		A0
A6		14	19		A1
A5		15	18		A2
A4		16	17		A3

OPERATING RANGE

Range	Ambient Temperature	VCC
Commercial	0°C to +70°C	5V ± 10%
Industrial	–40°C to +85°C	5V ± 10%
2		Integrated Silicon Solution, Inc. — 1-800-379-4774
			Rev. G
		01/14/00

IS62C1024							ISSI®
TRUTH TABLE
Mode	WE	CE1	CE2	OE	I/O Operation	Vcc Current
Not Selected	X	H	X	X	High-Z	ISB1, ISB2
(Power-down)	X	X	L	X	High-Z	ISB1, ISB2
Output Disabled	H	L	H	H	High-Z	ICC
Read	H	L	H	L	DOUT	ICC
Write	L	L	H	X	DIN	ICC

ABSOLUTE MAXIMUM RATINGS(1)

Symbol	Parameter	Value	Unit
VTERM	Terminal Voltage with Respect to GND	–0.5 to +7.0	V
TBIAS	Temperature Under Bias	–10 to +85	°C
TSTG	Storage Temperature	–65 to +150	°C
PT	Power Dissipation	1.5	W
IOUT	DC Output Current (LOW)	20	mA

Notes:

1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

CAPACITANCE(1,2)

Symbol	Parameter	Conditions	Max.	Unit
CIN	Input Capacitance	VIN = 0V	6	pF
COUT	Output Capacitance	VOUT = 0V	8	pF

Notes:

1.Tested initially and after any design or process changes that may affect these parameters.

2.Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol	Parameter	Test Conditions		Min.	Max.	Unit
VOH	Output HIGH Voltage	VCC = Min., IOH = –1.0 mA		2.4	—	V
VOL	Output LOW Voltage	VCC = Min., IOL = 2.1 mA		—	0.4	V
VIH	Input HIGH Voltage			2.2	VCC + 0.5	V
VIL	Input LOW Voltage(1)	GND ≤ VIN ≤ VCC		–0.3	0.8	V
ILI	Input Leakage		Com.	–5	5	µA
		GND ≤ VOUT ≤ VCC	Ind.	–10	10
ILO	Output Leakage		Com.	–5	5	µA
			Ind.	–10	10

Notes:

1. VIL = –3.0V for pulse width less than 10 ns.

Integrated Silicon Solution, Inc. — 1-800-379-4774

3

Rev. G

01/14/00