ISSI IS61SP6436-117TQI, IS61SP6436-117TQ, IS61SP6436-117PQI, IS61SP6436-117PQ, IS61SP6436-6TQI Datasheet

		ISSI
IS61SP6436					®
IS61SP6436

64K x 36 SYNCHRONOUS PIPELINED STATIC RAM

FEATURES

•Internal self-timed write cycle

•Individual Byte Write Control and Global Write

•Clock controlled, registered address, data and control

•Pentium™ or linear burst sequence control using MODE input

•Three chip enables for simple depth expansion and address pipelining

•Common data inputs and data outputs

•Power-down control by ZZ input

•JEDEC 100-Pin TQFP and PQFP package

•Single +3.3V power supply

JULY 1999

DESCRIPTION

The ISSI IS61SP6436 is a high-speed, low-power synchronous static RAM designed to provide a burstable, highperformance, secondary cache for the i486™, Pentium™, 680X0™, and PowerPC™ microprocessors. It is organized as 65,536 words by 36 bits, fabricated with ISSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.

Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs.

•Two Clock enables and one Clock disable to eliminate multiple bank bus contention.

•Control pins mode upon power-up:

–MODE in interleave burst mode

–ZZ in normal operation mode

These control pins can be connected to GNDQ or VCCQ to alter their power-up state

FAST ACCESS TIME

Separate byte enables allow individual bytes to be written. BW1 controls DQP1 and DQ1-DQ8, BW2 controls DQP2 and DQ9-DQ16, BW3 controls DQP3 and DQ17-DQ24, BW4 controls DQP4 and DQ25-DQ32, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written.

Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IS61SP6436 and controlled by the ADV (burst address advance) input pin.

Asynchronous signals include output enable (OE), sleep mode input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH input on the ZZ pin puts the SRAM in the power-down state. When ZZ is pulled LOW (or no connect), the SRAM normally operates after three cycles of the wake-up period. A LOW input, i.e., GNDQ, on MODE pin selects LINEAR Burst. A VCCQ (or no connect) on MODE pin selects INTERLEAVED Burst.

Symbol	Parameter	-133	-117	-5	-6	-7	-8	Unit
tKQ	Clock Access Time	5	5	5	6	7	8	ns
tKC	Cycle Time	7.5	8.5	10	12	13	15	ns
	Frequency	133	117	100	83	75	66	MHz

This document contains PRELIMINARY data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1997, Integrated Silicon Solution, Inc.

Integrated Silicon Solution, Inc.

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SR029-1C 08/11/99

IS61SP6436

BLOCK DIAGRAM

				MODE
CLK		CLK	Q0	A0	A0'
		BINARY
		COUNTER			A1'
ADV	CE		Q1	A1
					64K x 36
ADSC
	CLR				MEMORY
ADSP
					ARRAY
A15-A0	16	Q		14	16
	D
	ADDRESS
	REGISTER
	CE
		CLK			36	36
GW	D	DQP4 Q
BWE	DQ32-DQ25
BW4
	BYTE WRITE
	REGISTERS
		CLK
	D	DQP3 Q
BW3	DQ24-DQ17
	BYTE WRITE
	REGISTERS
		CLK
	D	DQP2 Q
BW2	DQ16-DQ9
	BYTE WRITE
	REGISTERS
		CLK
	D	DQP1 Q
BW1		DQ8-DQ1
	BYTE WRITE
	REGISTERS
		CLK
CE					4
CE2	D	Q			INPUT	OUTPUT	36
CE2		ENABLE			REGISTERS	REGISTERS	DATA[36:1]
							OE
	REGISTER				CLK	CLK
	CE
		CLK
	D	Q
		ENABLE
		DELAY
	REGISTER
		CLK
OE
2						Integrated Silicon Solution, Inc.
							SR029-1C
							08/11/99

IS61SP6436

PIN CONFIGURATION

100-Pin TQFP and PQFP (Top View)

	A6	A7 CE	CE2	BW4 BW3 BW2 BW1 CE2 VCC		GND CLK GW BWE OE ADS C ADSP ADV A8		A9
	100 99 98 97			96 95 94 93	92 91 90 89 88 87 86		85 84 83 82 81
DQP3	1							80
DQ17	2							79
DQ18	3							78
VCCQ	4							77
GNDQ	5							76
DQ19	6							75
DQ20	7							74
DQ21	8							73
DQ22	9							72
GNDQ	10							71
VCCQ	11							70
DQ23	12							69
DQ24	13							68
VCCQ	14							67
VCC	15							66
NC	16							65
GND	17							64
DQ25	18							63
DQ26	19							62
VCCQ	20							61
GNDQ	21							60
DQ27	22							59
DQ28	23							58
DQ29	24							57
DQ30	25							56
GNDQ	26							55
VCCQ	27							54
DQ31	28							53
DQ32	29							52
DQP4	30							51
	31 32 33		34 35 36 37 38 39 40			41 42 43 44 45 46 47 48 49 50
	MODE	A5 A4	A3	A2 A1 A0 NC	NC GND	VCC NC NC A10 A11	A12 A13 A14 A15	NC

DQP2

DQ16

DQ15 VCCQ GNDQ DQ14 DQ13 DQ12 DQ11 GNDQ VCCQ DQ10 DQ9 GND NC VCC ZZ DQ8 DQ7 VCCQ GNDQ DQ6 DQ5 DQ4 DQ3 GNDQ VCCQ DQ2 DQ1 DQP1

PIN DESCRIPTIONS

A0-A15	Address Inputs
CLK	Clock
ADSP	Processor Address Status
ADSC	Controller Address Status
ADV	Burst Address Advance
BW1-BW4	Synchronous Byte Write Enable
BWE	Byte Write Enable
GW	Global Write Enable
CE, CE2, CE2	Synchronous Chip Enable
OE	Output Enable

DQ1-DQ32	Data Input/Output
DQP1-DQP4	Parity Inputs/Outputs
ZZ	Sleep Mode
MODE	Burst Sequence Mode
VCC	+3.3V Power Supply
GND	Ground
VCCQ	Isolated Output Buffer Supply:
	+3.3V
GNDQ	Isolated Output Buffer Ground

Integrated Silicon Solution, Inc.

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SR029-1C 08/11/99

IS61SP6436

TRUTH TABLE

	Address
Operation	Used	CE	CE2	CE2	ADSP	ADSC	ADV	WRITE	OE	DQ
Deselected, Power-down	None	H	X	X	X	L	X	X	X	High-Z
Deselected, Power-down	None	L	X	L	L	X	X	X	X	High-Z
Deselected, Power-down	None	L	H	X	L	X	X	X	X	High-Z
Deselected, Power-down	None	L	X	L	H	L	X	X	X	High-Z
Deselected, Power-down	None	L	H	X	H	L	X	X	X	High-Z
Read Cycle, Begin Burst	External	L	L	H	L	X	X	X	L	Q
Read Cycle, Begin Burst	External	L	L	H	L	X	X	X	H	High-Z
Write Cycle, Begin Burst	External	L	L	H	H	L	X	L	X	D
Read Cycle, Begin Burst	External	L	L	H	H	L	X	H	L	Q
Read Cycle, Begin Burst	External	L	L	H	H	L	X	H	H	High-Z
Read Cycle, Continue Burst	Next	X	X	X	H	H	L	H	L	Q
Read Cycle, Continue Burst	Next	X	X	X	H	H	L	H	H	High-Z
Read Cycle, Continue Burst	Next	H	X	X	X	H	L	H	L	Q
Read Cycle, Continue Burst	Next	H	X	X	X	H	L	H	H	High-Z
Write Cycle, Continue Burst	Next	X	X	X	H	H	L	L	X	D
Write Cycle, Continue Burst	Next	H	X	X	X	H	L	L	X	D
Read Cycle, Suspend Burst	Current	X	X	X	H	H	H	H	L	Q
Read Cycle, Suspend Burst	Current	X	X	X	H	H	H	H	H	High-Z
Read Cycle, Suspend Burst	Current	H	X	X	X	H	H	H	L	Q
Read Cycle, Suspend Burst	Current	H	X	X	X	H	H	H	H	High-Z
Write Cycle, Suspend Burst	Current	X	X	X	H	H	H	L	X	D
Write Cycle, Suspend Burst	Current	H	X	X	X	H	H	L	X	D
Notes:

1.All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK).

2.Wait states are inserted by suspending burst.

3.X means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW4) and BWE are LOW or GW is LOW. WRITE=H means all byte write enable signals are HIGH.

4.For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH throughout the input data hold time.

5.ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock.

PARTIAL TRUTH TABLE

Function	GW	BWE	BW1	BW2	BW3	BW4
READ	H	H	X	X	X	X
READ	H	L	H	H	H	H
WRITE Byte 1	H	L	L	H	H	H
WRITE All Bytes	H	L	L	L	L	L
WRITE All Bytes	L	X	X	X	X	X
4							Integrated Silicon Solution, Inc.
							SR029-1C
						08/11/99

IS61SP6436

INTERLEAVED BURST ADDRESS TABLE (MODE = VCCQ or No Connect)

External Address	1st Burst Address	2nd Burst Address	3rd Burst Address
A1 A0	A1 A0	A1 A0	A1 A0
00	01	10	11
01	00	11	10
10	11	00	01
11	10	01	00

LINEAR BURST ADDRESS TABLE (MODE = GNDQ)

0,0

A1', A0' = 1,1

0,1

1,0

ABSOLUTE MAXIMUM RATINGS(1)

Symbol	Parameter	Value	Unit
TBIAS	Temperature Under Bias	–40 to +85	°C
TSTG	Storage Temperature	–55 to +150	°C
PD	Power Dissipation	1.8	W
IOUT	Output Current (per I/O)	100	mA
VIN, VOUT	Voltage Relative to GND for I/O Pins	–0.5 to VCCQ + 0.3	V
VIN	Voltage Relative to GND for	–0.5 to 5.5	V
	for Address and Control Inputs
VCC	Voltage on Vcc Supply Relatiive to GND	–0.5 to 4.6	V

Notes:

1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2.This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.

3.This device contains circuitry that will ensure the output devices are in High-Z at power up.

Integrated Silicon Solution, Inc.

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SR029-1C 08/11/99