ISSI IS61SP12832-5TQI, IS61SP12832-5TQ, IS61SP12832-166TQ, IS61SP12832-166B, IS61SP12832-150TQ Datasheet

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IS61SP12832

ISSI®

128K x 32 SYNCHRONOUS PIPELINED STATIC RAM

FEATURES

•Internal self-timed write cycle

•Individual Byte Write Control and Global Write

•Clock controlled, registered address, data and control

•Pentium™ or linear burst sequence control using MODE input

•Three chip enables for simple depth expansion and address pipelining

•Common data inputs and data outputs

•JEDEC 100-Pin TQFP and 119-pin PBGA package

•Single +3.3V, +10%, –5% power supply

•Power-down snooze mode

FAST ACCESS TIME

ADVANCE INFORMATION

APRIL 1999

DESCRIPTION

The ISSI IS61SP12832 is a high-speed, low-power synchronous static RAM designed to provide a burstable, highperformance, secondary cache for the Pentium™, 680X0™, and PowerPC™ microprocessors. It is organized as 131,072 words by 32 bits, fabricated with ISSI's advanced CMOS technology. The device integrates a 2-bit burst counter, highspeed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.

Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written. BW1 controls DQa, BW2 controls DQb, BW3 controls DQc, BW4 controls DQd, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written.

Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IS61SP12832 and controlled by the ADV (burst address advance) input pin.

The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating.

Symbol	Parameter	-166	-150	-133	-117	-5	Units
tKQ	Clock Access Time	3.5	3.8	4	4	5	ns

tKC	Cycle Time	6	6.7	7.5	8.5	10	ns

	Frenquency	166	150	133	117	100	MHz

This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.

Integrated Silicon Solution, Inc. — 1-800-379-4774

ADVANCE INFORMATION SR038-0D 04/16/99

IS61SP12832

ISSI®

BLOCK DIAGRAM

				MODE
CLK		CLK	Q0	A0	A0’
			Q0

		BINARY
		COUNTER			A1’
ADV	CE		Q1	A1	A1’
ADV	CE		Q1		128K x 32

ADSC
ADSC	CLR				MEMORY
ADSP	CLR
ADSP
					ARRAY
A16-A0	17		Q	15	17
A16-A0	D		Q
	ADDRESS
	REGISTER
	CE
		CLK			32	32
					32	32
GW	D	DQd	Q
BWE		DQd
BWE	BYTE WRITE
BW4	BYTE WRITE
BW4	REGISTERS
	REGISTERS
		CLK
	D	DQc	Q
		DQc
BW3	BYTE WRITE
BW3	REGISTERS
	REGISTERS
		CLK
	D	DQb	Q
		DQb
BW2	BYTE WRITE
BW2	REGISTERS
	REGISTERS
		CLK
	D	DQa	Q
		DQa
BW1	BYTE WRITE
BW1	REGISTERS
	REGISTERS
		CLK
CE					4
CE2	D		Q		INPUT	OUTPUT	32
CE2		ENABLE			REGISTERS	REGISTERS	DQ[31:0]
CE2		ENABLE					OE
	REGISTER				CLK	CLK	OE
	REGISTER				CLK	CLK
	CE
		CLK
	D		Q
		ENABLE
		DELAY
	REGISTER
		CLK
OE
2					Integrated Silicon Solution, Inc. — 1-800-379-4774
						ADVANCE INFORMATION SR038-0D
							04/16/99

IS61SP12832

ISSI®

PIN CONFIGURATION

119-pin PBGA (Top View) and 100-Pin TQFP

A7 CE CE2

BW4BW3BW2BW1CE2 VCC

GND

CLKGWBWEOE ADSCADSPADV A8

100 99 98 97

96 95 94 93

92 91 90 89 88 87 86

85 84 83 82 81

ADSP

VCCQ

A16

VCCQ

DQc1

DQb8

ADSC

CE2

DQc2

DQb7

CE2

VCCQ

VCC

A12

A15

GND

DQc3

DQb6

DQc1

GND

DQb8

DQc4

DQb5

DQc5

DQb4

DQc2

DQc3

GND

DQb6

DQb7

DQc6

DQb3

GND

VCCQ

DQc4

GND

DQb5

VCCQ

BW3

ADV

BW2

DQc7

DQb2

DQc5

DQc6

DQb4

DQb3

DQc8

DQb1

GND

DQc7

DQc8

GND

DQb2

DQb1

VCC

VCCQ

VCC

VCCQ

GND

DQd1

DQa8

DQd1

DQd2

GND

CLK

GND

DQa7

DQa8

DQd2

DQa7

BW4

BW1

VCCQ

DQd4

DQd3

DQa5

DQa6

GND

BWE

DQd3

DQa6

VCCQ

DQd5

GND

DQa4

VCCQ

DQd4

DQa5

DQd7

GND

DQa3

DQa2

DQd5

DQa4

DQd6

DQa3

GND

DQa1

GND

DQd8

VCCQ

VCC

DQd7

DQa2

MODE

VCC

A13

DQd8

DQa1

A10

A11

A14

31 32 33

34 35 36 37 38 39 40

41 42 43 44 45 46 47 48 49 50

VCCQ

MODE

A5 A4

A2 A1 A0 NC

NC GND

VCC

NC NC A10 A11

A12 A13 A14 A15

A16

PIN DESCRIPTIONS

A0, A1	Synchronous Address Inputs. These
	pins must tied to the two LSBs of the
	address bus.

A2-A16	Synchronous Address Inputs

CLK	Synchronous Clock

ADSP	Synchronous Processor Address
	Status

ADSC	Synchronous Controller Address
	Status

ADV	Synchronous Burst Address Advance

BW1-BW4	Synchronous Byte Write Enable

BWE	Synchronous Byte Write Enable

GW	Synchronous Global Write Enable

CE, CE2, CE2	Synchronous Chip Enable

OE	Output Enable

DQa-DQd	Synchronous Data Input/Output

MODE	Burst Sequence Mode Selection

VCC	+3.3V Power Supply

GND	Ground

VCCQ	Isolated Output Buffer Supply:
	+3.3V

ZZ	Snooze Enable

GNDQ	Isolated Output Buffer Ground

Integrated Silicon Solution, Inc. — 1-800-379-4774

ADVANCE INFORMATION SR038-0D 04/16/99

IS61SP12832

ISSI®

TRUTH TABLE

Address

Operation

Used

CE2

ADSP

ADSC

ADV

WRITE

Deselected, Power-down

None

High-Z

Deselected, Power-down

None

High-Z

Deselected, Power-down

None

High-Z

Deselected, Power-down

None

High-Z

Deselected, Power-down

None

High-Z

Read Cycle, Begin Burst

External

High-Z

Read Cycle, Begin Burst

External

Read

High-Z

Write Cycle, Begin Burst

External

Write

High-Z

Read Cycle, Continue Burst

Read

Read Cycle, Continue Burst

Read

High-Z

Read Cycle, Continue Burst

Read

Read Cycle, Continue Burst

Read

High-Z

Write Cycle, Continue Burst

Write

High-Z

Write Cycle, Continue Burst

Write

High-Z

Read Cycle, Suspend Burst

Current

Read

Read Cycle, Suspend Burst

Current

Read

High-Z

Read Cycle, Suspend Burst

Current

Read

Read Cycle, Suspend Burst

Current

Read

High-Z

Write Cycle, Suspend Burst

Current

Write

High-Z

Write Cycle, Suspend Burst

Current

Write

High-Z

PARTIAL TRUTH TABLE

Function	GW	BWE	BW1	BW2	BW3	BW4
Read	H	H	X	X	X	X

Read	H	L	H	H	H	H
Write Byte 1	H	L	L	H	H	H
Write All Bytes	H	L	L	L	L	L

Write All Bytes	L	X	X	X	X	X

4 Integrated Silicon Solution, Inc. — 1-800-379-4774

ADVANCE INFORMATION SR038-0D 04/16/99

IS61SP12832

ISSI®

INTERLEAVED BURST ADDRESS TABLE (MODE = VCCQ or No Connect)

External Address	1st Burst Address	2nd Burst Address	3rd Burst Address
A1 A0	A1 A0	A1 A0	A1 A0

00	01	10	11

01	00	11	10
10	11	00	01

11	10	01	00

LINEAR BURST ADDRESS TABLE (MODE = GNDQ)

0,0

A1', A0' = 1,1

0,1

1,0

ABSOLUTE MAXIMUM RATINGS(1)

Symbol	Parameter	Value	Unit
TBIAS	Temperature Under Bias	–40 to +85	°C
TSTG	Storage Temperature	–55 to +150	°C
PD	Power Dissipation	1.6	W

IOUT	Output Current (per I/O)	100	mA

VIN, VOUT	Voltage Relative to GND for I/O Pins	–0.5 to VCCQ + 0.3	V

VIN	Voltage Relative to GND for	–0.5 to VCC + 0.5	V
	for Address and Control Inputs

VCC	Voltage on Vcc Supply Relatiive to GND	–0.5 to 4.6	V

Notes:

1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2.This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.

3.This device contains circuitry that will ensure the output devices are in High-Z at power up.

Integrated Silicon Solution, Inc. — 1-800-379-4774

ADVANCE INFORMATION SR038-0D 04/16/99

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