ISSI IS61NP51218-5TQI, IS61NP51218-5TQ, IS61NLP51218-5TQI, IS61NLP51218-5TQ, IS61NLP51218-5BI Datasheet

...
0 (0)

IS61NP25632 IS61NP25636 IS61NP51218 ISSI®

IS61NLP25632 IS61NLP25636 IS61NLP51218

256K x 32, 256K x 36 and 512K x 18 PIPELINE 'NO WAIT' STATE BUS SRAM

PRELIMINARY INFORMATION

APRIL 2001

FEATURES

DESCRIPTION

100 percent bus utilization

No wait cycles between Read and Write

Internal self-timed write cycle

Individual Byte Write Control

Single R/W (Read/Write) control pin

Clock controlled, registered address, data and control

Interleaved or linear burst sequence control using MODE input

Three chip enables for simple depth expansion and address pipelining for TQFP

Power Down mode

Common data inputs and data outputs

CKE pin to enable clock and suspend operation

JEDEC 100-pin TQFP, 119 PBGA package

Single +3.3V power supply (± 5%)

NP Version: 3.3V I/O Supply Voltage

NLP Version: 2.5V I/O Supply Voltage

Industrial temperature available

FAST ACCESS TIME

The 8 Meg 'NP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for network and communications customers. They are organized as 262,144 words by 32 bits, 262,144 words by 36 bits and 524,288 words by 18 bits, fabricated with ISSI's advanced CMOS technology.

Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit.

All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values.

All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW.

Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written.

A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected.

Symbol

Parameter

-133

-100

Units

tKQ

Clock Access Time

4.2

5

ns

 

 

 

 

 

tKC

Cycle Time

7.5

10

ns

 

 

 

 

 

 

Frequency

133

100

MHz

 

 

 

 

 

This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.

Integrated Silicon Solution, Inc. — 1-800-379-4774

1

PRELIMINARY INFORMATION Rev. 00E

04/26/01

IS61NP25632

IS61NP25636

IS61NP51218

ISSI

®

IS61NLP25632

IS61NLP25636

IS61NLP51218

 

BLOCK DIAGRAM

A [0:17] or

 

ADDRESS

A2-A17 or A2-A18

 

256Kx32; 256Kx36;

 

 

 

 

A [0:18]

 

REGISTER

 

 

 

 

 

512Kx18

 

 

 

 

 

 

 

MEMORY ARRAY

 

 

 

MODE

BURST

 

 

 

 

 

 

 

A0-A1

ADDRESS

A'0-A'1

K

DATA-IN

 

 

 

COUNTER

 

 

 

 

REGISTER

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK

CONTROL

WRITE

WRITE

K

DATA-IN

CKE

LOGIC

K

ADDRESS

ADDRESS

 

REGISTER

 

 

REGISTER

REGISTER

 

 

 

 

 

 

 

 

 

CE

 

 

 

 

 

 

 

 

CE2

 

 

 

 

 

 

 

 

CE2

 

 

 

 

 

 

 

 

ADV

CONTROL

 

 

 

 

 

 

REGISTER

 

 

 

 

K

 

BWŸWEX }

 

CONTROL

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

LOGIC

 

 

 

REGISTER

(X=a,b,c,d or a,b)

 

 

 

 

 

 

BUFFER

 

 

 

 

 

 

 

 

OE

 

 

 

 

 

 

 

 

ZZ

 

 

 

 

32, 36 or 18

 

 

 

DQa0-DQd7 or DQa0-DQb8

 

 

 

 

 

 

 

 

 

 

 

DQPa-DQPd

 

 

 

 

 

 

 

2

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00E

04/26/01

IS61NP25632

IS61NP25636

IS61NP51218

ISSI

®

IS61NLP25632

IS61NLP25636

IS61NLP51218

 

PIN CONFIGURATION

119-pin PBGA (Top View) and 100-Pin TQFP

1

2

3

4

5

6

7

 

 

 

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

A6

A7 CE

CE2

BWd BWc BWb BWa

CE2 VCC

GND CLK WE CKE OE

ADV NC A17

A8

A9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCCQ

A6

A4

NC

A8

A16

VCCQ

 

 

 

 

 

 

 

 

 

 

 

B

 

 

 

 

 

 

 

100 99 98 97

96 95 94 93

92 91 90 89 88 87 86

85 84 83 82 81

 

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

80

 

NC

CE2

A3

ADV

A9

CE2

NC

NC

 

 

 

 

 

 

 

NC

C

 

 

 

 

 

 

DQc1

2

 

 

 

 

 

 

 

79

DQb8

 

 

 

 

 

 

DQc2

3

 

 

 

 

 

 

 

78

DQb7

NC

A7

A2

VCC

A12

A15

NC

 

 

 

 

 

 

 

D

 

 

 

 

 

 

VCCQ

4

 

 

 

 

 

 

 

77

VCCQ

 

 

 

 

 

 

GND

5

 

 

 

 

 

 

 

76

GND

DQc1

NC

GND

NC

GND

NC

DQb8

 

 

 

 

 

 

 

DQc3

6

 

 

 

 

 

 

 

75

DQb6

E

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQc4

7

 

 

 

 

 

 

 

74

DQb5

DQc2

DQc3

GND

CE

GND

DQb6

DQb7

 

 

 

 

 

 

 

DQc5

8

 

 

 

 

 

 

 

73

DQb4

F

 

 

 

 

 

 

 

 

 

 

 

 

 

DQc4

GND

OE

GND

DQb5

VCCQ

DQc6

9

 

 

 

 

 

 

 

72

DQb3

VCCQ

GND

10

 

 

 

 

 

 

 

71

GND

G

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCCQ

11

 

 

 

 

 

 

 

70

VCCQ

DQc5

DQc6

BWc

A17

BWb

DQb4

DQb3

DQc7

12

 

 

 

 

 

 

 

69

DQb2

H

 

 

 

 

 

 

DQc8

13

 

 

 

 

 

 

 

68

DQb1

DQc7

DQc8

GND

WE

GND

DQb2

DQb1

VCC

14

 

 

 

 

 

 

 

67

GND

J

 

 

 

 

 

 

VCC

15

 

 

 

 

 

 

 

66

VCC

VCCQ

VCC

NC

VCC

NC

VCC

VCCQ

VCC

16

 

 

 

 

 

 

 

65

VCC

K

 

 

 

 

 

 

GND

17

 

 

 

 

 

 

 

64

ZZ

DQd1

DQd2

GND

CLK

GND

DQa7

DQa8

DQd1

18

 

 

 

 

 

 

 

63

DQa8

L

 

 

 

 

 

 

DQd2

19

 

 

 

 

 

 

 

62

DQa7

 

 

 

 

 

 

VCCQ

20

 

 

 

 

 

 

 

61

VCCQ

DQd4

DQd3

BWd

NC

BWa

DQa5

DQa6

 

 

 

 

 

 

 

GND

21

 

 

 

 

 

 

 

60

GND

M

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQd3

22

 

 

 

 

 

 

 

59

DQa6

VCCQ

DQd5

GND

CKE

GND

DQa4

VCCQ

 

 

 

 

 

 

 

DQd4

23

 

 

 

 

 

 

 

58

DQa5

N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQd5

24

 

 

 

 

 

 

 

57

DQa4

DQd6

DQd7

GND

A1

GND

DQa3

DQa2

 

 

 

 

 

 

 

DQd6

25

 

 

 

 

 

 

 

56

DQa3

P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

26

 

 

 

 

 

 

 

55

GND

DQd8

NC

GND

A0

GND

NC

DQa1

VCCQ

27

 

 

 

 

 

 

 

54

VCCQ

R

 

 

 

 

 

 

DQd7

28

 

 

 

 

 

 

 

53

DQa2

NC

A5

MODE

VCC

VCC

A13

NC

DQd8

29

 

 

 

 

 

 

 

52

DQa1

T

 

 

 

 

 

 

NC

30

 

34 35 36 37 38 39 40

 

 

 

51

NC

NC

NC

A10

A11

A14

NC

ZZ

 

31 32 33

41 42 43 44 45 46 47 48 49 50

 

 

 

 

 

 

 

 

 

 

 

 

U

 

 

 

 

 

 

 

MODE

A5 A4

A3

A2 A1 A0 NC

NC GND

VCC NC NC A10 A11

A12 A13 A14

A15

A16

 

VCCQ

NC

NC

NC

NC

NC

VCCQ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

256K x 32

 

 

 

 

 

 

 

 

 

 

PIN DESCRIPTIONS

A0, A1

Synchronous Address Inputs. These

 

pins must tied to the two LSBs of the

 

address bus.

 

 

A2-A17

Synchronous Address Inputs

 

 

CLK

Synchronous Clock

 

 

ADV

Synchronous Burst Address Advance

 

 

BWa-BWd

Synchronous Byte Write Enable

 

 

WE

Write Enable

 

 

CKE

Clock Enable

 

 

CE, CE2, CE2 Synchronous Chip Enable

OE

Output Enable

 

 

DQa-DQd

Synchronous Data Input/Output

 

 

MODE

Burst Sequence Mode Selection

 

 

VCC

+3.3V Power Supply

 

 

GND

Ground

 

 

VCCQ

Isolated Output Buffer Supply: +3.3V/2.5V

 

 

ZZ

Snooze Enable

 

 

Integrated Silicon Solution, Inc. — 1-800-379-4774

3

PRELIMINARY INFORMATION Rev. 00E

04/26/01

IS61NP25632

IS61NP25636

IS61NP51218

ISSI

®

IS61NLP25632

IS61NLP25636

IS61NLP51218

 

PIN CONFIGURATION

119-pin PBGA (Top View) and 100-Pin TQFP

1

2

3

4

5

6

7

 

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

A6

A7 CE CE2

BWd BWc BWb BWa

CE2 VCC GND CLK WE CKE OE

ADV NC A17

A8

A9

 

VCCQ

A6

A4

NC

A8

A16

VCCQ

 

 

 

 

 

 

 

 

 

B

CE2

A3

ADV

A9

CE2

NC

 

100 99 98 97

96 95 94 93

92 91 90 89 88 87 86

85 84 83 82 81

 

NC

DQPc

1

 

 

 

 

 

80

DQPb

 

 

 

 

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

DQc1

2

 

 

 

 

 

79

DQb8

NC

A7

A2

VCC

A12

A15

NC

DQc2

3

 

 

 

 

 

78

DQb7

D

 

 

 

 

 

 

VCCQ

4

 

 

 

 

 

77

VCCQ

DQc1

DQPc

GND

NC

GND

DQPb

DQb8

GND

5

 

 

 

 

 

76

GND

E

 

 

 

 

 

 

DQc3

6

 

 

 

 

 

75

DQb6

DQc2

DQc3

GND

CE

GND

DQb6

DQb7

DQc4

7

 

 

 

 

 

74

DQb5

F

 

 

 

 

 

 

DQc5

8

 

 

 

 

 

73

DQb4

 

 

 

 

 

 

DQc6

9

 

 

 

 

 

72

DQb3

VCCQ

DQc4

GND

OE

GND

DQb5

VCCQ

 

 

 

 

 

G

 

 

 

 

 

 

GND

10

 

 

 

 

 

71

GND

 

 

 

 

 

 

VCCQ

11

 

 

 

 

 

70

VCCQ

DQc5

DQc6

BWc

A17

BWb

DQb4

DQb3

 

 

 

 

 

DQc7

12

 

 

 

 

 

69

DQb2

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQc8

13

 

 

 

 

 

68

DQb1

DQc7

DQc8

GND

WE

GND

DQb2

DQb1

 

 

 

 

 

VCC

14

 

 

 

 

 

67

GND

J

 

 

 

 

 

 

 

 

 

 

 

VCC

NC

VCC

NC

VCC

VCCQ

VCC

15

 

 

 

 

 

66

VCC

VCCQ

VCC

16

 

 

 

 

 

65

VCC

K

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

17

 

 

 

 

 

64

ZZ

DQd1

DQd2

GND

CLK

GND

DQa7

DQa8

DQd1

18

 

 

 

 

 

63

DQa8

L

 

 

 

 

 

 

DQd2

19

 

 

 

 

 

62

DQa7

DQd4

DQd3

BWd

NC

BWa

DQa5

DQa6

VCCQ

20

 

 

 

 

 

61

VCCQ

M

 

 

 

 

 

 

GND

21

 

 

 

 

 

60

GND

VCCQ

DQd5

GND

CKE

GND

DQa4

VCCQ

DQd3

22

 

 

 

 

 

59

DQa6

N

 

 

 

 

 

 

DQd4

23

 

 

 

 

 

58

DQa5

DQd6

DQd7

GND

A1

GND

DQa3

DQa2

DQd5

24

 

 

 

 

 

57

DQa4

P

 

 

 

 

 

 

DQd6

25

 

 

 

 

 

56

DQa3

 

 

 

 

 

 

GND

26

 

 

 

 

 

55

GND

DQd8

DQPd

GND

A0

GND

DQPa

DQa1

 

 

 

 

 

VCCQ

27

 

 

 

 

 

54

VCCQ

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQd7

28

 

 

 

 

 

53

DQa2

NC

A5

MODE

VCC

VCC

A13

NC

 

 

 

 

 

DQd8

29

 

 

 

 

 

52

DQa1

T

 

 

 

 

 

 

 

 

 

 

 

NC

A10

A11

A14

NC

ZZ

DQPd

30

 

 

 

 

 

51

DQPa

NC

 

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

 

U

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCCQ

NC

NC

NC

NC

NC

VCCQ

 

MODE

A5 A4 A3

A2 A1 A0 NC

NC GND VCC NC NC A10 A11

A12 A13 A14

A15

A16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

256K x 36

 

 

 

 

 

 

 

 

PIN DESCRIPTIONS

A0, A1

Synchronous Address Inputs. These

 

pins must tied to the two LSBs of the

 

address bus.

 

 

A2-A17

Synchronous Address Inputs

 

 

CLK

Synchronous Clock

 

 

ADV

Synchronous Burst Address Advance

 

 

BWa-BWd

Synchronous Byte Write Enable

 

 

WE

Write Enable

 

 

CKE

Clock Enable

 

 

CE, CE2, CE2

Synchronous Chip Enable

 

 

OE

Output Enable

 

 

DQa-DQd

Synchronous Data Input/Output

 

 

MODE

Burst Sequence Mode Selection

 

 

VCC

+3.3V Power Supply

 

 

GND

Ground

 

 

VCCQ

Isolated Output Buffer Supply: +3.3V/2.5V

 

 

ZZ

Snooze Enable

 

 

DQPa-DQPd

Parity Data I/O

 

 

4 Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00E

04/26/01

ISSI IS61NP51218-5TQI, IS61NP51218-5TQ, IS61NLP51218-5TQI, IS61NLP51218-5TQ, IS61NLP51218-5BI Datasheet

IS61NP25632

IS61NP25636

IS61NP51218

ISSI

®

IS61NLP25632

IS61NLP25636

IS61NLP51218

 

PIN CONFIGURATION

119-pin PBGA (Top View) and 100-Pin TQFP

1

2

3

4

5

6

7

 

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

A6

A7 CE CE2

NC NC BWb BWa

CE2 VCC GND CLK WE CKE OE

ADV NC A18

A8

A9

 

VCCQ

A6

A4

NC

A8

A16

VCCQ

 

 

 

 

 

 

 

 

 

B

CE2

A3

ADV

A9

CE2

NC

 

100 99 98 97

96 95 94 93

92 91 90 89 88 87 86

85 84 83 82 81

 

NC

NC

1

 

 

 

 

 

80

A10

 

 

 

 

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

NC

2

 

 

 

 

 

79

NC

NC

A7

A2

VCC

A12

A15

NC

NC

3

 

 

 

 

 

78

NC

D

 

 

 

 

 

 

VCCQ

4

 

 

 

 

 

77

VCCQ

DQ9

NC

GND

NC

GND

DQP1

NC

GND

5

 

 

 

 

 

76

GND

E

 

 

 

 

 

 

NC

6

 

 

 

 

 

75

NC

NC

DQ10

GND

CE

GND

NC

DQ8

NC

7

 

 

 

 

 

74

DQP1

F

 

 

 

 

 

 

DQ9

8

 

 

 

 

 

73

DQ8

 

 

 

 

 

 

DQ10

9

 

 

 

 

 

72

DQ7

VCCQ

NC

GND

OE

GND

DQ7

VCCQ

 

 

 

 

 

G

 

 

 

 

 

 

GND

10

 

 

 

 

 

71

GND

 

 

 

 

 

 

VCCQ

11

 

 

 

 

 

70

VCCQ

NC

DQ11

BWb

A17

NC

NC

DQ6

 

 

 

 

 

DQ11

12

 

 

 

 

 

69

DQ6

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ12

13

 

 

 

 

 

68

DQ5

DQ12

NC

GND

WE

GND

DQ5

NC

 

 

 

 

 

VCC

14

 

 

 

 

 

67

GND

J

 

 

 

 

 

 

 

 

 

 

 

VCC

NC

VCC

NC

VCC

VCCQ

VCC

15

 

 

 

 

 

66

VCC

VCCQ

VCC

16

 

 

 

 

 

65

VCC

K

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

17

 

 

 

 

 

64

ZZ

NC

DQ13

GND

CLK

GND

NC

DQ4

DQ13

18

 

 

 

 

 

63

DQ4

L

 

 

 

 

 

 

DQ14

19

 

 

 

 

 

62

DQ3

DQ14

NC

NC

NC

BWa

DQ3

NC

VCCQ

20

 

 

 

 

 

61

VCCQ

M

 

 

 

 

 

 

GND

21

 

 

 

 

 

60

GND

VCCQ

DQ15

GND

CKE

GND

NC

VCCQ

DQ15

22

 

 

 

 

 

59

DQ2

N

 

 

 

 

 

 

DQ16

23

 

 

 

 

 

58

DQ1

DQ16

NC

GND

A1

GND

DQ2

NC

DQP2

24

 

 

 

 

 

57

NC

P

 

 

 

 

 

 

NC

25

 

 

 

 

 

56

NC

 

 

 

 

 

 

GND

26

 

 

 

 

 

55

GND

NC

DQP2

GND

A0

GND

NC

DQ1

 

 

 

 

 

VCCQ

27

 

 

 

 

 

54

VCCQ

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

28

 

 

 

 

 

53

NC

NC

A5

MODE

VCC

VCC

A13

NC

 

 

 

 

 

NC

29

 

 

 

 

 

52

NC

T

 

 

 

 

 

 

 

 

 

 

 

A10

A11

NC

A14

A18

ZZ

NC

30

 

 

 

 

 

51

NC

NC

 

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

 

U

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCCQ

NC

NC

NC

NC

NC

VCCQ

 

MODE

A5 A4 A3

A2 A1 A0 NC

NC GND VCC NC NC A11 A12

A13 A14 A15

A16

A17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

512K x 18

 

 

 

 

 

 

 

 

PIN DESCRIPTIONS

A0, A1

Synchronous Address Inputs. These

 

pins must tied to the two LSBs of the

 

address bus.

 

 

A2-A18

Synchronous Address Inputs

 

 

CLK

Synchronous Clock

 

 

ADV

Synchronous Burst Address Advance

 

 

BWa-BWb

Synchronous Byte Write Enable

 

 

WE

Write Enable

 

 

CKE

Clock Enable

 

 

CE, CE2, CE2 Synchronous Chip Enable

OE

Output Enable

 

 

DQ1-DQ16

Synchronous Data Input/Output

 

 

MODE

Burst Sequence Mode Selection

 

 

VCC

+3.3V Power Supply

 

 

GND

Ground

 

 

VCCQ

Isolated Output Buffer Supply: +3.3V/2.5V

 

 

ZZ

Snooze Enable

 

 

DQP1-DQP2

Parity Data I/O DQP1 is parity for

 

DQ1-8; DQP2 is parity for DQ9-16

 

 

Integrated Silicon Solution, Inc. — 1-800-379-4774

5

PRELIMINARY INFORMATION Rev. 00E

04/26/01

IS61NP25632

IS61NP25636

IS61NP51218

 

 

 

 

ISSI

®

IS61NLP25632

IS61NLP25636

IS61NLP51218

 

 

 

 

 

STATE DIAGRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BEGIN

 

WRITE

 

 

 

 

 

 

 

 

 

READ

 

 

 

BEGIN

 

 

 

 

 

 

 

 

 

 

 

 

 

READ

DS

DS

WRITE

WRITE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ

WRITE

 

 

 

 

 

READ BURST

 

DESELECT

BURST WRITE

 

 

 

DS

 

BURST

 

DS

 

DS

BURST

WRITE

 

BURST

BURST

 

 

BURST

READ

 

 

WRITE

 

 

 

READ

SYNCHRONOUS TRUTH TABLE(1)

 

Address

 

 

 

 

 

 

 

 

 

Operation

Used

CS1

CS2

CS2

ADV

WE

BWx

OE

CKE

CLK

 

 

 

 

 

 

 

 

 

 

 

Not Selected Continue

N/A

X

X

X

H

X

X

X

L

Begin Burst Read

External Address

L

H

L

L

H

X

L

L

Continue Burst Read

Next Address

X

X

X

H

X

X

L

L

NOP/Dummy Read

External Address

L

H

L

L

H

X

H

L

Dummy Read

Next Address

X

X

X

H

X

X

H

L

Begin Burst Write

External Address

L

H

L

L

L

L

X

L

Continue Burst Write

Next Address

X

X

X

H

X

L

X

L

 

 

 

 

 

 

 

 

 

 

 

NOP/Write Abort

N/A

L

H

L

L

L

H

X

L

Write Abort

Next Address

X

X

X

H

X

H

X

L

 

 

 

 

 

 

 

 

 

 

 

Ignore Clock

Current Address

X

X

X

X

X

X

X

H

Notes:

1."X" means don't care.

2.The rising edge of clock is symbolized by ↑

3.A continue deselect cycle can only be entered if a deselect cycle is executed first.

4.WE = L means Write operation in Write Truth Table. WE = H means Read operation in Write Truth Table.

5.Operation finally depends on status of asynchronous pins (ZZ and OE).

6 Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00E

04/26/01

Loading...
+ 14 hidden pages