IS61NP25632 IS61NP25636 IS61NP51218 ISSI®
IS61NLP25632 IS61NLP25636 IS61NLP51218
256K x 32, 256K x 36 and 512K x 18 PIPELINE 'NO WAIT' STATE BUS SRAM
PRELIMINARY INFORMATION
APRIL 2001
FEATURES |
DESCRIPTION |
•100 percent bus utilization
•No wait cycles between Read and Write
•Internal self-timed write cycle
•Individual Byte Write Control
•Single R/W (Read/Write) control pin
•Clock controlled, registered address, data and control
•Interleaved or linear burst sequence control using MODE input
•Three chip enables for simple depth expansion and address pipelining for TQFP
•Power Down mode
•Common data inputs and data outputs
•CKE pin to enable clock and suspend operation
•JEDEC 100-pin TQFP, 119 PBGA package
•Single +3.3V power supply (± 5%)
•NP Version: 3.3V I/O Supply Voltage
•NLP Version: 2.5V I/O Supply Voltage
•Industrial temperature available
FAST ACCESS TIME
The 8 Meg 'NP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for network and communications customers. They are organized as 262,144 words by 32 bits, 262,144 words by 36 bits and 524,288 words by 18 bits, fabricated with ISSI's advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit.
All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW.
Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected.
Symbol |
Parameter |
-133 |
-100 |
Units |
tKQ |
Clock Access Time |
4.2 |
5 |
ns |
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tKC |
Cycle Time |
7.5 |
10 |
ns |
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Frequency |
133 |
100 |
MHz |
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This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
1 |
PRELIMINARY INFORMATION Rev. 00E
04/26/01
IS61NP25632 |
IS61NP25636 |
IS61NP51218 |
ISSI |
® |
IS61NLP25632 |
IS61NLP25636 |
IS61NLP51218 |
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BLOCK DIAGRAM
A [0:17] or |
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ADDRESS |
A2-A17 or A2-A18 |
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256Kx32; 256Kx36; |
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A [0:18] |
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REGISTER |
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512Kx18 |
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MEMORY ARRAY |
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MODE |
BURST |
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A0-A1 |
ADDRESS |
A'0-A'1 |
K |
DATA-IN |
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COUNTER |
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REGISTER |
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CLK |
CONTROL |
WRITE |
WRITE |
K |
DATA-IN |
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CKE |
LOGIC |
K |
ADDRESS |
ADDRESS |
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REGISTER |
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REGISTER |
REGISTER |
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CE |
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CE2 |
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CE2 |
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ADV |
CONTROL |
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REGISTER |
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K |
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BWŸWEX } |
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CONTROL |
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OUTPUT |
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LOGIC |
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REGISTER |
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(X=a,b,c,d or a,b) |
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BUFFER |
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OE |
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ZZ |
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32, 36 or 18 |
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DQa0-DQd7 or DQa0-DQb8 |
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DQPa-DQPd |
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2 |
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
PRELIMINARY INFORMATION Rev. 00E
04/26/01
IS61NP25632 |
IS61NP25636 |
IS61NP51218 |
ISSI |
® |
IS61NLP25632 |
IS61NLP25636 |
IS61NLP51218 |
|
PIN CONFIGURATION
119-pin PBGA (Top View) and 100-Pin TQFP
1 |
2 |
3 |
4 |
5 |
6 |
7 |
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A |
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A6 |
A7 CE |
CE2 |
BWd BWc BWb BWa |
CE2 VCC |
GND CLK WE CKE OE |
ADV NC A17 |
A8 |
A9 |
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VCCQ |
A6 |
A4 |
NC |
A8 |
A16 |
VCCQ |
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B |
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100 99 98 97 |
96 95 94 93 |
92 91 90 89 88 87 86 |
85 84 83 82 81 |
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1 |
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80 |
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NC |
CE2 |
A3 |
ADV |
A9 |
CE2 |
NC |
NC |
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NC |
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C |
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DQc1 |
2 |
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79 |
DQb8 |
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DQc2 |
3 |
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78 |
DQb7 |
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NC |
A7 |
A2 |
VCC |
A12 |
A15 |
NC |
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D |
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VCCQ |
4 |
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77 |
VCCQ |
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GND |
5 |
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76 |
GND |
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DQc1 |
NC |
GND |
NC |
GND |
NC |
DQb8 |
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DQc3 |
6 |
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75 |
DQb6 |
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E |
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DQc4 |
7 |
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74 |
DQb5 |
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DQc2 |
DQc3 |
GND |
CE |
GND |
DQb6 |
DQb7 |
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DQc5 |
8 |
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73 |
DQb4 |
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F |
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DQc4 |
GND |
OE |
GND |
DQb5 |
VCCQ |
DQc6 |
9 |
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72 |
DQb3 |
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VCCQ |
GND |
10 |
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71 |
GND |
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G |
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VCCQ |
11 |
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70 |
VCCQ |
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DQc5 |
DQc6 |
BWc |
A17 |
BWb |
DQb4 |
DQb3 |
DQc7 |
12 |
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69 |
DQb2 |
H |
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DQc8 |
13 |
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68 |
DQb1 |
DQc7 |
DQc8 |
GND |
WE |
GND |
DQb2 |
DQb1 |
VCC |
14 |
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67 |
GND |
J |
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VCC |
15 |
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66 |
VCC |
VCCQ |
VCC |
NC |
VCC |
NC |
VCC |
VCCQ |
VCC |
16 |
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65 |
VCC |
K |
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GND |
17 |
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64 |
ZZ |
DQd1 |
DQd2 |
GND |
CLK |
GND |
DQa7 |
DQa8 |
DQd1 |
18 |
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63 |
DQa8 |
L |
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DQd2 |
19 |
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62 |
DQa7 |
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VCCQ |
20 |
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61 |
VCCQ |
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DQd4 |
DQd3 |
BWd |
NC |
BWa |
DQa5 |
DQa6 |
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GND |
21 |
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60 |
GND |
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M |
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DQd3 |
22 |
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59 |
DQa6 |
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VCCQ |
DQd5 |
GND |
CKE |
GND |
DQa4 |
VCCQ |
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DQd4 |
23 |
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58 |
DQa5 |
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N |
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DQd5 |
24 |
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57 |
DQa4 |
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DQd6 |
DQd7 |
GND |
A1 |
GND |
DQa3 |
DQa2 |
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DQd6 |
25 |
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56 |
DQa3 |
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P |
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GND |
26 |
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55 |
GND |
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DQd8 |
NC |
GND |
A0 |
GND |
NC |
DQa1 |
VCCQ |
27 |
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54 |
VCCQ |
R |
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DQd7 |
28 |
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53 |
DQa2 |
NC |
A5 |
MODE |
VCC |
VCC |
A13 |
NC |
DQd8 |
29 |
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52 |
DQa1 |
T |
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NC |
30 |
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34 35 36 37 38 39 40 |
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51 |
NC |
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NC |
NC |
A10 |
A11 |
A14 |
NC |
ZZ |
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31 32 33 |
41 42 43 44 45 46 47 48 49 50 |
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U |
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MODE |
A5 A4 |
A3 |
A2 A1 A0 NC |
NC GND |
VCC NC NC A10 A11 |
A12 A13 A14 |
A15 |
A16 |
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VCCQ |
NC |
NC |
NC |
NC |
NC |
VCCQ |
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256K x 32 |
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PIN DESCRIPTIONS
A0, A1 |
Synchronous Address Inputs. These |
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pins must tied to the two LSBs of the |
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address bus. |
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A2-A17 |
Synchronous Address Inputs |
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CLK |
Synchronous Clock |
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ADV |
Synchronous Burst Address Advance |
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BWa-BWd |
Synchronous Byte Write Enable |
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WE |
Write Enable |
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CKE |
Clock Enable |
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CE, CE2, CE2 Synchronous Chip Enable
OE |
Output Enable |
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DQa-DQd |
Synchronous Data Input/Output |
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MODE |
Burst Sequence Mode Selection |
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VCC |
+3.3V Power Supply |
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GND |
Ground |
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VCCQ |
Isolated Output Buffer Supply: +3.3V/2.5V |
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ZZ |
Snooze Enable |
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Integrated Silicon Solution, Inc. — 1-800-379-4774 |
3 |
PRELIMINARY INFORMATION Rev. 00E
04/26/01
IS61NP25632 |
IS61NP25636 |
IS61NP51218 |
ISSI |
® |
IS61NLP25632 |
IS61NLP25636 |
IS61NLP51218 |
|
PIN CONFIGURATION
119-pin PBGA (Top View) and 100-Pin TQFP
1 |
2 |
3 |
4 |
5 |
6 |
7 |
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A |
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A6 |
A7 CE CE2 |
BWd BWc BWb BWa |
CE2 VCC GND CLK WE CKE OE |
ADV NC A17 |
A8 |
A9 |
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VCCQ |
A6 |
A4 |
NC |
A8 |
A16 |
VCCQ |
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B |
CE2 |
A3 |
ADV |
A9 |
CE2 |
NC |
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100 99 98 97 |
96 95 94 93 |
92 91 90 89 88 87 86 |
85 84 83 82 81 |
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NC |
DQPc |
1 |
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80 |
DQPb |
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C |
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DQc1 |
2 |
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79 |
DQb8 |
NC |
A7 |
A2 |
VCC |
A12 |
A15 |
NC |
DQc2 |
3 |
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78 |
DQb7 |
D |
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VCCQ |
4 |
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77 |
VCCQ |
DQc1 |
DQPc |
GND |
NC |
GND |
DQPb |
DQb8 |
GND |
5 |
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76 |
GND |
E |
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DQc3 |
6 |
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75 |
DQb6 |
DQc2 |
DQc3 |
GND |
CE |
GND |
DQb6 |
DQb7 |
DQc4 |
7 |
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74 |
DQb5 |
F |
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DQc5 |
8 |
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73 |
DQb4 |
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DQc6 |
9 |
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72 |
DQb3 |
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VCCQ |
DQc4 |
GND |
OE |
GND |
DQb5 |
VCCQ |
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G |
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GND |
10 |
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71 |
GND |
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VCCQ |
11 |
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70 |
VCCQ |
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DQc5 |
DQc6 |
BWc |
A17 |
BWb |
DQb4 |
DQb3 |
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DQc7 |
12 |
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69 |
DQb2 |
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H |
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DQc8 |
13 |
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68 |
DQb1 |
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DQc7 |
DQc8 |
GND |
WE |
GND |
DQb2 |
DQb1 |
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VCC |
14 |
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67 |
GND |
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J |
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VCC |
NC |
VCC |
NC |
VCC |
VCCQ |
VCC |
15 |
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66 |
VCC |
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VCCQ |
VCC |
16 |
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65 |
VCC |
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K |
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GND |
17 |
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64 |
ZZ |
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DQd1 |
DQd2 |
GND |
CLK |
GND |
DQa7 |
DQa8 |
DQd1 |
18 |
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63 |
DQa8 |
L |
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DQd2 |
19 |
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62 |
DQa7 |
DQd4 |
DQd3 |
BWd |
NC |
BWa |
DQa5 |
DQa6 |
VCCQ |
20 |
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61 |
VCCQ |
M |
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GND |
21 |
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60 |
GND |
VCCQ |
DQd5 |
GND |
CKE |
GND |
DQa4 |
VCCQ |
DQd3 |
22 |
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59 |
DQa6 |
N |
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DQd4 |
23 |
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58 |
DQa5 |
DQd6 |
DQd7 |
GND |
A1 |
GND |
DQa3 |
DQa2 |
DQd5 |
24 |
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57 |
DQa4 |
P |
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DQd6 |
25 |
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56 |
DQa3 |
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GND |
26 |
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55 |
GND |
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DQd8 |
DQPd |
GND |
A0 |
GND |
DQPa |
DQa1 |
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VCCQ |
27 |
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54 |
VCCQ |
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R |
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DQd7 |
28 |
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53 |
DQa2 |
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NC |
A5 |
MODE |
VCC |
VCC |
A13 |
NC |
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DQd8 |
29 |
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52 |
DQa1 |
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T |
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NC |
A10 |
A11 |
A14 |
NC |
ZZ |
DQPd |
30 |
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51 |
DQPa |
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NC |
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31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 |
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U |
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VCCQ |
NC |
NC |
NC |
NC |
NC |
VCCQ |
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MODE |
A5 A4 A3 |
A2 A1 A0 NC |
NC GND VCC NC NC A10 A11 |
A12 A13 A14 |
A15 |
A16 |
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256K x 36 |
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PIN DESCRIPTIONS
A0, A1 |
Synchronous Address Inputs. These |
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pins must tied to the two LSBs of the |
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address bus. |
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A2-A17 |
Synchronous Address Inputs |
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CLK |
Synchronous Clock |
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ADV |
Synchronous Burst Address Advance |
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BWa-BWd |
Synchronous Byte Write Enable |
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WE |
Write Enable |
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CKE |
Clock Enable |
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CE, CE2, CE2 |
Synchronous Chip Enable |
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OE |
Output Enable |
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DQa-DQd |
Synchronous Data Input/Output |
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MODE |
Burst Sequence Mode Selection |
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VCC |
+3.3V Power Supply |
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GND |
Ground |
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VCCQ |
Isolated Output Buffer Supply: +3.3V/2.5V |
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ZZ |
Snooze Enable |
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DQPa-DQPd |
Parity Data I/O |
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4 Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00E
04/26/01
IS61NP25632 |
IS61NP25636 |
IS61NP51218 |
ISSI |
® |
IS61NLP25632 |
IS61NLP25636 |
IS61NLP51218 |
|
PIN CONFIGURATION
119-pin PBGA (Top View) and 100-Pin TQFP
1 |
2 |
3 |
4 |
5 |
6 |
7 |
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A |
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A6 |
A7 CE CE2 |
NC NC BWb BWa |
CE2 VCC GND CLK WE CKE OE |
ADV NC A18 |
A8 |
A9 |
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VCCQ |
A6 |
A4 |
NC |
A8 |
A16 |
VCCQ |
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B |
CE2 |
A3 |
ADV |
A9 |
CE2 |
NC |
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100 99 98 97 |
96 95 94 93 |
92 91 90 89 88 87 86 |
85 84 83 82 81 |
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NC |
NC |
1 |
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80 |
A10 |
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C |
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NC |
2 |
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79 |
NC |
NC |
A7 |
A2 |
VCC |
A12 |
A15 |
NC |
NC |
3 |
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78 |
NC |
D |
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VCCQ |
4 |
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77 |
VCCQ |
DQ9 |
NC |
GND |
NC |
GND |
DQP1 |
NC |
GND |
5 |
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76 |
GND |
E |
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NC |
6 |
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75 |
NC |
NC |
DQ10 |
GND |
CE |
GND |
NC |
DQ8 |
NC |
7 |
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74 |
DQP1 |
F |
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DQ9 |
8 |
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73 |
DQ8 |
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DQ10 |
9 |
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72 |
DQ7 |
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VCCQ |
NC |
GND |
OE |
GND |
DQ7 |
VCCQ |
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G |
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GND |
10 |
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71 |
GND |
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VCCQ |
11 |
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70 |
VCCQ |
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NC |
DQ11 |
BWb |
A17 |
NC |
NC |
DQ6 |
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DQ11 |
12 |
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69 |
DQ6 |
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H |
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DQ12 |
13 |
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68 |
DQ5 |
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DQ12 |
NC |
GND |
WE |
GND |
DQ5 |
NC |
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VCC |
14 |
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67 |
GND |
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J |
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VCC |
NC |
VCC |
NC |
VCC |
VCCQ |
VCC |
15 |
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66 |
VCC |
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VCCQ |
VCC |
16 |
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65 |
VCC |
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K |
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GND |
17 |
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64 |
ZZ |
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NC |
DQ13 |
GND |
CLK |
GND |
NC |
DQ4 |
DQ13 |
18 |
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63 |
DQ4 |
L |
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DQ14 |
19 |
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62 |
DQ3 |
DQ14 |
NC |
NC |
NC |
BWa |
DQ3 |
NC |
VCCQ |
20 |
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61 |
VCCQ |
M |
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GND |
21 |
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60 |
GND |
VCCQ |
DQ15 |
GND |
CKE |
GND |
NC |
VCCQ |
DQ15 |
22 |
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59 |
DQ2 |
N |
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DQ16 |
23 |
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58 |
DQ1 |
DQ16 |
NC |
GND |
A1 |
GND |
DQ2 |
NC |
DQP2 |
24 |
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57 |
NC |
P |
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NC |
25 |
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56 |
NC |
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GND |
26 |
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55 |
GND |
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NC |
DQP2 |
GND |
A0 |
GND |
NC |
DQ1 |
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VCCQ |
27 |
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54 |
VCCQ |
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R |
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NC |
28 |
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53 |
NC |
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NC |
A5 |
MODE |
VCC |
VCC |
A13 |
NC |
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NC |
29 |
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52 |
NC |
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T |
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A10 |
A11 |
NC |
A14 |
A18 |
ZZ |
NC |
30 |
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51 |
NC |
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NC |
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31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 |
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U |
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VCCQ |
NC |
NC |
NC |
NC |
NC |
VCCQ |
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MODE |
A5 A4 A3 |
A2 A1 A0 NC |
NC GND VCC NC NC A11 A12 |
A13 A14 A15 |
A16 |
A17 |
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512K x 18 |
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PIN DESCRIPTIONS
A0, A1 |
Synchronous Address Inputs. These |
|
pins must tied to the two LSBs of the |
|
address bus. |
|
|
A2-A18 |
Synchronous Address Inputs |
|
|
CLK |
Synchronous Clock |
|
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ADV |
Synchronous Burst Address Advance |
|
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BWa-BWb |
Synchronous Byte Write Enable |
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WE |
Write Enable |
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CKE |
Clock Enable |
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CE, CE2, CE2 Synchronous Chip Enable
OE |
Output Enable |
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DQ1-DQ16 |
Synchronous Data Input/Output |
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MODE |
Burst Sequence Mode Selection |
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VCC |
+3.3V Power Supply |
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GND |
Ground |
|
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VCCQ |
Isolated Output Buffer Supply: +3.3V/2.5V |
|
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ZZ |
Snooze Enable |
|
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DQP1-DQP2 |
Parity Data I/O DQP1 is parity for |
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DQ1-8; DQP2 is parity for DQ9-16 |
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Integrated Silicon Solution, Inc. — 1-800-379-4774 |
5 |
PRELIMINARY INFORMATION Rev. 00E
04/26/01
IS61NP25632 |
IS61NP25636 |
IS61NP51218 |
|
|
|
|
ISSI |
® |
||||||||||||
IS61NLP25632 |
IS61NLP25636 |
IS61NLP51218 |
|
|
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STATE DIAGRAM |
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READ |
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BEGIN |
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WRITE |
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READ |
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BEGIN |
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READ |
DS |
DS |
WRITE |
WRITE |
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READ |
WRITE |
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READ BURST |
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DESELECT |
BURST WRITE |
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DS |
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BURST |
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DS |
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DS |
BURST |
WRITE |
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BURST |
BURST |
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BURST |
READ |
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WRITE |
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READ |
SYNCHRONOUS TRUTH TABLE(1)
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Address |
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Operation |
Used |
CS1 |
CS2 |
CS2 |
ADV |
WE |
BWx |
OE |
CKE |
CLK |
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Not Selected Continue |
N/A |
X |
X |
X |
H |
X |
X |
X |
L |
↑ |
Begin Burst Read |
External Address |
L |
H |
L |
L |
H |
X |
L |
L |
↑ |
Continue Burst Read |
Next Address |
X |
X |
X |
H |
X |
X |
L |
L |
↑ |
NOP/Dummy Read |
External Address |
L |
H |
L |
L |
H |
X |
H |
L |
↑ |
Dummy Read |
Next Address |
X |
X |
X |
H |
X |
X |
H |
L |
↑ |
Begin Burst Write |
External Address |
L |
H |
L |
L |
L |
L |
X |
L |
↑ |
Continue Burst Write |
Next Address |
X |
X |
X |
H |
X |
L |
X |
L |
↑ |
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NOP/Write Abort |
N/A |
L |
H |
L |
L |
L |
H |
X |
L |
↑ |
Write Abort |
Next Address |
X |
X |
X |
H |
X |
H |
X |
L |
↑ |
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Ignore Clock |
Current Address |
X |
X |
X |
X |
X |
X |
X |
H |
↑ |
Notes:
1."X" means don't care.
2.The rising edge of clock is symbolized by ↑
3.A continue deselect cycle can only be entered if a deselect cycle is executed first.
4.WE = L means Write operation in Write Truth Table. WE = H means Read operation in Write Truth Table.
5.Operation finally depends on status of asynchronous pins (ZZ and OE).
6 Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00E
04/26/01