IS61LV256 |
ISSI® |
32K x 8 LOW VOLTAGE CMOS STATIC RAM
FEATURES
•High-speed access times:
--8, 10, 12, 15, 20 ns
•Automatic power-down when chip is deselected
•CMOS low power operation
--345 mW (max.) operating
--7 mW (max.) CMOS standby
•TTL compatible interface levels
•Single 3.3V power supply
•Fully static operation: no clock or refresh required
•Three-state outputs
OCTOBER 1999
DESCRIPTION
The ISSI IS61LV256 is a very high-speed, low power, 32,768-word by 8-bit static RAM. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 8 ns maximum.
When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation is reduced to 50 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active LOW Chip Enable (CE). The active LOW Write Enable (WE) controls both writing and reading of the memory.
The IS61LV256 is available in the JEDEC standard 28-pin, 300-mil SOJ and the 450-mil TSOP (Type I) package.
FUNCTIONAL BLOCK DIAGRAM
A0-A14 |
DECODER |
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256 X 1024 |
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MEMORY ARRAY |
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VCC
GND
I/O
I/O0-I/O7 DATA COLUMN I/O
CIRCUIT
CE
CONTROL
OE CIRCUIT
WE
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
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Rev. I
11/09/99
IS61LV256 |
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ISSI® |
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PIN CONFIGURATION |
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PIN CONFIGURATION |
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28-Pin SOJ |
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28-Pin TSOP (Type I) |
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A14 |
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1 |
28 |
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VCC |
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22 |
21 |
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A10 |
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OE |
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A12 |
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2 |
27 |
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WE |
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A11 |
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23 |
20 |
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26 |
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A13 |
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CE |
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A7 |
3 |
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19 |
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I/O7 |
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25 |
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A8 |
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A9 |
24 |
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A6 |
4 |
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18 |
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I/O6 |
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A5 |
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24 |
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A9 |
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A8 |
25 |
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5 |
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17 |
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I/O5 |
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A13 |
26 |
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A4 |
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23 |
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A11 |
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27 |
16 |
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I/O4 |
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6 |
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WE |
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A3 |
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22 |
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VCC |
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28 |
15 |
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I/O3 |
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7 |
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OE |
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21 |
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A10 |
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A14 |
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1 |
14 |
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GND |
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A2 |
8 |
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A12 |
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2 |
13 |
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I/O2 |
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A1 |
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20 |
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CE |
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A7 |
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3 |
12 |
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I/O1 |
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19 |
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I/O7 |
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A0 |
10 |
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A6 |
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4 |
11 |
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I/O0 |
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I/O0 |
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11 |
18 |
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I/O6 |
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A5 |
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5 |
10 |
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A0 |
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I/O1 |
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17 |
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I/O5 |
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12 |
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A4 |
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6 |
9 |
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A1 |
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I/O2 |
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16 |
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I/O4 |
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A3 |
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7 |
8 |
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A2 |
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13 |
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GND |
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15 |
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I/O3 |
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14 |
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PIN DESCRIPTIONS
A0-A14 |
Address Inputs |
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CE |
Chip Enable Input |
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OE |
Output Enable Input |
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WE |
Write Enable Input |
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I/O0-I/O7 |
Input/Output |
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Vcc |
Power |
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GND |
Ground |
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TRUTH TABLE
Mode |
WE |
CE |
OE |
I/O Operation |
Vcc Current |
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Not Selected |
X |
H |
X |
High-Z |
ISB1, ISB2 |
(Power-down) |
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Output Disabled |
H |
L |
H |
High-Z |
ICC |
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Read |
H |
L |
L |
DOUT |
ICC |
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Write |
L |
L |
X |
DIN |
ICC |
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ABSOLUTE MAXIMUM RATINGS(1)
Symbol |
Parameter |
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Value |
Unit |
VCC |
Power Supply Voltage Relative to GND |
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–0.5 to +4.6 |
V |
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VTERM |
Terminal Voltage with Respect to GND |
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–0.5 to +4.6 |
V |
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TBIAS |
Temperature Under Bias |
Com. |
–10 to +85 |
°C |
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Ind. |
–45 to +90 |
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TSTG |
Storage Temperature |
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–65 to +150 |
°C |
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PD |
Power Dissipation |
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1 |
W |
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IOUT |
DC Output Current |
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±20 |
mA |
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Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. I
11/09/99
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IS61LV256 |
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ISSI® |
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OPERATING RANGE |
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Range |
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Ambient Temperature |
Speed |
VCC |
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Commercial |
0°C to +70°C |
8, 10, 12 |
3.3V, +10%, –5% |
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15, 20 |
3.3V ± 10% |
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Industrial |
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–40°C to +85°C |
All |
3.3V + 10%, –5% |
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DC ELECTRICAL CHARACTERISTICS (Over Operating Range) |
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Symbol |
Parameter |
Test Conditions |
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Min. |
Max. |
Unit |
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VOH |
Output HIGH Voltage |
VCC = Min., IOH = –2.0 mA |
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2.4 |
— |
V |
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VOL |
Output LOW Voltage |
VCC = Min., IOL = 4.0 mA |
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— |
0.4 |
V |
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VIH |
Input HIGH Voltage |
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2.2 |
VCC + 0.3 |
V |
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VIL |
Input LOW Voltage(1) |
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–0.3 |
0.8 |
V |
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ILI |
Input Leakage |
GND ≤ |
VIN ≤ VCC |
Com. |
–1 |
1 |
µA |
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Ind. |
–5 |
5 |
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ILO |
Output Leakage |
GND ≤ |
VOUT ≤ VCC, Outputs Disabled Com. |
–1 |
1 |
µA |
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Ind. |
–5 |
5 |
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Notes:
1.VIL (min.) = –0.3V (DC); VIL (min.) = –2.0V (pulse width ≤ 2.0 ns).
VIH (max.) = VCC + 0.5V (DC); VIH (max.) = Vcc + 2.0V (pulse width ≤ 2.0 ns).
2.Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
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-8 ns(2) |
-10 ns(2) |
-12 ns |
-15 ns |
-20 ns |
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Sym. |
Parameter |
TestConditions |
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Min. Max. |
Min. Max. |
Min. Max. |
Min. Max. |
Min. Max. |
Unit |
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ICC |
VccDynamicOperating |
VCC =Max.,CE= VIL |
Com. |
— |
120 |
— |
110 |
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100 |
— |
90 |
— |
80 |
mA |
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SupplyCurrent |
IOUT = 0 mA, f = fMAX |
Ind. |
— |
— |
— |
120 |
— |
110 |
— |
100 |
— |
90 |
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ISB1 |
TTLStandbyCurrent |
VCC =Max., |
Com. |
— |
15 |
— |
10 |
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10 |
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10 |
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10 |
mA |
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(TTLInputs) |
VIN =VIH orVIL |
Ind. |
— |
— |
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20 |
— |
20 |
— |
20 |
— |
20 |
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CE≥ VIH, f = 0 |
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ISB2 |
CMOSStandby |
VCC =Max., |
Com. |
— |
2 |
— |
2 |
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2 |
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2 |
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2 |
mA |
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Current(CMOSInputs) |
CE≤ VCC –0.2V, |
Ind. |
— |
— |
— |
5 |
— |
5 |
— |
5 |
— |
5 |
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VIN >VCC –0.2V, or |
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VIN ≤ 0.2V, f = 0 |
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Notes:
1.At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2.Shaded area = PREPRODUCTION AVAILABILITY.
CAPACITANCE(1,2)
Symbol |
Parameter |
Conditions |
Max. |
Unit |
CIN |
Input Capacitance |
VIN = 0V |
6 |
pF |
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COUT |
Output Capacitance |
VOUT = 0V |
5 |
pF |
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Notes:
1.Tested initially and after any design or process changes that may affect these parameters.
2.Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
3 |
Rev. I
11/09/99