ISSI IS61LV12824-8TQ, IS61LV12824-12TQI, IS61LV12824-12TQ, IS61LV12824-12BI, IS61LV12824-10TQI Datasheet

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IS61LV12824

ISSI®

128K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY

DECEMBER 1999

FEATURES

•High-speed access time: 8, 9, 10, 12 ns

•CMOS low power operation

—756 mW (max.) operating @ 8 ns

—36 mW (max.) standby @ 8 ns

•TTL compatible interface levels

•Single 3.3V power supply

•Fully static operation: no clock or refresh required

•Three state outputs

•Available in 119-pin Plastic Ball Grid Array (PBGA) and 100-pin TQFP packages.

•Industrial temperature available

DESCRIPTION

The ISSI IS61LV12824 is a high-speed, static RAM organized as 131,072 words by 24 bits. It is fabricated using ISSI's highperformance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 8 ns with low power consumption.

When CE1, CE2 are HIGH and CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels.

Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE1, CE2, CE2 and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory.

The IS61LV12824 is packaged in the JEDEC standard 119-pin PBGA and 100-pin TQFP.

FUNCTIONAL BLOCK DIAGRAM

A0-A16		128K x 24
	DECODER	128K x 24
	DECODER	MEMORY ARRAY
		MEMORY ARRAY

VCC

GND

I/O

I/O0-I/O23 DATA COLUMN I/O

CIRCUIT

CE2

CE1

CE2

CONTROL

CIRCUIT

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

04/17/01

IS61LV12824

ISSI®

PIN CONFIGURATION - 119-pin PBGA

	1	2	3	4	5	6	7
A	NC	A11	A14	A15	A16	A4	NC

B	NC	A12	A13	CE1	A5	A3	NC

C	I/O16	NC	CE2	NC	CE2	NC	I/O0

D	I/O17	VCCQ	GND	GND	GND	VCCQ	I/O1

E	I/O18	GND	VCC	GND	VCC	GND	I/O2

F	I/O19	VCCQ	GND	GND	GND	VCCQ	I/O3

G	I/O20	GND	VCC	GND	VCC	GND	I/O4

H	I/O21	VCCQ	GND	GND	GND	VCCQ	I/O5

J	VCCQ	GND	VCC	GND	VCC	GND	VCCQ

K	I/O22	VCCQ	GND	GND	GND	VCCQ	I/O6

L	I/O23	GND	VCC	GND	VCC	GND	I/O7

M	I/O12	VCCQ	GND	GND	GND	VCCQ	I/O8

N	I/O13	GND	VCC	GND	VCC	GND	I/O9

P	I/O14	VCCQ	GND	GND	GND	VCCQ	I/O10

R	I/O15	NC	NC	NC	NC	NC	I/O11

T	NC	A10	A8	WE	A0	A1	NC

U	NC	A9	A7	OE	A6	A2	NC

PIN DESCRIPTIONS

A0-A16	Address Inputs

I/O0-I/O23	Data Inputs/Outputs

CE1, CE2	Chip Enable Input LOW

CE2	Chip Enable Input HIGH

OE	Output Enable Input

WE	Write Enable Input

NC	No Connection

Vcc	Power

VCCQ	I/O Power

GND	Ground

2 Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

04/17/01

IS61LV12824

ISSI®

PIN CONFIGURATION

100-Pin TQFP

Vcc

GND I/O16 I/O17 GND VccQ I/O18 I/O19 GND VccQ I/O20 I/O21

Vcc

NC GND I/O22 I/O23 VccQ GND I/O12 I/O13 VccQ GND I/O14 I/O15

Vcc

GND

NC	NC A11	A12	A13 A14 A15 CE2	Vcc GND	CE2 CE1 A16 A5 A4	A3	NC	NC	NC	NC


100 99 98 97			96 95 94 93	92 91 90 89 88 87 86		85 84 83 82 81
1										80
2										79
3										78
4										77
5										76
6										75
7										74
8										73
9										72
10										71
11										70
12										69
13										68
14										67
15										66
16										65
17										64
18										63
19										62
20										61
21										60
22										59
23										58
24										57
25										56
26										55
27										54
28										53
29										52
30										51
31 32 33		34 35 36 37 38 39 40			41 42 43 44 45 46 47 48 49 50


NC	NC NC	NC	A10 A9 A8 A7	OE GND	Vcc WE A6 A0 A1	A2	NC	NC	NC	NC

Vcc

GND I/O0 I/O1 GND VccQ I/O2 I/O3 GND VccQ I/O4 I/O5 Vcc NC NC GND I/O6 I/O7 VccQ GND I/O8 I/O9 VccQ GND I/O10 I/O11 Vcc GND NC

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

04/17/01

IS61LV12824							ISSI®
TRUTH TABLE

Mode	WE	CE1	CE2	CE2	OE	I/O0-I/O23	Vcc Current

Not Selected	X	H	X	X	X	High-Z	ISB1, ISB2
	X	X	L	X	X
	X	X	X	H	X

Output Disabled	H	L	H	L	H	High-Z	ICC

Read	H	L	H	L	L	DOUT	ICC

Write	L	L	H	L	X	DIN	ICC

ABSOLUTE MAXIMUM RATINGS(1)

Symbol	Parameter		Value	Unit
VCC	Power Supply Voltage Relative to GND		–0.5 to 5.0	V

VTERM	Terminal Voltage with Respect to GND		–0.5 to Vcc + 0.5	V

TSTG	Storage Temperature		–65 to + 150	°C

TBIAS	Temperature Under Bias:	Com.	–10 to + 85	°C
		Ind.	–45 to + 90	°C

PT	Power Dissipation		2.0	W

IOUT	DC Output Current		±20	mA

Note:

1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

OPERATING RANGE

Range	Ambient Temperature	VCC (8, 9 ns)	VCC (10, 12 ns)
Commercial	0°C to +70°C	3.3V + 10%, – 5%	3.3V ± 10%

Industrial	–40°C to +85°C	3.3V + 10%, – 5%	3.3V ± 10%

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol	Parameter	Test Conditions	Min.	Max.	Unit
VOH	Output HIGH Voltage	VCC = Min., IOH = –4.0 mA	2.4	—	V

VOL	Output LOW Voltage	VCC = Min., IOL = 8.0 mA	—	0.4	V

VIH	Input HIGH Voltage		2.2	VCC + 0.3	V

VIL	Input LOW Voltage(1)		–0.3	0.8	V
ILI	Input Leakage	GND ≤ VIN ≤ VCC	–1	1	µA
ILO	Output Leakage	GND ≤ VOUT ≤ VCC, Outputs Disabled	–1	1	µA

Note:

1.VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width ≤ 2.0 ns).

VIH (max.) = VCC + 0.3V DC; VIH (max.) = VCC + 2.0V AC (pulse width ≤ 2.0 ns).

4 Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

04/17/01

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