ISSI IS42G32256-8PQ, IS42G32256-7PQ, IS42G32256-10PQ Datasheet

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IS42G32256
IS42G32256
ISSI
ISSI
®
®
256K x 32 x 2 (16-Mbit) SYNCHRONOUS GRAPHICS RAM
FEATURES
• 256,144 words x 32 bits x 2-bank organization
• All inputs are sampled at the positive going edge of the system clock
• Dual internal bank control
• Single 3.3V ± 3V power supply
• Programmable mode register – Burst length (1, 2, 4, 8, and full page) – CAS latency (2 and 3) – Burst type: Sequential and Interleave
• Burst Read single-bit Write Operation
• Refresh capability – Auto, self-refresh
• 2,048 refresh cycles/32 ms
• LVTTL compatible inputs and outputs
• 100-pin PQFP (14mm x 20mm)
GRAPHIC FEATURES
• SMRS cycle
• Write per bit (old mask)
• Block write (eight columns)
DESCRIPTION
The ISSI IS42G32256 is a high-speed 16-Mbit CMOS Synchronous Graphics RAM organized as 256K words x 32 bits x 2 banks. With SGRAM, all input and output signals are synchronized with the rising edge of the system clock. Programmable Mode Register and Special Registers provide a choice of Read or Write burst lengths of 1, 2, 4, or 8 locations or a Full Page with burst termination options. The SGRAM performance is enhanced with the Write-per-bit (WPB) and eight columns of Block Write functions.
The IS42G32256 is ideal for high-performance, high­bandwidth applications including workstation graphics, set top box, games, and PC-2D/3D graphic applications.
ADVANCE INFORMATION
SEPTEMBER 1998
– Load mask register – Load color register
Table 1. Key Timing Parameters
Symbol Parameter -7 -8 -10 Units
tCK Clock Cycle Time 7 8 10 ns
Access Time @ CL = 3 6 6.5 7 ns Operating Frequency 143 125 100 MHz
This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR037-0C
09/10/98
1
IS42G32256
ISSI
®
CLK
CKE
CS RAS CAS
WE
DSF
DQM0-3
TIMING
REGISTER
BLOCK WRITE
CONTROL
LOGIC
COLUMN
MASK
REGISTER
PROGRAM
DQM0-3
LATENCY &
BURST LENGTH
CONTROL
MASK
COLUMN
WRITE LOGIC
SENSE
DECODER
REFRESH COUNTER
AMPLIFIER
MUX
256K x 32
MEMORY
CELL
ARRAY
ROW DECODER
ADDRESS BUFFER
INPUT REGISTER
ROW
MASK
REGISTER
COLOR
REGISTER
256K x 32
MEMORY
CELL
ARRAY
DATA IN
BUFFER
DATA OUT
BUFFER
SERIAL
COUNTER
COLUMN
ADDRESS BUFFER
DQ31-DQ0
DQM0-3
A0-A10CLOCK
Figure 1. IS42G32256 Functional Block Diagram
2
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR037-0C
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IS42G32256
DQ3
CCQ
V
DQ4 DQ5
GND
DQ6 DQ7
CCQ
V DQ16 DQ17
GND
DQ18 DQ19
CCQ
V
V
CC
GND DQ20 DQ21
GND
DQ22 DQ23
CCQ
V
DQM0 DQM2
WE CAS RAS
CS
BA (A10)
A8
ISSI
®
DQ2
GNDQDQ1
DQ0
VCCNCNCNCNCNCNCNCNCNCNCGND
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100 1 2 3 4 5
Q
6 7 8 9 10 11
Q
12 13 14 15 16 17 18 19
Q
20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
DQ31
DQ30
GNDQDQ29
46 47 48 49 50
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQ28
CCQ
V DQ27 DQ26 GND DQ25 DQ24
CCQ
V DQ15 DQ14 GND DQ13 DQ12
CCQ
V GND
CC
V DQ11 DQ10 GND DQ9 DQ8
CCQ
V NC DQM3 DQM1 CLK CKE DSF NC A9
Q
Q
Q
Figure 2. IS42G32256 Pin Configuration, 100-pin PQFP
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR037-0C
09/10/98
A0A1A2
CC
A3
NCNCNCNCNCNCNCNCNC
V
NC
A4A5A6
GND
A7
3
IS42G32256
Table 2. Pin Descriptions
Symbol Pin Number I/O Name and Function
A0-A9 30-34, 47-51 I Address: Row/Column addresses are multi-
plexed on the same pins. Row address: RA0­RA9 Column address: CA0-CA7
A10/BP 29 I Bank Select Address: Selects bank to be acti-
vated during row address latch time. Selects bank for read/write during column address latch time.
CAS
CKE 54 I Clock Enable: Masks system clock to freeze
CLK 55 I System Clock: Active on the positive going
CS
DQ0-DQ31 1, 3-4, 6-7, 9-10, I/O Data Input/Output: Data Inputs/Outputs are
12-13, 17-18, 20-21, 60-61, multiplexed on the same pins. 63-64, 68-69, 71-72, 74-75,
77-78, 81-81, 83-84, 97-98, 100
DQM0-DQM3 23-24, 56-57 I/O Data Input/Output Mask: Makes data output
DSF 53 Define Special Function: Enables write per bit,
RAS
WE
VCCQ 2, 8, 14, 22, 59, 67, 73, 76, 79 Supplies voltage for data output
Vcc 15, 35, 65, 96 Power Supply Voltage
GNDQ 5, 11, 19, 62, 70, 82, 99 Ground for DQ
GND 16, 46, 66, 85 Ground
NC 36-45, 52, 58, 86-95 No connect
26 I Column Address Strobe: Latches column ad-
dresses on the positive going edge of the CLK with
CAS
low. Enables column access.
operation from the next clock cycle. CKE should be enabled at least one clock + tCKS prior to new command. Disable input buffers for power down in standby.
edge to sample all inputs.
28 I Chip Select: Disables or enables device opera-
tion by masking or enabling all inputs except CLK, CKE and DQMX.
Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte Mask­ing)
block write and special mode register set.
27 I Row Address Strobe: Latches row addresses
on the positive going edge of the CLK with low. Enables row access and precharge.
25 I Write Enable: Enables write operation and row
precharge.
ISSI
RAS
®
4
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR037-0C
09/10/98
IS42G32256
Table 3. Frequency vs. AC Parameter Relationships IS42G32256: 7 ns (Unit: number of clocks)
CASCAS
CAS
CASCAS
Frequency Latency 63 ns 42 ns 21 ns 14 ns 20 ns 7 ns 7 ns 7 ns
143 MHz (7 ns) 396323111 125 MHz (8 ns) 386323111 100 MHz (10 ns) 275322111 83 MHz (12 ns) 264222111 75 MHz (13.4 ns) 254222111 66 MHz (15 ns) 253212111
IS42G32256: 8 ns (Unit: number of clocks)
CASCAS
CAS
CASCAS
Frequency Latency 70 ns 48 ns 24 ns 16 ns 20 ns 8 ns 8 ns 8 ns
125 MHz (8 ns) 396323111
tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL
tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL
ISSI
®
100 MHz (10 ns) 385322111 83 MHz (12 ns) 264222111 75 MHz (13.4 ns) 264222111 66 MHz (15 ns) 254222111 50 MHz (20 ns) 243211111
IS42G32256: 10 ns (Unit: number of clocks)
CASCAS
CAS
CASCAS
Frequency Latency 80 ns 50 ns 26 ns 20 ns 20 ns 10 ns 10 ns 10 ns
100 MHz (10 ns) 385322211 83 MHz (12 ns) 375322211 71 MHz (14 ns) 264222211 66 MHz (15 ns) 264222211 50 MHz (20 ns) 243211111 40 MHz (25 ns) 242211111
tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL
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IS42G32256
Table 4. Truth Table
ISSI
®
Function CKEn-1 CKEn
Mode Register Set Special Mode Register Set Auto Refresh Self Refresh, Entry Self Refresh, Exit
(2,3)
(2,3,8)
(4)
(4)
(4)
H X LLLLLX OP CODE H X LLLLHX OP CODE H H LLLHLXXXX H L LLLHLXXXX L H LHHHXXXXX
CSCS
CS
CSCS
RASRAS
RAS
RASRAS
CASCAS
CAS
CASCAS
WEWE
WE
WEWE
DSF DQM A10 A9 A8-A0
L H HXXXXXXXX
Bank Active/Row Address H X L L H H L X V Row Write Per Bit Disable
Bank Active/Row Address H X L L H H H X V Row Write Per Bit Enable
Read and Column Address H X LHLHLXVLColumn Auto Precharge Disable
Read and Column Address H X LHLHLXVHColumn Auto Precharge Enable
Write and Column Address H X L H L L L X V L Column Auto Precharge Disable
Write and Column Address H X L H L L L X V H Column Auto Precharge Enable
Block Write and Column Address H X L H L L H X V L Column Auto Precharge Disable
Block Write and Column Address H X L H L L H X V H Column Auto Precharge Enable
Burst Stop
(8)
(5,6)
(5,6,10)
(5)
(5,6)
(5,6)
(5,6,7,10)
(5,6)
(5,6,7,10)
Address Address Address Address Address Address Address Address
H X LHHLLXXXX Precharge Bank Selection H X L L H L L X V L X Precharge Both Banks H X L L H L L X X H X Clock Suspend or H L L H H H X X X X X
Active Power Down Entry H L H XXXXXXXX Clock Suspend or L H XXXXXXXXX
Active Power Down Exit Precharge Pover Down Mode Entry H L L H H H X X X X X
H L HXXXXXXXX Precharge Pover Down Mode Exit L H L VVVVXXXX
L H HXXXXXXXX
(9)
DQM
H X XXXXXVXXX No Operation Command H X L H H H X X X X X
H X HXXXXXXXX
Notes:
1. V = Valid, X = Don’t Care, H = Logic High, L = Logic Low
2. OP Code: Operand Code; A0-A10: Program keys (@MRS); A5, A6: LMR or LCR select. (@SMRS) Color register exists only
one per DQi which both banks share. So does Mask Register. Color or mask is loaded into chip through DQ pin.
3. MRS can be issued only at both banks precharge state. SMRS can be issued only if DQs are idle. A new command can be
issued at the next clock of MRS/SMRS.
4. Auto refresh functions as same as CBR refresh of DRAM. The automatical precharge without row precharge command is
meant by “Auto”. Auto/Self refresh can be issued only at both precharge state.
5. A10: bank select address. If “Low” at read, (block) write, row active and precharge, bank A is selected. If “High” at read,
(block) write, row active and precharge, bank B is selected. If A9 is “High” at row precharge, A10 is ignored and both banks are precharged.
6. It is determined at row active cycle whether normal/block write operates in write per bit mode or not. For A bank write, at A
bank row active, for B bank write, at B bank row active. Terminology: Write per bit = I/O mask. (Block) Write with write per bit mode = masked (block) write.
7. During burst read or write with auto precharge, new read/(block) write command cannot be issued. Another bank read/(block)
write command can be issued at t
RP after the end of burst.
8. Burst stop command is valid only at full page burst length.
9. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (write DQM latency is 0) but makes Hi-Z
state the data-out of 2 CLK cycles after. (Read DQM latency is 2.)
10. Graphic features added to SDRAMs original features. If SDF is tied to low, graphic functions are disabled and chip operates
as a 16M SDRAM with 32 DQs.
6
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR037-0C
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IS42G32256
ISSI
Table 5. SGRAM vs SDRAM
SDRAM Function MRS Bank Active Write
DSF LH L H LH
SGRAM Function MRS SMRS Bank Active Bank Active Normal Block
with with Write Write
Write per bit Write per bit
Disable Enable
Notes:
1. If DSF is low, SGRAM functionality is identical to SDRAM functionality.
2. SGRAM can be used as a unified memory by the appropriate DSF control; SGRAM = Graphic Memory + Main Memory.
Table 6. Mode Register Field Table to Program Modes Register Programmed with MRS
Address A10 A9 A8, A7 A6, A5, A4 A3 A2, A1, A0
Function RFU
(1)
W.B.L.
(2)
TM CAS Latency BT Burst Length
Test Mode CAS Latency Burst Type Burst Length
A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0 BT=1
00
Mode Register Set
0 0 0 Reserved 0 Sequential 0 0 0 1 Reserved 0 1 Vendor 0 0 1 1 Interleave 0 0 1 2 Reserved 10 Use 0 1 0 2 010 4 4 1 1 Only 0 1 1 3 0 1 1 8 8
Write Burst Length
1 0 0 Reserved 1 0 0 Reserved Reserved
A9 Length 1 0 1 Reserved 1 0 1 Reserved Reserved
0 Burst 1 1 0 Reserved 1 1 0 Reserved Reserved 1 Single Bit 1 1 1 Reserved 1 1 1 256(Full)
(3)
Reserved
®
Special mode Register Programmed with SMRS
Address A10, A9, A8, A7 A6 A5 A4, A3, A2, A1, A0
Function X LC
A6 Function A5 Function
Notes:
1. RFU (Reserved for Future Use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
3. The full column burst (256-bit) is available only at Sequential mode of burst type.
4. If LC and LM both high (1), data of mask and color register will be unknown.
(4)
Load Color Load Mask
0 Disable 0 Disable 1 Enable 1 Enable
LM
(4)
X
POWER UP SEQUENCE
1. Apply power and start clock, attempt to maintain DKE = “H” and the other pins are NOP condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200 µs.
3. Issue precharge commands for all banks of the devices.
4. Issue two or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
6. Sequence of 4 and 5 may be changed. The device is now ready for normal operation.
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IS42G32256
Table 7. Burst Sequence (Burst Length = 4)
Initial Address
A1 A0 Sequential Interleave
0 0 0123 0123 0 l 1230 1032
l 0 2301 2301
1 1 3012 3210
Table 8. Burst Sequence (Burst Length = 8)
Initial Address
A2 A1 A0 Sequential Interleave
000 01234567 01234567 001 12345670 10325476 010 23456701 23016745 011 34567012 32107654 100 45670123 45670123 101 56701234 54761032 110 67012345 67452301 111 70123456 76543210
ISSI
®
Table 10. Pixel to DQ Mapping (at Block Write)
Column Address 3 Byte 2 Byte 1 Byte 0 Byte
A2 A1 A0 I/O31-I/O24 I/O23-I/O16 I/O15-I/O8 I/O7-I/O0
0 0 0 DQ24 DQ 16 DQ8 DQ0 0 0 1 DQ25 DQ 17 DQ9 DQ1 0 1 0 DQ26 DQ18 DQ10 DQ2 0 1 1 DQ27 DQ19 DQ11 DQ3 1 0 0 DQ28 DQ20 DQ12 DQ4 1 0 1 DQ29 DQ21 DQ13 DQ5 1 1 0 DQ30 DQ22 DQ14 DQ6 1 1 1 DQ31 DQ23 DQ 15 DQ7
8
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ADVANCE INFORMATION SR037-0C
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IS42G32256
ISSI
®
DEVICE OPERATIONS Clock (CLK)
The clock input is used as the reference for all SGRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between VIL and VIH. During operation with CKE high all inputs are assumed to be in valid state (low or high) for the duration of setup and hold time around positive edge of the clock for proper functionality and Icc specifications.
Clock Enable (CKE)
The clock enable (CKE) gates the clock onto SGRAM. If CKE goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When both banks are in the idle state and CKE goes low synchronously with clock, the SGRAM enters the power down mode from the next clock cycle. The SGRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least “tSS+lCLOCK” before the high going edge of the clock, then the SGRAM becomes active from the same clock edge accepting all the input commands.
Bank Select (A10)
This SGRAM is organized as two independent banks of 262,144 words x 32 bits memory arrays. The A10 inputs are latched at the time of assertion of select the bank to be used for the operation. When A10 is asserted low, bank A is selected. When A10 is latched high, bank B is selected. The banks select Al0 is latched at bank activate, read, write, mode register set and precharge operations.
RAS
and
CAS
to
Address Inputs (A0-A9)
The 18 address bits are required to decode the 262,144 word locations are multiplexed into ten address input pins (A0-A9). The 10-bit row address is latched along with and A10 during bank activate command. The 8-bit column address is latched along with read or with command.
CAS, WE
and A10 during
RAS
NOP and Device Deselect
When
RAS, CAS
no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock cycle like bank activate,
and WE are high, The SGRAM performs
burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that the address inputs are ignored.
RAS, CAS, WE
, DSF and all
Power-up
The following sequence is recommended for Power-up:
1. Power must be applied to either CKE and DQM inputs to pull them high and other pins are NOP condition at the condition at the inputs before or along with VDD (and VDDQ) supply.
The clock signal must also be asserted at the same time.
2. After VDD reaches the desired voltage, a minimum pause of 200 microseconds is required with inputs in NOP condition.
3. Both banks must be precharged now.
4. Perform a minimum of two auto refresh cycles to stabilize the internal circuitry.
5. Perform a Mode Register Set cycle to program the
CAS
latency, burst length and burst type as the default
value of mode register is undefined.
At the end of one clock cycle from the mode register set cycle, the device is ready for operation.
When the above sequence is used for Power-up, all the outputs will be in high-impedance state. The high­impedance of outputs is not guaranteed in any other power-up sequence.
Note: Sequence of 4 and 5 may be changed.
Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of SGRAM. It programs the latency, burst type, addressing, burst length, test mode and various vendor specific options to make SGRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SGRAM. The mode register is written by asserting low on
CS, RAS, CAS, WE
active mode with CKE already high prior to writing the mode register). The state of address pins A0-A9 and A10 in the same cycle as CS, is the data written in the mode register. One clock cycles is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as both banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length field uses A0-A2, burst type
and DSF (The SGRAM should be in
RAS, CAS, WE
and DSF going low
CAS
Integrated Silicon Solution, Inc.
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IS42G32256
ISSI
®
uses A3, A4-A6, A7-A8 and A10 are uses for vendor specific options or test mode use. And the write burst length is programmed using A9. A7-A8 and A10 must be set to low for normal SGRAM operation. Refer to the table for specific codes for various burst length, addressing modes and
CAS
latency (read latency from column address)
CAS
latencies.
Bank Activate
The bank activate command is used to select a random row in an idle bank. By asserting low on desired row and bank addresses, a row access is initiated. The read or write operation can occur after a time delay of tRCD (min) from the time of bank activation. tRCD (min) is the internal timing parameter of SGRAM, therefore it is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing tRCD (min) with cycle time of the clock and then rounding of the result to the next higher integer. The SGRAM has two internal banks in the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of both banks immediately. Also the noise generated during sensing of each bank of SGRAM is high requiring some time for power supplies to recover before another bank can be sensed reliably. tRRD (min) specifies the minimum time required between activating different bank. The number of clock cycles required between different bank activation must be calculated similar to tRCD specification. The minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by tRAS (min). Every SGRAM bank activate command must satisfy tRAS (min) specification before a precharge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by tRAS (max). The number of cycles for both tRAS (min) and tRAS (max) can be calculated similar to tRCD specification.
RAS
and CS with
Burst Read
The burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The burst read command is issued by asserting low on CS and the clock. The bank must be active for at least tRCD (min) before the burst read command is issued. The first output appears in issue of burst read command. The burst length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in the mode register. The output
RAS
with WE being high on the positive edge of
CAS
latency number of clock cycles after the
goes into high-impedance at the end of burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. The burst stop command is valid for all burst length.
Burst Write
The burst write command is similar to burst read command, and is used to write data into the SGRAM on consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. By asserting low on CS, and WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even though the internal writing may not have been completed yet. The writing can not complete burst length. The burst write can be terminated by issuing a burst read and DQM for blocking data inputs or burst write in the same or the other active bank.
The write burst can also be terminated by using DQM for blocking data and precharging the bank “tRDL” after the last data input to be written into the active row. See DQM Operation also.
CAS
DQM Operation
The DQM is used mask input and output operations. It works similar to OE during operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock. The DQM signal is important during burst interrupts of write with read or precharge in the SGRAM. Due to asynchronous nature of the internal write, the DQM operation is critical to avoid unwanted or incomplete writes when the complete burst write is required. DQM is also used for device selection and bus control in a memory system. DQM0 controls DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23, DQM3 controls DQ24 to DQ31. DQM masks the DQs by a byte regardless that the corresponding DQs are in a state of WPB masking or Pixel masking. Please refer to DQM timing diagram also.
Precharge
The precharge is performed on an active bank by asserting low on CS, be precharged. The precharge command can be asserted anytime after tRAS (min) is satisfy from the bank activate command in the desired bank. “tRP” is defined as the minimum time required to precharge a bank.
RAS, WE
and A9 with valid A10 of the bank to
10
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IS42G32256
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®
The minimum number of clock cycles required to complete row precharge is calculated by dividing “tRP” with clock cycle time and rounding up to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can be active is specified by tRAS (max). Therefore, each bank has to be precharged within tRAS (max) from the bank activate command. At the end of precharge, the bank enters the idle state and is ready to be activated again.
Entry to Power Down, Auto refresh, Self refresh and Mode register Set etc. is possible only when both banks are in idle state.
Auto Precharge
The precharge operation can also be performed by using auto precharge. The SGRAM internally generates the timing to satisfy tRAS (min) and “tRP” for the programmed burst length and command is issued at the same time as burst write by asserting high on A9. If burst read or burst write command is issued with low on A9, the bank is left active until a new command is asserted. Once auto precharge command is given, no new command are possible to that particular bank until the bank achieves idle state.
CAS
latency. The auto precharge
Both Banks Precharge
Both banks can be precharged at the same time by using Precharge all command. Asserting low on CS,
WE
with high on A9 after all banks have satisfied tRAS (min) requirement, performs precharge on both banks. At the end of tRP after performing precharge all, all banks are in idle state.
RAS
and
Auto Refresh
The storage cells of SGRAM need to be refreshed every 32 ms to maintain data. An auto refresh cycle accomplishes refresh of a single row of storage cells. The internal counter increments automatically on every auto refresh cycle to refresh all the rows. An auto refresh command is issued by asserting low on CS,
WE
. The auto refresh command can only be asserted with both banks being in idle state and the device is not in power down mode (CKE is high in the previous cycle). The time required to complete the auto refresh operation is specified by tRC (min). The minimum number of clock cycles required can be calculated by driving tRC with clock cycle time and them rounding up to the next higher integer. The auto refresh command must be followed by NOPs until the auto refresh operation is completed. Both banks will be in the idle state at the end of auto refresh operation. The auto
RAS
and
CAS
with high on CKE and
refresh is the preferred refresh mode when the SGRAM is being used for normal data transactions. The auto refresh cycle can be performed once in 15.6 µs or the burst of 2048 auto refresh cycles in 32 ms.
Self Refresh
The self refresh is another refresh mode available in the SGRAM. The self refresh is the preferred refresh mode for data retention and low power operation of SGRAM. In self refresh mode, the SGRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing is internally generated to reduce power consumption.
The self refresh mode is entered from all banks idle state by asserting low on CS,
WE
. Once the self refresh mode is entered, only CKE state being low matters, all the other inputs including clock are ignored to remain in the refresh.
The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP’s for a minimum time of tRC before the SGRAM reaches idle state to begin normal operation. If the system uses burst auto refresh during normal operation, it is recommended to use burst 2048 auto refresh cycles immediately after exiting self refresh.
RAS, CAS
and CKE with high on
Define Special Function (DSF)
The DSF controls the graphic applications of SGRAM. If DSF is tied to low, SGRAM functions as 256K x 32 x 2 Bank SGRAM. SGRAM can be used as an unified memory by the appropriate DSF command. All the graphic function mode can be entered only by setting DSF high when issuing commands which otherwise would be normal SGRAM commands.
SGRAM functions such as change to SGRAM functions such as WPB, Block Write and SWCBR respectively that DSF controls.
RAS
Active, Write and WCBR
RAS
Active with
Special Mode Register Set (SMRS)
There are two kinds of special mode registers in SGRAM. One is color register and the other is mask register. Those usage will be explained at “Write Per Bit” and “Block Write” session. When A5 and DSF goes high in the same cycle as CS, filled with color data for associated DQ’s through the DQ pins. If both A5 and A6 are high at SMRS, data of mask and color cycle is required to complete the write in the mask register and the color register at LMR and LCR respectively. The next color of LMR and LCR, a new commands can be
RAS, CAS
and WE going low, load color register is
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR037-0C
09/10/98
11
IS42G32256
CLK
CKE
CS
RAS
CAS
WE
DSF
2 CLK BW
HIGH
ISSI
®
issued. SMRS, compared with MRS, can be issued at the active state under the condition that DQs are idle. As in write operation, SMRS accepts the data needed through DQ pins. Therefore it should be attended not to induce bus contention. The more detailed materials can be obtained by referring corresponding timing diagram.
Write Per Bit
Write per bit (i.e., I/O mask mode) for SGRAM is a function that selectively masks bits of data being written to the devices. The mask is stored in an internal register and applied to each bit of data written when enable. Bank active command with DSF=High enable write per bit for the associated bank. The mask used for write per bit operations is stored in the mask register accessed by SWCBR (Special Mode Register Set Command). When a mask bit=0, the associated data bit is unaltered when a write command is executed and the write per bit has been enable for the bank being written. No additional timing conditions. Write per bit writes can be either masking is the same for write per bit and non-WPB write.
Block Write
Block write is a feature allowing the simultaneous writing of consecutive eight columns of data within a RAM device during a single access cycle. During block write the data to be written comes from the internal “color” register and DQ I/O pins are used for independent column selection. The block of column to be written is aligned on 8-column boundaries and is defined by the column address with the three LSBs ignored. Write command with DSF=1 enable block write for the associated bank. The block width is eight columns where column =“n” bits for by “n” part. The color register is the same width as the data port of the chip. It is width via a SWCBR where data present on the DQ pins is to be coupled into the internal color register. The color register provides the data masked by the DQ column select, WPB mask (if enable), and DQM byte mask. Column data masking (Pixel masking) is provided on an individual column basis for each byte of data. The column mask is driven on the DQ pins during a block write command. The DQ column mask function is segmented on a per bit basis (i.e., DQ[0:7] provided the column mask for data bits [0:7], DQ[8:15] provided the column mask for data bits [8:15], DQ0 masks column [0] for data bits [0:7], DQ9 masks column [1] for data bits [8:15], etc.). Block writes are always non-burst independent of the burst length that has been programmed into to the mode register. If write per bit was enabled by the bank active command with DSF=1, then write per bit masking of the color register data is enabled.
If write per bit was disabled by a bank active command with DSF=0, the write per bit masking of the color register data is disabled. DQM masking provides independent data byte masking during normal write operations, except that the control is extended to the consecutive eight columns of the block write.
Figure 3. Timing Diagram to Illustrate tBWC.
(2CLK Clcle Block Write)
12
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR037-0C
09/10/98
IS42G32256
Table 11. Summary of SGRAM Basic Features and Benefits
Features 256K x 32 x 2 SGRAM Benefits
Interface Synchronous Better interaction between memory and system without wait-
state of asynchronous DRAM. High speed vertical and horizontal drawing. High operation frequency allows performance gain for SCROLL, FILL, and BitBLT.
Bank 2 each Pseudo-infinite row length by on-chip interleaving operation.
Hidden row activation precharge. Page Depth /1 Row 256 bit High-speed vertical and horizontal drawing. Total Page Depth 2048 bytes High speed vertical and horizontal drawing. Burst Length (Read) 1, 2, 4, 8 Full Page Programmable burst of 1, 2, 4, 8 and full page transfer per
column address. Burst Length (Write) 1 2 4 8 Full Page Programmable burst of 1, 2, 4, 8 and full page transfer per
column address.
BRSW Switch to burst length of 1 at write without MRS. Burst Type Sequential & Interleave Compatible with Intel and Motorola CPU based system. CAS Latency 2, 3 Programmable CAS latency. Block Write 8-Column High speed FILL, CLEAR, Text with color registers.
Maximum 32-byte data transfer (e.g., for 8bpp: 32 pixels) with
plane and byte masking functions. Color Register 1 each A and B bank share. Mask Register 1 each Write-per-bit capability (bit plane masking). A and B bank
share.
DQM0-3 Byte masking (pixel masking for 8bpp system) for data-out/in.
Mask function Write per bit Each bit of the mask register directly controls a corresponding
bit plane.
Pixel Mask at Block Write Byte masking (pixel masking for 8bpp system) for color DQi.
ISSI
®
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR037-0C
09/10/98
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IS42G32256
BASIC FEATURES AND FUNCTION DESCRIPTION
1. CLOCK SUSPENDED DURING WRITE (BURST LENGTH = 4) 2. CLOCK SUSPENDED DURING READ (BURST LENGTH = 4)
CLK
COMMAND
CKE
INTERNAL
CLK
DQ (CLOCK
LATENCY = 2)
DQ (CLOCK
LATENCY = 3)
Note:
1. CKE to CLK disable/enable = 1 clock.
WR RD
MASKED BY CKE
D0
D1 D2 D3
D0 D1 D2 D3
NOT WRITTEN SUSPENDED DOUT
Figure 4. Clock Suspend
MASKED BY CKE
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
ISSI
®
1. WRITE MASK (BURST LENGTH = 4) 2. READ MASK (BURST LENGTH = 4)
CLK
COMMAND
DQM
DQ (CLOCK LATENCY = 2)
DQ (CLOCK LATENCY = 3)
CLK
COMMAND
CKE
DQM
DQ (CLOCK LATENCY = 2)
DQ (CLOCK LATENCY = 3)
WR
MASKED BY CKE
D0
D1 D3
D0 D1
DQM TO DATA IN MASK = 0 CLK
3. DQM WITH CLOCK SUSPEND (FULL PAGE READ) NOTE 2
RD
Q0 Q2 Q4
HI-Z HI-Z HI-Z
HI-Z HI-Z HI-Z
Q1 Q3 Q5 Q6 Q7
RD
Notes:
1. There are four DQMi (i = 0-3). Each DQMi masks eight DQs. (One Byte, one Pixel for 8bpp.)
2. DQM masks data out Hi-Z after two clocks which should be masked by CKE “L”.
MASKED BY CKE
HI-Z
Q0 Q2 Q3
HI-Z
Q1 Q2 Q3
DQM TO DATA OUT MASK = 2
Q6 Q7 Q8
14
Figure 5. DQM Operation
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR037-0C
09/10/98
IS42G32256
1. READ INTERRUPTED BY READ (BURST LENGTH = 4) (SEE NOTE 1.)
CLK
COMMAND
ADD
DQ (CLOCK
LATENCY = 2)
DQ (CLOCK
LATENCY = 3)
RD RD
A B
t
CCD
(SEE NOTE 2)
QA0 QB0 QB1 QB2 QB3
QA0 QB0 QB3
QB1 QB2
ISSI
®
CLK
COMMAND
ADD
DQ
CLK
COMMAND
ADD
DQ
2. WRITE INTERRUPTED BY (BLOCK) WRITE (BURST LENGTH = 2)
WR WR WR BW
t
CCD (NOTE 2)
A B A B
DA0 DB0 DB1
t
CDL
(NOTE 3)
4. BLOCK WRITE TO BLOCK WRITE
BW NOP BW
(NOTE 7)
A X B
PIXEL PIXEL
t
BWC
(NOTE 6)
t
CCD (NOTE 2)
t
CDL
(NOTE 3
(NOTE 4)
DC0 PIXEL
DQ (CLOCK
LATENCY = 2)
DQ (CLOCK
LATENCY = 3)
3. WRITE INTERRUPTED BY READ (BURST LENGTH = 2)
WR RD
t
CCD (NOTE 2)
A B
DA0 DB0 DB1
DA0 DB0 DB1
(NOTE 3)
Notes:
1. By “Interrpt”, it is possible to stop burst read/write by external before the end of burst. By “
CAS
CCD:
Interrupt”, to stop burst read/write by
CAS
to
CAS
2. t
CDL: Last data in to new column address delay (=1CLK).
3. t
delay (=1CLK).
CAS
access; read, write, and block write.
4. Pixel: Pixel mask.
CC: Clock cycle time.
5. t
BWC: Block write minimum cycle time.
6. t
7. Other bank can be active or precharge.
t
CDL
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR037-0C
09/10/98
Figure 6.
CASCAS
CAS
Interrupt (I)
CASCAS
15
IS42G32256
1. CLOCK LATENCY = 2, BURST LENGTH = 4.
CLK
ISSI
®
CMD 1
DQM
DQ
CMD 2
DQM
DQ
CMD 3
DQM
DQ
CMD 4
DQM
DQ
CLK
CMD 1
DQM
RD RD
D0 D1 D2 D3
RD WR
HI-Z
D0
RD WR
RD WR
D1 D2 D3
HI-Z
D0
HI-Z
(NOTE 1)
2. CLOCK LATENCY = 3, BURST LENGTH = 4.
RD WR
D1 D2 D3
D0Q0
D1 D2 D3
DQ
CMD 2
RD WR
D0 D1 D2 D3
DQM
DQ
CMD 3
RD WR
D0 D1 D2 D3
DQM
DQ
CMD 4
RD WR
D0 D1 D2 D3
DQM
DQ
CMD 5
D0Q0
RD WR
D1 D2 D3
HI-Z
DQM
(NOTE 2)
HI-Z
D0Q0
D1 D2 D3
DQ
Notes:
1. To prevent bus contention, there should be at least one gap between data in and data out.
2. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
Figure 7.
CASCAS
CAS
Interrupt (II): Read Interrupted by Write and DQM
CASCAS
16
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR037-0C
09/10/98
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