IS41C4400X |
® |
IS41LV4400X SERIES |
ISSI |
4M x 4 (16-MBIT) DYNAMIC RAM |
|
WITH EDO PAGE MODE |
JUNE, 2001 |
FEATURES
•Extended Data-Out (EDO) Page Mode access cycle
•TTL compatible inputs and outputs
•Refresh Interval:
–2,048 cycles/32 ms
–4,096 cycles/64 ms
•Refresh Mode: RAS-Only,
CAS-before-RAS (CBR), and Hidden
•Single power supply:
– 5V±10% or 3.3V ± 10%
•Byte Write and Byte Read operation via two CAS
•Industrial temperature range -40°C to 85°C
PRODUCT SERIES OVERVIEW
Part No. |
Refresh |
Voltage |
IS41C44002 |
2K |
5V ± 10% |
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IS41C44004 |
4K |
5V ± 10% |
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IS41LV44002 |
2K |
3.3V ± 10% |
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IS41LV44004 |
4K |
3.3V ± 10% |
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DESCRIPTION
The ISSI 4400 Series is a 4,194,304 x 4-bit high-performance CMOS Dynamic Random Access Memory. These devices offer an accelerated cycle access called EDO Page Mode. EDO Page Mode allows 2,048 or 4096 random accesses within a single row with access cycle time as short as 20 ns per 4-bit word.
These features make the 4400 Series ideally suited for high-bandwidth graphics, digital signal processing, high-performance computing systems, and peripheral applications.
The 4400 Series is packaged in a 24-pin 300-mil SOJ with JEDEC standard pinouts.
KEY TIMING PARAMETERS
Parameter |
-50 |
-60 |
Unit |
RASAccess Time (tRAC) |
50 |
60 |
ns |
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CASAccess Time (tCAC) |
13 |
15 |
ns |
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Column Address Access Time (tAA) |
25 |
30 |
ns |
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EDO Page Mode Cycle Time (tPC) |
20 |
25 |
ns |
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Read/Write Cycle Time (tRC) |
84 |
104 |
ns |
PIN CONFIGURATION
24 Pin SOJ
VCC |
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1 |
24 |
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GND |
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I/O0 |
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23 |
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I/O3 |
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2 |
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I/O1 |
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22 |
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I/O2 |
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3 |
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21 |
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WE |
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4 |
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CAS |
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20 |
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RAS |
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5 |
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OE |
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*A11(NC) |
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19 |
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A9 |
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6 |
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A10 |
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18 |
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A8 |
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7 |
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A0 |
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17 |
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A7 |
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8 |
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A1 |
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16 |
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A6 |
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9 |
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A2 |
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15 |
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A5 |
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10 |
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A3 |
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14 |
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A4 |
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11 |
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VCC |
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12 |
13 |
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GND |
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* A11 is NC for 2K Refresh devices.
PIN DESCRIPTIONS
A0-A11 |
Address Inputs (4K Refresh) |
A0-A10 |
Address Inputs (2K Refresh) |
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I/O0-3 |
Data Inputs/Outputs |
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WE |
Write Enable |
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OE |
Output Enable |
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RAS |
Row Address Strobe |
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CAS |
Column Address Strobe |
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Vcc |
Power |
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GND |
Ground |
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NC |
No Connection |
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ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
1 |
Rev. D
06/24/01
IS41C4400X |
ISSI |
® |
IS41LV4400X SERIES |
|
FUNCTIONAL BLOCK DIAGRAM
OE |
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WE |
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CAS |
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WE |
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OE |
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CAS |
CONTROL |
CAS |
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CONTROL |
CONTROL |
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LOGIC |
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LOGICS |
WE |
LOGIC |
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OE |
RAS |
RAS |
RAS |
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DATA I/O BUS |
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CLOCK |
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GENERATOR |
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COLUMN DECODERS |
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REFRESH |
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SENSE AMPLIFIERS |
I/O BUFFERS |
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COUNTER |
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I/O0-I/O3 |
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DECODER |
MEMORY ARRAY |
DATA |
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4,194,304 x 4 |
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ADDRESS |
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ROW |
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A0-A10(A11) |
BUFFERS |
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TRUTH TABLE
Function |
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RAS |
CAS |
WE |
OE |
Address tR/tC |
I/O |
Standby |
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H |
H |
X |
X |
X |
High-Z |
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Read |
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L |
L |
H |
L |
ROW/COL |
DOUT |
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Write: Word (Early Write) |
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L |
L |
L |
X |
ROW/COL |
DIN |
Read-Write |
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L |
L |
H→L |
L→H |
ROW/COL |
DOUT, DIN |
EDO Page-Mode Read |
1st Cycle: |
L |
H→L |
H |
L |
ROW/COL |
DOUT |
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2nd Cycle: |
L |
H→L |
H |
L |
NA/COL |
DOUT |
EDO Page-Mode Write |
1st Cycle: |
L |
H→L |
L |
X |
ROW/COL |
DIN |
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2nd Cycle: |
L |
H→L |
L |
X |
NA/COL |
DIN |
EDO Page-Mode |
1st Cycle: |
L |
H→L |
H→L |
L→H |
ROW/COL |
DOUT, DIN |
Read-Write |
2nd Cycle: |
L |
H→L |
H→L |
L→H |
NA/COL |
DOUT, DIN |
Hidden Refresh |
Read |
L→H→L |
L |
H |
L |
ROW/COL |
DOUT |
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Write(1) |
L→H→L |
L |
L |
X |
ROW/COL |
DOUT |
RAS-Only Refresh |
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L |
H |
X |
X |
ROW/NA |
High-Z |
CBR Refresh |
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H→L |
L |
X |
X |
X |
High-Z |
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Note: |
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1. EARLY WRITE only. |
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2 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
06/24/01
IS41C4400X |
ISSI |
® |
IS41LV4400X SERIES |
|
Functional Description
The IS41C4400x and IS41LV4400x are CMOS DRAMs optimized for high-speed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 11 or 12 address bits. These are entered 11 bits (A0-A10) at a time for the 2K refresh device or 12 bits (A0-A11) at a time for the 4K refresh device. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first nine bits and CAS is used the latter ten bits.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA, tCAC and tOEA are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs last.
Auto Refresh Cycle
To retain data, 2,048 refresh cycles are required in each 32 ms period, or 4,096 refresh cycles are required in each 64ms period. There are two ways to refresh the memory:
1.By clocking each of the 2,048 row addresses (A0 through A10) or 4096 row addresses (A0 through A11) with RAS at least once every 32 ms or 64ms respectively. Any read, write, read-modify-write or RAS-only cycle refreshes the addressed row.
2.Using a CAS-before-RAS refresh cycle. CAS-before-RAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 9-bit counter provides the row addresses and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle.
Power-On
After application of the VCC supply, an initial pause of 200 µs is required followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS signal).
During power-on, it is recommended that RAS track with VCC or be held at a valid VIH to avoid current surges.
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
3 |
Rev. D
06/24/01
IS41C4400X |
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ISSI |
® |
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IS41LV4400X SERIES |
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ABSOLUTE MAXIMUM RATINGS(1) |
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Symbol |
Parameters |
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Rating |
Unit |
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VT |
Voltage on Any Pin Relative to GND |
5V |
–1.0 to +7.0 |
V |
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3.3V |
–0.5 to +4.6 |
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VCC |
Supply Voltage |
5V |
–1.0 to +7.0 |
V |
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3.3V |
–0.5 to +4.6 |
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IOUT |
Output Current |
|
50 |
mA |
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PD |
Power Dissipation |
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1 |
W |
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TA |
Commercial Operation Temperature |
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0 to +70 |
°C |
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Industrial Operation Temperature |
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-40 to +85 |
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TSTG |
Storage Temperature |
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–55 to +125 |
°C |
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Note:
1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol |
Parameter |
|
Min. |
Typ. |
Max. |
Unit |
VCC |
Supply Voltage |
5V |
4.5 |
5.0 |
5.5 |
V |
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3.3V |
3.0 |
3.3 |
3.6 |
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VIH |
Input High Voltage |
5V |
2.4 |
— |
VCC + 1.0 |
V |
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3.3V |
2.0 |
— |
VCC + 0.3 |
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VIL |
Input Low Voltage |
5V |
–1.0 |
— |
0.8 |
V |
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3.3V |
–0.3 |
— |
0.8 |
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TA |
Commercial Ambient Temperature |
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0 |
— |
70 |
°C |
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Industrial Ambient Temperature |
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-40 |
— |
85 |
°C |
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CAPACITANCE(1,2)
Symbol |
Parameter |
Max. |
Unit |
CIN1 |
Input Capacitance: A0-A10(A11) |
5 |
pF |
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CIN2 |
Input Capacitance: RAS, CAS, WE, OE |
7 |
pF |
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CIO |
Data Input/Output Capacitance: I/O0-I/O3 |
7 |
pF |
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Notes:
1.Tested initially and after any design or process changes that may affect these parameters.
2.Test conditions: TA = 25°C, f = 1 MHz.
4 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
06/24/01
IS41C4400X |
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ISSI |
® |
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IS41LV4400X SERIES |
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ELECTRICAL CHARACTERISTICS(1) |
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(Recommended Operating Conditions unless otherwise noted.) |
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Symbol |
Parameter |
Test Condition |
VCC |
Speed |
Min. |
Max. |
Unit |
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IIL |
Input Leakage Current |
Any input 0V ≤ VIN ≤ Vcc |
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–5 |
5 |
µA |
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Other inputs not under test = 0V |
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IIO |
Output Leakage Current |
Output is disabled (Hi-Z) |
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–5 |
5 |
µA |
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0V ≤ VOUT ≤ Vcc |
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VOH |
Output High Voltage Level |
IOH = –5.0 mA, Vcc = 5V |
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2.4 |
— |
V |
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IOH = –2.0 mA, Vcc = 3.3V |
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VOL |
Output Low Voltage Level |
IOL = 4.2 mA, Vcc = 5V |
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— |
0.4 |
V |
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IOL = 2 mA, Vcc = 3.3V |
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ICC1 |
Standby Current: TTL |
RAS, CAS ≥ VIH Commercial |
5V |
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— |
2 |
mA |
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3.3V |
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— |
0.5 |
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Industrial |
5V |
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— |
3 |
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3.3V |
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— |
2 |
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ICC2 |
Standby Current: CMOS |
RAS, CAS ≥ VCC – 0.2V |
5V |
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— |
1 |
mA |
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3.3V |
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— |
0.5 |
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ICC3 |
Operating Current: |
RAS, CAS, |
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-50 |
— |
120 |
mA |
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Random Read/Write(2,3,4) |
Address Cycling, tRC = tRC (min.) |
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-60 |
— |
110 |
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Average Power Supply Current |
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ICC4 |
Operating Current: |
RAS = VIL, CAS, |
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-50 |
— |
90 |
mA |
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EDO Page Mode(2,3,4) |
Cycling tPC = tPC (min.) |
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-60 |
— |
80 |
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Average Power Supply Current |
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ICC5 |
Refresh Current: |
RAS Cycling, CAS ≥ VIH |
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-50 |
— |
120 |
mA |
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RAS-Only(2,3) |
tRC = tRC (min.) |
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-60 |
— |
110 |
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Average Power Supply Current |
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ICC6 |
Refresh Current: |
RAS, CAS Cycling |
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-50 |
— |
120 |
mA |
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CBR(2,3,5) |
tRC = tRC (min.) |
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-60 |
— |
110 |
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Average Power Supply Current |
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Notes:
1.An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2.Dependent on cycle rates.
3.Specified values are obtained with minimum cycle time and the output open.
4.Column-address is changed once each EDO page cycle.
5.Enables on-chip refresh and address counters.
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
5 |
Rev. D
06/24/01
IS41C4400X |
ISSI |
® |
IS41LV4400X SERIES |
|
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
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-50 |
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-60 |
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Symbol |
Parameter |
Min. |
Max. |
Min. |
Max. |
Units |
tRC |
Random READ or WRITE Cycle Time |
84 |
— |
104 |
— |
ns |
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tRAC |
Access Time from RAS(6, 7) |
— |
50 |
— |
60 |
ns |
tCAC |
Access Time from CAS(6, 8, 15) |
— |
13 |
— |
15 |
ns |
tAA |
Access Time from Column-Address(6) |
— |
25 |
— |
30 |
ns |
tRAS |
RAS Pulse Width |
50 |
10K |
60 |
10K |
ns |
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tRP |
RAS Precharge Time |
30 |
— |
40 |
— |
ns |
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tCAS |
CAS Pulse Width(23) |
8 |
10K |
10 |
10K |
ns |
tCP |
CAS Precharge Time(9) |
9 |
— |
9 |
— |
ns |
tCSH |
CAS Hold Time (21) |
38 |
— |
40 |
— |
ns |
tRCD |
RAS to CAS Delay Time(10, 20) |
12 |
37 |
14 |
45 |
ns |
tASR |
Row-Address Setup Time |
0 |
— |
0 |
— |
ns |
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tRAH |
Row-Address Hold Time |
8 |
— |
10 |
— |
ns |
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tASC |
Column-Address Setup Time(20) |
0 |
— |
0 |
— |
ns |
tCAH |
Column-Address Hold Time(20) |
8 |
— |
10 |
— |
ns |
tAR |
Column-Address Hold Time |
30 |
— |
40 |
— |
ns |
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(referenced to RAS) |
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tRAD |
RAS to Column-Address Delay Time(11) |
10 |
25 |
12 |
30 |
ns |
tRAL |
Column-Address to RAS Lead Time |
25 |
— |
30 |
— |
ns |
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tRPC |
RAS to CAS Precharge Time |
5 |
— |
5 |
— |
ns |
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tRSH |
RAS Hold Time |
8 |
— |
10 |
— |
ns |
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tRHCP |
RAS Hold Time from CAS Precharge |
30 |
— |
35 |
— |
ns |
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tCLZ |
CAS to Output in Low-Z(15, 24) |
0 |
— |
0 |
— |
ns |
tCRP |
CAS to RAS Precharge Time(21) |
5 |
— |
5 |
— |
ns |
tOD |
Output Disable Time(19, 24) |
3 |
15 |
3 |
15 |
ns |
tOE |
Output Enable Time(15, 16) |
— |
12 |
— |
15 |
ns |
tOED |
Output Enable Data Delay (Write) |
12 |
— |
15 |
— |
ns |
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tOEHC |
OE HIGH Hold Time from CAS HIGH |
5 |
— |
5 |
— |
ns |
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tOEP |
OE HIGH Pulse Width |
10 |
— |
10 |
— |
ns |
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tOES |
OE LOW to CAS HIGH Setup Time |
5 |
— |
5 |
— |
ns |
|
|
|
|
|
|
|
tRCS |
Read Command Setup Time(17, 20) |
0 |
— |
0 |
— |
ns |
tRRH |
Read Command Hold Time |
0 |
— |
0 |
— |
ns |
|
(referenced to RAS)(12) |
|
|
|
|
|
tRCH |
Read Command Hold Time |
0 |
— |
0 |
— |
ns |
|
(referenced to CAS)(12, 17, 21) |
|
|
|
|
|
tWCH |
Write Command Hold Time(17) |
8 |
— |
10 |
— |
ns |
tWCR |
Write Command Hold Time |
40 |
— |
50 |
— |
ns |
|
(referenced to RAS)(17) |
|
|
|
|
|
tWP |
Write Command Pulse Width(17) |
8 |
— |
10 |
— |
ns |
tWPZ |
WE Pulse Widths to Disable Outputs |
7 |
— |
7 |
— |
ns |
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|
|
|
|
|
|
6 |
|
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
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Rev. D |
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06/24/01 |