ISSI IS41LV16400-60TI, IS41LV16400-60TE, IS41LV16400-50TE, IS41LV16400-50T, IS41LV16400-60T Datasheet

IS41LV16400

ISSI®

4M x 16 (64-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

NOVEMBER 1999

FEATURES

•Extended Data-Out (EDO) Page Mode access cycle

•TTL compatible inputs and outputs; tristate I/O

•Refresh Interval: 4,096 cycles / 64 ms

•Auto refresh Mode: RAS-Only, CAS-before-RAS (CBR), and Hidden

•Low Standby power dissipation:

–1.8mW(max) CMOS Input Level

•Single power supply: 3.3V ± 10%

•Byte Write and Byte Read operation via two CAS

•	Extended Temperature Range	-30oC to 85oC
•	Industrail Temperature Range	-40oC to 85oC

DESCRIPTION

The ISSI IS41LV16400 is 4,194,304 x 16-bit high-perfor- mance CMOS Dynamic Random Access Memories. These devices offer an accelerated cycle access called EDO Page Mode. EDO Page Mode allows 1,024 random accesses within a single row with access cycle time as short as 20 ns per 16-bit word. The Byte Write control, of upper and lower byte, makes the IS41LV16400 ideal for use in 16-bit wide data bus systems.

These features make the S41LV16400 ideally suited for high-bandwidth graphics, digital signal processing, high-performance computing systems, and peripheral applications.

The IS41LV16400 is packaged in a 50-pin TSOP (Type II). JEDEC standard pinout.

	PIN CONFIGURATION																									PIN DESCRIPTIONS
	50-Pin TSOP (Type II)
																										A0-A11	Address Inputs
																										I/O0-15	Data Inputs/Outputs
	VCC											1		50				GND								WE	Write Enable
														49
		I/O0										2						I/O15
		I/O1										3		48				I/O14								OE	Output Enable
		I/O2										4		47				I/O13								RAS	Row Address Strobe
														46
		I/O3										5						I/O12
	VCC											6		45				GND								UCAS	Upper Column Address Strobe
		I/O4										7		44				I/O11								LCAS	Lower Column Address Strobe
														43
		I/O5										8						I/O10
		I/O6										9		42				I/O9								Vcc	Power
		I/O7										10		41				I/O8
																										GND	Ground
														40
		NC										11						NC
	VCC										12			39				GND								NC	No Connection
														38
			W									13							LCAS
														37
		RAS										14								UCAS
		NC										15		36
																					OE					KEY TIMING PARAMETERS
		NC										16		35				NC
		NC												34				NC
												17
																										Parameter		-50	-60	Unit
		NC										18		33				NC
		A0										19		32				A11
																										Max. RAS Access Time (tRAC)		50	60	ns
														31
		A1							20									A10
		A2										21		30				A9								Max. CAS Access Time (tCAC)		13	15	ns
		A3										22		29				A8
																										Max. Column Address Access Time (tAA)		25	30	ns
														28
		A4										23						A7
		A5								24				27				A6								Min. EDO Page Mode Cycle Time (tPC)		20	25	ns
	VCC												25	26				GND
																										Min. Read/Write Cycle Time (tRC)		84	104	ns

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.

Integrated Silicon Solution, Inc. — 1-800-379-4774

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Rev. A

11/18/99

IS41LV16400

ISSI®

FUNCTIONAL BLOCK DIAGRAM

OE
WE
LCAS	CAS			WE			OE
	CLOCK			CONTROL			CONTROL
		CAS				WE
UCAS	GENERATOR			LOGICS			LOGIC
								OE
RAS	RAS	RAS			DATA I/O BUS
	CLOCK
	GENERATOR			COLUMN DECODERS
	REFRESH			SENSE AMPLIFIERS			I/O BUFFERS
	COUNTER							I/O0-I/O15
			DECODER	MEMORY ARRAY			DATA
	ADDRESS				4,194,304 x 16
A0-A11	BUFFERS		ROW

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Rev. A

11/18/99

IS41LV16400

ISSI®

TRUTH TABLE

Function

RAS

LCAS

UCAS

WE

OE

Address tR/tC

I/O

Standby

H

H

H

X

X

X

High-Z

Read: Word

L

L

L

H

L

ROW/COL

DOUT

Read: Lower Byte

L

L

H

H

L

ROW/COL

Lower Byte, DOUT

Upper Byte, High-Z

Read: Upper Byte

L

H

L

H

L

ROW/COL

Lower Byte, High-Z

Upper Byte, DOUT

Write: Word (Early Write)

L

L

L

L

X

ROW/COL

DIN

Write: Lower Byte (Early Write)

L

L

H

L

X

ROW/COL

Lower Byte, DIN

Upper Byte, High-Z

Write: Upper Byte (Early Write)

L

H

L

L

X

ROW/COL

Lower Byte, High-Z

Upper Byte, DIN

Read-Write(1,2)

L

L

L

H→

L

L→

H

ROW/COL

DOUT, DIN

EDO Page-Mode Read(2)

1st Cycle:

L

H→

L

H→

L

H

L

ROW/COL

DOUT

2nd Cycle:

L

H→

L

H→

L

H

L

NA/COL

DOUT

Any Cycle:

L

L→

H

L→

H

H

L

NA/COL

DOUT

EDO Page-Mode Write(1)

1st Cycle:

L

H→

L

H→

L

L

X

ROW/COL

DIN

2nd Cycle:

L

H→

L

H→

L

L

X

NA/COL

DIN

EDO Page-Mode(1,2)

1st Cycle:

L

H→

L

H→

L

H→

L

L→

H

ROW/COL

DOUT, DIN

Read-Write

2nd Cycle:

L

H→

L

H→

L

H→

L

L→

H

NA/COL

DOUT, DIN

Hidden Refresh

Read(2)

L→ H→ L

L

L

H

L

ROW/COL

DOUT

Write(1,3)

L→ H→ L

L

L

L

X

ROW/COL

DOUT

RAS-Only Refresh

L

H

H

X

X

ROW/NA

High-Z

CBR Refresh(4)

H→ L

L

L

X

X

X

High-Z

Notes:

1.These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).

2.These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).

3.EARLY WRITE only.

4.At least one of the two CAS signals must be active (LCAS or UCAS).

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Rev. A

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IS41LV16400

ISSI®

FUNCTIONAL DESCRIPTION

The IS41LV16400 is a CMOS DRAM optimized for high-speed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 22 address bits: 12 row address bits (A0~A11) and 10 column address bits (A0~A9). The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first twelve bits and CAS is used the latter ten bits.

The IS41LV16400 has two CAS controls, LCAS and UCAS. The LCAS and UCAS inputs internally generates

a CAS signal functioning in an identical manner to the single CAS input on the other 4M x 16 DRAMs. The key difference is that each CAS controls its corresponding I/O tristate logic (in conjunction with OE and WE and RAS). LCAS controls I/O0 through I/O7 and UCAS controls I/O8 through I/O15.

The IS41LV16400 CAS function is determined by the first CAS (LCAS or UCAS) transitioning LOW and the last

transitioning back HIGH. The two CAS controls give the IS41LV16400 both BYTE READ and BYTE WRITE cycle capabilities.

Memory Cycle

A memory cycle is initiated by bring RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP, tCP has elapsed.

Read Cycle

A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA, tCAC and tOEA are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters.

Write Cycle

A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs last.

Refresh Cycle

To retain data, 4,096 refresh cycles are required in each 64 ms period. There are two ways to refresh the memory.

1.By clocking each of the 4,096 row addresses (A0 through A11) with RAS at least once every 64 ms. Any read, write, read-modify-write or RAS-only cycle refreshes the addressed row.

2.Using a CAS-before-RAS refresh cycle. CAS-before-RAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 12-bit counter provides the row addresses and the external address inputs are ignored.

CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle.

Extended Data Out Page Mode

EDO page mode operation permits all 1,024 columns within a selected row to be randomly accessed at a high data rate.

In EDO page mode read cycle, the data-out is held to the next CAS cycle’s falling edge, instead of the rising edge. For this reason, the valid data output time in EDO page mode is extended compared with the fast page mode. In the fast page mode, the valid data output time becomes shorter as the CAS cycle time becomes shorter. Therefore, in EDO page mode, the timing margin in read cycle is larger than that of the fast page mode even if the CAS cycle time becomes shorter.

In EDO page mode, due to the extended data function, the CAS cycle time can be shorter than in the fast page mode if the timing margin is the same.

The EDO page mode allows both read and write operations during one RAS cycle, but the performance is equivalent to that of the fast page mode in that case.

Power-On

After application of the VCC supply, an initial pause of 200 µs is required followed by a minimum of eight

initialization cycles (any combination of cycles containing a RAS signal).

During power-on, it is recommended that RAS track with VCC or be held at a valid VIH to avoid current surges.

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Rev. A

11/18/99

IS41LV16400				ISSI®
ABSOLUTE MAXIMUM RATINGS(1)
Symbol	Parameters	Rating	Unit
VT	Voltage on Any Pin Relative to GND	–0.5 to +4.6	V
VCC	Supply Voltage	–0.5 to +4.6	V
IOUT	Output Current	50	mA
PD	Power Dissipation	1	W
TA	Commercial Operation Temperature	0 to +70	°C
	Extended Temperature	–30 to +85	°C
	Industrail Temperature	–40 to +85	°C
TSTG	Storage Temperature	–55 to +125	°C

Note:

1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)

Symbol	Parameter	Min.	Typ.	Max.	Unit
VCC	Supply Voltage	3.0	3.3	3.6V	V
VIH	Input High Voltage	2.0	—	VCC + 0.3	V
VIL	Input Low Voltage	–0.3	—	0.8	V
TA	Commercial Ambient Temperature	0	—	70	°C
	Extended Ambient Temperature	–30	—	85	°C
	Industrail Ambient Temperature	–40	—	85	°C

CAPACITANCE(1,2)

Symbol	Parameter	Max.	Unit
CIN1	Input Capacitance: A0-A11	5	pF
CIN2	Input Capacitance: RAS, UCAS, LCAS, WE, OE	7	pF
CIO	Data Input/Output Capacitance: I/O0-I/O15	7	pF

Notes:

1.Tested initially and after any design or process changes that may affect these parameters.

2.Test conditions: TA = 25°C, f = 1 MHz.

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Rev. A

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IS41LV16400

ISSI®

ELECTRICAL CHARACTERISTICS(1)

(Recommended Operating Conditions unless otherwise noted.)

Symbol	Parameter	Test Condition		Speed	Min.	Max.	Unit
IIL	Input Leakage Current	Any input 0V ≤ VIN ≤	Vcc		–5	5	µA
		Other inputs not under test = 0V
IIO	Output Leakage Current	Output is disabled (Hi-Z)			–5	5	µA
		0V ≤ VOUT ≤ Vcc
VOH	Output High Voltage Level	IOH = –2.0 mA			2.4	—	V
VOL	Output Low Voltage Level	IOL = 2.0 mA			—	0.4	V
ICC1	Standby Current: TTL	RAS, LCAS, UCAS ≥	VIH Commerical		—	1	mA
			Extended		—	2	mA
			Industrial		—	2	mA
ICC2	Standby Current: CMOS	RAS, LCAS, UCAS ≥	VCC – 0.2V		—	0.5	mA
ICC3	Operating Current:	RAS, LCAS, UCAS,		-50	—	160	mA
	Random Read/Write(2,3,4)	Address Cycling, tRC = tRC (min.)		-60	—	145
	Average Power Supply Current
ICC4	Operating Current:	RAS = VIL, LCAS, UCAS,		-50	—	90	mA
	EDO Page Mode(2,3,4)	Cycling tPC = tPC (min.)		-60	—	80
	Average Power Supply Current
ICC5	Refresh Current:	RAS Cycling, LCAS, UCAS ≥ VIH		-50	—	160	mA
	RAS-Only(2,3)	tRC = tRC (min.)		-60	—	145
	Average Power Supply Current
ICC6	Refresh Current:	RAS, LCAS, UCAS Cycling		-50	—	160	mA
	CBR(2,3,5)	tRC = tRC (min.)		-60	—	145
	Average Power Supply Current

Notes:

1.An initial pause of 200 µs is required after power-up followed by eight RASrefresh cycles (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.

2.Dependent on cycle rates.

3.Specified values are obtained with minimum cycle time and the output open.

4.Column-address is changed once each EDO page cycle.

5.Enables on-chip refresh and address counters.

AC TEST CONDITIONS

Output load: One TTL Load and 50 pF

Input timing reference levels: VIH = 2.0V, VIL = 0.8V Output timing reference levels: VOH = 2.0V, VOL = 0.8V

319 Ω

3.3V

OUTPUT

50 pF

353 Ω

Including

jig and

scope

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Rev. A

11/18/99