IS41C16257 |
ISSI |
® |
IS41LV16257 |
|
256K x 16 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE
MAY 1999
FEATURES |
DESCRIPTION |
•Fast access and cycle time
•TTL compatible inputs and outputs
•Refresh Interval: 512 cycles/8 ms
•Refresh Mode: RAS-Only, CAS-before-RAS (CBR), and Hidden
•JEDEC standard pinout
•Single power supply:
--5V ± 10% (IS41C16257)
--3.3V ± 10% (IS41LV16257)
•Byte Write and Byte Read operation via two CAS
•Industrial temperature available
The ISSI IS41C16257 and the IS41LV16257 are 262,144 x 16-bit high-performance CMOS Dynamic Random Access Memories. Fast Page Mode allows 512 random accesses within a single row with access cycle time as short as 12 ns per 16-bit word. The Byte Write control, of upper and lower byte, makes these devices ideal for use in 16and 32-bit wide data bus systems.
These features make the IS41C16257 and the IS41LV16257 ideally suited for high band-width graphics, digital signal processing, high-performance computing systems, and peripheral applications.
The IS41C16257 and the IS41LV16257 are packaged in a 40-pin, 400-mil SOJ and TSOP (Type II).
KEY TIMING PARAMETERS
Parameter |
-35 |
-60 |
Unit |
Max. RAS Access Time (tRAC) |
35 |
60 |
ns |
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Max. CAS Access Time (tCAC) |
10 |
15 |
ns |
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Max. Column Address Access Time (tAA) |
18 |
30 |
ns |
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Min. Fast Page Mode Cycle Time (tPC) |
12 |
25 |
ns |
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Min. Read/Write Cycle Time (tRC) |
60 |
110 |
ns |
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ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
1 |
DR004-1B 05/24/99
IS41C16257 |
ISSI |
® |
IS41LV16257 |
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FUNCTIONAL BLOCK DIAGRAM
OE |
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WE |
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LCAS |
CAS |
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WE |
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OE |
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CLOCK |
CAS |
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CONTROL |
CONTROL |
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UCAS |
GENERATOR |
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LOGICS |
WE |
LOGIC |
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OE |
RAS |
RAS |
RAS |
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DATA I/O BUS |
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CLOCK |
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GENERATOR |
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COLUMN DECODERS |
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REFRESH |
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SENSE AMPLIFIERS |
I/O BUFFERS |
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COUNTER |
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I/O0-I/O15 |
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DECODER |
MEMORY ARRAY |
DATA |
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262,144 x 16 |
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ADDRESS |
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ROW |
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A0-A8 |
BUFFERS |
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PIN CONFIGURATIONS
40-Pin TSOP (Type II) |
40-Pin SOJ |
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40 |
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VCC |
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1 |
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GND |
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I/O0 |
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39 |
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I/O15 |
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2 |
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I/O1 |
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38 |
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I/O14 |
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3 |
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I/O2 |
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37 |
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I/O13 |
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4 |
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I/O3 |
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36 |
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I/O12 |
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5 |
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VCC |
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35 |
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GND |
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6 |
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I/O4 |
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34 |
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I/O11 |
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7 |
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I/O5 |
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8 |
33 |
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I/O10 |
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I/O6 |
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32 |
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I/O9 |
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9 |
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I/O7 |
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31 |
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I/O8 |
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10 |
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NC |
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30 |
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NC |
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11 |
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NC |
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12 |
29 |
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LCAS |
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13 |
28 |
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WE |
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UCAS |
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14 |
27 |
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RAS |
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OE |
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NC |
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26 |
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A8 |
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15 |
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A0 |
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16 |
25 |
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A7 |
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A1 |
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17 |
24 |
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A6 |
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A2 |
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18 |
23 |
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A5 |
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A3 |
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19 |
22 |
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A4 |
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VCC |
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20 |
21 |
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GND |
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40 |
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GND |
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VCC |
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1 |
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I/O0 |
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39 |
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I/O15 |
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2 |
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I/O1 |
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38 |
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I/O14 |
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3 |
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I/O2 |
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37 |
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I/O13 |
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4 |
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I/O3 |
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36 |
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I/O12 |
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5 |
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VCC |
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35 |
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GND |
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6 |
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I/O4 |
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34 |
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I/O11 |
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7 |
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I/O5 |
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8 |
33 |
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I/O10 |
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I/O6 |
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32 |
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I/O9 |
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9 |
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I/O7 |
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31 |
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I/O8 |
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10 |
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NC |
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30 |
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NC |
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11 |
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NC |
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29 |
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12 |
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LCAS |
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28 |
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WE |
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13 |
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UCAS |
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14 |
27 |
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RAS |
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OE |
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NC |
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26 |
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A8 |
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15 |
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A0 |
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16 |
25 |
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A7 |
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A1 |
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17 |
24 |
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A6 |
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A2 |
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18 |
23 |
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A5 |
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A3 |
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19 |
22 |
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A4 |
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VCC |
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20 |
21 |
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GND |
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PIN DESCRIPTIONS
A0-A8 |
Address Inputs |
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I/O0-I/O15 |
Data Inputs/Outputs |
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WE |
Write Enable |
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OE |
Output Enable |
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RAS |
Row Address Strobe |
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UCAS |
Upper Column Address |
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Strobe |
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LCAS |
Lower Column Address |
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Strobe |
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Vcc |
Power |
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GND |
Ground |
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NC |
No Connection |
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2 |
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
DR004-1B 05/24/99
IS41C16257 |
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ISSI |
® |
|
IS41LV16257 |
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TRUTH TABLE |
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Function |
RAS |
LCAS |
UCAS |
WE |
OE |
Address tR/tC |
I/O |
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Standby |
H |
H |
H |
X |
X |
X |
High-Z |
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Read: Word |
L |
L |
L |
H |
L |
ROW/COL |
DOUT |
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Read: Lower Byte |
L |
L |
H |
H |
L |
ROW/COL |
Lower Byte, DOUT |
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Upper Byte, High-Z |
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Read: Upper Byte |
L |
H |
L |
H |
L |
ROW/COL |
Lower Byte, High-Z |
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Upper Byte, DOUT |
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Write: Word (Early Write) |
L |
L |
L |
L |
X |
ROW/COL |
DIN |
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Write: Lower Byte (Early Write) |
L |
L |
H |
L |
X |
ROW/COL |
Lower Byte, DIN |
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Upper Byte, High-Z |
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Write: Upper Byte (Early Write) |
L |
H |
L |
L |
X |
ROW/COL |
Lower Byte, High-Z |
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Upper Byte, DIN |
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Read-Write(1,2) |
L |
L |
L |
H→L |
L→H |
ROW/COL |
DOUT, DIN |
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Hidden Refresh2) |
Read L→H→L |
L |
L |
H |
L |
ROW/COL |
DOUT |
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Write L→H→L |
L |
L |
L |
X |
ROW/COL |
DOUT |
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RAS-Only Refresh |
L |
H |
H |
X |
X |
ROW/NA |
High-Z |
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CBR Refresh(3) |
H→L |
L |
L |
X |
X |
X |
High-Z |
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Notes:
1.These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2.These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3.At least one of the two CAS signals must be active (LCAS or UCAS).
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
3 |
DR004-1B 05/24/99
IS41C16257 |
ISSI |
® |
IS41LV16257 |
|
FUNCTIONAL DESCRIPTION
The IS41C16257 and the IS41LV16257 are CMOS DRAMs optimized for high-speed bandwidth, low-power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 18 address bits. These are entered nine bits (A0-A8) at a time. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first nine bits and CAS is used to latch the latter nine bits.
The IS41C16257 and the IS41LV16257 has two CAS controls, LCAS and UCAS. The LCAS and UCAS inputs internally generate a CAS signal functioning in an identical manner to the single CAS input on the other 256K x 16 DRAMs. The key difference is that each CAS controls its corresponding I/O tristate logic (in conjunction with OE and WE and RAS). LCAS controls I/O0 - I/O7 and UCAS controls I/O8 - I/O15.
The IS41C16257 and the IS41LV16257 CAS function is determined by the first CAS (LCAS or UCAS) transitioning LOW and the last transitioning back HIGH. The two CAS controls give the IS41C16257 both BYTE READ and BYTE WRITE cycle capabilities.
on the timing relationships between these parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs last.
Refresh Cycle
To retain data, 512 refresh cycles are required in each 8 ms period. There are two ways to refresh the memory:
1.By clocking each of the 512 row addresses (A0 through A8) with RAS at least once every 8 ms. Any read, write, read-modify-write or RAS-only cycle refreshes the addressed row.
2.Using a CAS-before-RAS refresh cycle. CAS-before- RAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 9-bit counter provides the row addresses and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle.
Memory Cycle
A memory cycle is initiated by bringing RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensure proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA, tCAC and tOEA are all satisfied. As a result, the access time is dependent
Power-On
After application of the VCC supply, an initial pause of 200 s is required followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS signal).
During power-on, it is recommended that RAStrack with VCC or be held at a valid VIH to avoid current surges.
4 |
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
DR004-1B 05/24/99
IS41C16257 |
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ISSI |
® |
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IS41LV16257 |
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ABSOLUTE MAXIMUM RATINGS(1) |
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Symbol |
Parameters |
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Rating |
Unit |
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VT |
Voltage on Any Pin Relative to GND |
5V |
–1.0 to |
+7.0 |
V |
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3.3V |
–0.5 t0 |
+4.6 |
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VCC |
Supply Voltage |
5V |
–1.0 to |
+7.0 |
V |
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3.3V |
–0.5 t0 |
+4.6 |
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IOUT |
Output Current |
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50 |
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mA |
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PD |
Power Dissipation |
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1 |
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W |
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TA |
Operation Temperature |
Com. |
0 to 70 |
°C |
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Ind. |
–40 to |
+85 |
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TSTG |
Storage Temperature |
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–55 to +125 |
°C |
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Note:
1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND)
Symbol |
Parameter |
Voltage |
Min. |
Typ. |
Max. |
Unit |
VCC |
Supply Voltage |
5V |
4.5 |
5.0 |
5.5 |
V |
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VCC |
Supply Voltage |
3.3V |
3.0 |
3.3 |
3.6 |
V |
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VIH |
Input High Voltage |
5V |
2.4 |
— |
VCC + 1.0 |
V |
VIH |
Input High Voltage |
3.3V |
2.0 |
— |
VCC + 0.3 |
V |
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VIL |
Input Low Voltage |
5V |
–1.0 |
— |
0.8 |
V |
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VIL |
Input Low Voltage |
3.3 |
–0.3 |
— |
0.8 |
V |
TA |
Ambient Temperature |
Com. |
0 |
— |
70 |
°C |
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Ind. |
–40 |
— |
85 |
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CAPACITANCE(1,2)
Symbol |
Parameter |
Max. |
Unit |
CIN1 |
Input Capacitance: A0-A8 |
5 |
pF |
CIN2 |
Input Capacitance: RAS, UCAS, LCAS, WE, OE |
7 |
pF |
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CIO |
Data Input/Output Capacitance: I/O0-I/O15 |
7 |
pF |
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Notes:
1.Tested initially and after any design or process changes that may affect these parameters.
2.Test conditions: TA = 25°C, f = 1 MHz, VCC = 5.0V + 10% or Vcc=3.3V ± 10%.
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
5 |
DR004-1B 05/24/99
IS41C16257 |
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ISSI |
® |
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IS41LV16257 |
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ELECTRICAL CHARACTERISTICS(1) (Recommended Operation Conditions unless otherwise noted.) |
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Symbol |
Parameter |
Test Condition |
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Speed |
Min. |
Max. |
Unit |
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IIL |
Input Leakage Current |
Any input 0V < VIN < Vcc |
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–10 |
10 |
A |
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Other inputs not under test = 0V |
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IIO |
Output Leakage Current |
Output is disabled (Hi-Z) |
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–10 |
10 |
A |
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0V < VOUT < Vcc |
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VOH |
Output High Voltage Level |
IOH = –2.5 mA |
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2.4 |
— |
V |
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VOL |
Output Low Voltage Level |
IOL = 2.1 mA |
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— |
0.4 |
V |
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ICC1 |
Stand-by Current: TTL |
RAS, LCAS, UCAS ≥ VIH |
Com. |
5V |
— |
2 |
mA |
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Ind. |
5V |
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3 |
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ICC1 |
Stand-by Current: TTL |
RAS, LCAS, UCAS ≥ VIH |
Com. |
3.3V |
— |
1 |
mA |
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Ind. |
3.3V |
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2 |
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ICC2 |
Stand-by Current: CMOS |
RAS, LCAS, UCAS ≥ VCC – 0.2V |
|
5V |
— |
2 |
mA |
|
|
ICC2 |
Stand-by Current: CMOS |
RAS, LCAS, UCAS ≥ VCC – 0.2V |
|
3.3V |
— |
1 |
mA |
|
|
ICC3 |
Operating Current: |
RAS, LCAS, UCAS, |
|
-35 |
— |
230 |
mA |
|
|
|
Random Read/Write(2,3,4) |
Address Cycling, tRC = tRC (min.) |
|
-60 |
— |
170 |
|
|
|
|
Average Power Supply Current |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ICC4 |
Operating Current: |
RAS = VIL, LCAS, UCAS, |
|
-35 |
— |
220 |
mA |
|
|
|
Fast Page Mode(2,3,4) |
Cycling tPC = tPC (min.) |
|
-60 |
— |
160 |
|
|
|
|
Average Power Supply Current |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ICC5 |
Refresh Current: |
RAS Cycling, LCAS, UCAS ≥ VIH |
|
-35 |
— |
230 |
mA |
|
|
|
RAS-Only(2,3) |
tRC = tRC (min.) |
|
-60 |
— |
170 |
|
|
|
|
Average Power Supply Current |
|
|
|
|
|
|
|
|
ICC6 |
Refresh Current: |
RAS, LCAS, UCAS Cycling |
|
-35 |
— |
230 |
mA |
|
|
|
CBR(2,3,5) |
tRC = tRC (min.) |
|
-60 |
— |
170 |
|
|
|
|
Average Power Supply Current |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Notes:
1.An initial pause of 200 s is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured.The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2.Dependent on cycle rates.
3.Specified values are obtained with minimum cycle time and the output open.
4.Column-address is changed once each fast page cycle.
5.Enables on-chip refresh and address counters.
6 |
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
DR004-1B 05/24/99