ISSI IS41LV16256-60TI, IS41LV16256-60T, IS41LV16256-60KI, IS41LV16256-35T, IS41LV16256-35K Datasheet

...
0 (0)
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. J
06/29/00
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
IS41C16256
IS41LV16256 ISSI
FEATURES
TTL compatible inputs and outputs
Refresh Interval: 512 cycles/8 ms
Refresh Mode : RAS-Only, CAS-before-RAS
(CBR), and Hidden
JEDEC standard pinout
Single power supply
5V ± 10% (IS41C16256)
3.3V ± 10% (IS41LV16256)
Byte Write and Byte Read operation via two CAS
Extended Temperature Range -30
o
C to 85
o
C
Industrail Temperature Range -40
o
C to 85
o
C
DESCRIPTION
The
ISSI
IS41C16256 and IS41LV16256 are 262,144 x 16-bit
high-performance CMOS Dynamic Random Access Memory. Both
products offer accelerated cycle access EDO Page Mode. EDO
Page Mode allows 512 random accesses within a single row with
access cycle time as short as 10ns per 16-bit word. The Byte Write
control, of upper and lower byte, makes the IS41C16256 and
IS41LV16256 ideal for use in 16 and 32-bit wide data bus systems.
These features make the IS41C16256 and IS41LV1626 ideally
suited for high
band-width
graphics,
digital signal processing,
high-performance computing systems, and peripheral applications.
The IS41C16256 and IS41LV16256 are packaged in 40-pin
400-mil SOJ and TSOP (Type II).
256K x 16 (4-MBIT) DYNAMIC RAM JUNE 2000
WITH EDO PAGE MODE
KEY TIMING PARAMETERS
Parameter -35 -50 -60 Unit
Max. RAS Access Time (tRAC) 355060ns
Max. CAS Access Time (tCAC) 101415ns
Max. Column Address Access Time (tAA)182530ns
Min. EDO Page Mode Cycle Time (tPC)122025ns
Min. Read/Write Cycle Time (tRC) 60 90 110 ns
PIN CONFIGURATIONS
40-Pin TSOP (Type II) 40-Pin SOJ
PIN DESCRIPTIONS
A0-A8 Address Inputs
I/O0-15
Data Inputs/Outputs
WE Write Enable
OE Output Enable
RAS Row Address Strobe
UCAS
Upper Column Address Strobe
LCAS
Lower Column Address Strobe
Vcc Power
GND Ground
NC No Connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
GND
2
Integrated Silicon Solution, Inc. 1-800-379-4774
Rev. J
06/29/00
IS41C16256
IS41LV16256 ISSI
®
FUNCTIONAL BLOCK DIAGRAM
OE
WE
LCAS
UCAS
CAS WE
OE
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
MEMORY ARRAY
262,144 x 16
ROW DECODER
DATA I/O BUFFERS
CAS
CLOCK
GENERATOR
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
I/O0-I/O15
RAS
RAS
A0-A8
RAS
CLOCK
GENERATOR
REFRESH
COUNTER
ADDRESS
BUFFERS
Integrated Silicon Solution, Inc. 1-800-379-4774
3
Rev. J
06/29/00
IS41C16256
IS41LV16256 ISSI
®
TRUTH TABLE
Function RAS LCAS UCAS WE OE Address tR/tC I/O
Standby H H H X X X High-Z
Read: Word L L L H L ROW/COL DOUT
Read: Lower Byte L L H H L ROW/COL Lower Byte, DOUT
Upper Byte, High-Z
Read: Upper Byte L H L H L ROW/COL Lower Byte, High-Z
Upper Byte, DOUT
Write: Word (Early Write) L L L L X ROW/COL DIN
Write: Lower Byte (Early Write) L L H L X ROW/COL Lower Byte, DIN
Upper Byte, High-Z
Write: Upper Byte (Early Write) L H L L X ROW/COL Lower Byte, High-Z
Upper Byte, DIN
Read-Write
(1,2)
LLLHLLH ROW/COL DOUT, DIN
EDO Page-Mode Read
(2)
1st Cycle: L H LHL H L ROW/COL DOUT
2nd Cycle: L HLHL H L NA/COL DOUT
Any Cycle: L L HL H H L NA/NA DOUT
EDO Page-Mode Write
(1)
1st Cycle: L H LHL L X ROW/COL DIN
2nd Cycle: L HLHL L X NA/COL DIN
EDO Page-Mode 1st Cycle: L HLHLHLL H ROW/COL DOUT, DIN
Read-Write
(1,2)
2nd Cycle: L HLHLH LLH NA/COL DOUT, DIN
Hidden Refresh
2)
Read LH L L L H L ROW/COL DOUT
Write LHL L L L X ROW/COL DOUT
RAS-Only Refresh L H H X X ROW/NA High-Z
CBR Refresh
(3)
H L L L X X X High-Z
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. At least one of the two CAS signals must be active (LCAS or UCAS).
4
Integrated Silicon Solution, Inc. 1-800-379-4774
Rev. J
06/29/00
IS41C16256
IS41LV16256 ISSI
®
Functional Description
The IS41C16256 and IS41LV16256 is a CMOS DRAM
optimized for high-speed bandwidth, low power applica-
tions. During READ or WRITE cycles, each bit is uniquely
addressed through the 18 address bits. These are en-
tered nine bits (A0-A8) at a time. The row address is
latched by the Row Address Strobe (RAS). The column
address is latched by the Column Address Strobe (CAS).
RAS is used to latch the first nine bits and CAS is used the
latter nine bits.
The IS41C16256 and IS41LV16256 has two CAS con-
trols, LCAS and UCAS. The LCAS and UCAS inputs
internally generates a CAS signal functioning in an iden-
tical manner to the single CAS input on the other 256K x
16 DRAMs. The key difference is that each CAS controls
its corresponding I/O tristate logic (in conjunction with OE
and WE and RAS). LCAS controls I/O0 through I/O7 and
UCAS controls I/O8 through I/O15.
The IS41C16256 and IS41LV16256 CAS function is
determined by the first CAS ( LCAS or UCAS) transitioning
LOW and the last transitioning back HIGH. The two CAS
controls give the IS41C16256 both BYTE READ and
BYTE WRITE cycle capabilities.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time speci-
fied by tAR. Data Out becomes valid only when tRAC, tAA,
tCAC and tOEA are all satisfied. As a result, the access time
is dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid
at or before the falling edge of CAS or WE, whichever
occurs last.
Refresh Cycle
To retain data, 512 refresh cycles are required in each
8 ms period. There are two ways to refresh the memory.
1. By clocking each of the 512 row addresses (A0 through
A8) with RAS at least once every 8 ms. Any read, write,
read-modify-write or RAS-only cycle refreshes the ad-
dressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Extended Data Out Page Mode
EDO page mode operation permits all 512 columns within
a selected row to be randomly accessed at a high data
rate.
In EDO page mode read cycle, the data-out is held to the
next CAS cycles falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CAS cycle time becomes shorter. There-
fore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the CAS
cycle time becomes shorter.
In EDO page mode, due to the extended data function, the
CAS cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write opera-
tions during one RAS cycle, but the performance is
equivalent to that of the fast page mode in that case.
Power-On
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS signal).
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
Integrated Silicon Solution, Inc. 1-800-379-4774
5
Rev. J
06/29/00
IS41C16256
IS41LV16256 ISSI
®
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameters Rating Unit
VT Voltage on Any Pin Relative to GND 5V 1.0 to +7.0 V
3.3V -0.5 to 4.6 V
V
CC Supply Voltage 5V 1.0 to +7.0 V
3.3V -0.5 to 4.6 V
IOUT Output Current 50 mA
PD Power Dissipation 1 W
T
A Commercial Operation Temperature 0 to +70 °C
Extended Temperature 30 to +85 °C
Industrail Temperature 40 to +85 °C
TSTG Storage Temperature 55 to +125 °C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
CAPACITANCE
(1,2)
Symbol Parameter Max. Unit
CIN1 Input Capacitance: A0-A8 5 pF
CIN2 Input Capacitance: RAS, UCAS, LCAS, WE, OE 7pF
CIO Data Input/Output Capacitance: I/O0-I/O15 7 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A = 25°C, f = 1 MHz,
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 5V 4.5 5.0 5.5 V
3.3V 3.0 3.3 3.6
VIH Input High Voltage 5V 2.4 VCC + 1.0 V
3.3V 2.0 VCC + 0.3
VIL Input Low Voltage 5V 1.0 0.8 V
3.3V 0.3 0.8
TA Commercial Ambient Temperature 0 70 °C
Extended Ambient Temperature 30 85 °C
Industrail Ambient Temperature 40 85 °C
6
Integrated Silicon Solution, Inc. 1-800-379-4774
Rev. J
06/29/00
IS41C16256
IS41LV16256 ISSI
®
ELECTRICAL CHARACTERISTICS
(1)
(Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter Test Condition Speed Min. Max. Unit
I
IL Input Leakage Current Any input 0V VIN Vcc 10 10 µA
Other inputs not under test = 0V
I
IO Output Leakage Current Output is disabled (Hi-Z) 10 10 µA
0V VOUT Vcc
VOH Output High Voltage Level IOH = 2.5 mA 2.4 V
VOL Output Low Voltage Level IOL = +2.1 mA 0.4 V
I
CC1 Stand-by Current: TTL RAS, LCAS, UCAS VIH Commercial 5V 3mA
Industrial 5V 4
Commercial 3V 2
Industrial 3V 3
ICC2 Stand-by Current: CMOS RAS, LCAS, UCAS VCC 0.2V 5V 2mA
3V 1
ICC3 Operating Current: RAS, LCAS, UCAS, -35 230 mA
Random Read/Write
(2,3,4)
Address Cycling, tRC = tRC (min.) -50 180
Average Power Supply Current
-60 170
ICC4 Operating Current: RAS = VIL, LCAS, UCAS, -35 220 mA
EDO Page Mode
(2,3,4)
Cycling tPC = tPC (min.) -50 170
Average Power Supply Current
-60 160
ICC5 Refresh Current: RAS Cycling, LCAS, UCAS VIH -35 230 mA
RAS-Only
(2,3)
tRC = tRC (min.) -50 180
Average Power Supply Current
-60 170
ICC6 Refresh Current: RAS, LCAS, UCAS Cycling -35 230 mA
CBR
(2,3,5)
tRC = tRC (min.) -50 180
Average Power Supply Current -60 170
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the t
REF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
Loading...
+ 13 hidden pages