ISSI IS41LV16100-60TI, IS41LV16100-60TE, IS41LV16100-60T, IS41LV16100-60K, IS41LV16100-50TI Datasheet

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IS41C16100

®

IS41LV16100

ISSI

1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

FEBRUARY 2000

FEATURES

TTL compatible inputs and outputs; tristate I/O

Refresh Interval:

Auto refresh Mode: 1,024 cycles /16 ms

RAS-Only, CAS-before-RAS (CBR), and Hidden

Self refresh Mode - 1,024 cycles / 128ms

JEDEC standard pinout

Single power supply:

5V ± 10% (IS41C16100)

3.3V ± 10% (IS41LV16100)

Byte Write and Byte Read operation via two CAS

• Extended Temperature Range -30oC to 85oC

• Industrail Temperature Range -40oC to 85oC

PIN CONFIGURATIONS

50(44)-Pin TSOP (Type II)

42-Pin SOJ

 

 

 

 

 

 

 

44

 

 

 

 

 

 

 

VCC

 

 

1

 

 

GND

 

I/O0

 

43

 

 

I/O15

 

 

 

2

 

 

 

I/O1

 

42

 

 

I/O14

 

 

 

3

 

 

 

I/O2

 

41

 

 

I/O13

 

 

 

4

 

 

 

I/O3

 

40

 

 

I/O12

 

 

 

5

 

 

VCC

 

39

 

 

GND

 

 

6

 

 

 

I/O4

 

38

 

 

I/O11

 

 

 

7

 

 

 

I/O5

 

 

8

37

 

 

I/O10

 

 

 

 

 

 

I/O6

 

36

 

 

I/O9

 

 

 

9

 

 

 

I/O7

 

35

 

 

I/O8

 

 

 

10

 

 

 

 

NC

 

34

 

 

NC

 

 

 

 

11

 

 

 

 

NC

 

 

12

33

 

 

NC

 

 

 

 

 

 

NC

 

 

13

32

 

 

 

 

 

 

 

 

 

 

 

LCAS

 

 

 

 

14

31

 

 

 

 

 

 

 

 

 

WE

 

 

 

 

 

 

UCAS

 

 

 

 

15

30

 

 

 

 

 

 

 

 

RAS

 

 

 

 

 

 

 

OE

 

 

 

 

NC

 

 

16

29

 

 

A9

 

 

 

 

 

 

NC

 

 

17

28

 

 

A8

 

 

 

 

 

 

A0

 

 

18

27

 

 

A7

 

 

 

 

 

 

A1

 

 

19

26

 

 

A6

 

 

 

 

 

 

A2

 

 

20

25

 

 

A5

 

 

 

 

 

 

A3

 

 

21

24

 

 

A4

 

 

 

 

VCC

 

 

22

23

 

 

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

42

 

GND

VCC

 

1

 

I/O0

 

41

 

I/O15

 

2

 

I/O1

 

40

 

I/O14

 

3

 

I/O2

 

39

 

I/O13

 

4

 

I/O3

 

38

 

I/O12

 

5

 

VCC

 

37

 

GND

 

6

 

I/O4

 

36

 

I/O11

 

7

 

I/O5

 

8

35

 

I/O10

 

 

I/O6

 

34

 

I/O9

 

9

 

I/O7

 

33

 

I/O8

 

10

 

 

 

NC

 

32

 

NC

 

 

 

11

 

 

 

NC

 

31

 

 

 

 

 

 

 

 

 

12

 

 

LCAS

 

 

 

 

 

 

30

 

 

 

 

 

 

 

 

WE

 

 

13

 

 

UCAS

 

 

 

 

 

 

29

 

 

 

 

 

 

 

RAS

 

 

14

 

OE

 

 

 

 

NC

 

28

 

A9

 

 

 

15

 

 

 

NC

 

16

27

 

A8

 

 

 

 

 

 

A0

 

17

26

 

A7

 

 

 

 

 

 

A1

 

18

25

 

A6

 

 

 

 

 

 

A2

 

19

24

 

A5

 

 

 

 

 

 

A3

 

20

23

 

A4

 

 

 

 

VCC

 

21

22

 

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DESCRIPTION

The ISSI IS41C16100 and IS41LV16100 are 1,048,576 x 16-bit high-performance CMOS Dynamic Random Access Memories. ThesedevicesofferanacceleratedcycleaccesscalledEDOPage Mode. EDO Page Mode allows 1,024 random accesses within a singlerowwithaccesscycletimeasshortas20nsper16-bitword. The Byte Write control, of upper and lower byte, makes the IS41C16100idealforusein16-bitand32-bitwidedatabussystems.

These features make the IS41C16100and IS41LV16100 ideally suited for high-bandwidth graphics, digital signal processing, high-performancecomputingsystems,andperipheralapplications.

The IS41C16100 and IS41LV16100 are packaged in a 42-pin 400-mil SOJ and 400-mil 50- (44-) pin TSOP (Type II).

KEY TIMING PARAMETERS

Parameter

-50

-60

Unit

Max. RAS Access Time (tRAC)

50

60

ns

 

 

 

 

Max. CAS Access Time (tCAC)

13

15

ns

 

 

 

 

Max. Column Address Access Time (tAA)

25

30

ns

 

 

 

 

Min. EDO Page Mode Cycle Time (tPC)

20

25

ns

 

 

 

 

Min. Read/Write Cycle Time (tRC)

84

104

ns

 

 

 

 

PIN DESCRIPTIONS

A0-A9

Address Inputs

 

 

I/O0-15

Data Inputs/Outputs

 

 

WE

Write Enable

 

 

OE

Output Enable

 

 

RAS

Row Address Strobe

 

 

UCAS

Upper Column Address Strobe

 

 

LCAS

Lower Column Address Strobe

 

 

Vcc

Power

 

 

GND

Ground

 

 

NC

No Connection

 

 

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.

Integrated Silicon Solution, Inc. — 1-800-379-4774

1

Rev. F

03/08/00

ISSI IS41LV16100-60TI, IS41LV16100-60TE, IS41LV16100-60T, IS41LV16100-60K, IS41LV16100-50TI Datasheet

IS41C16100

ISSI

®

IS41LV16100

 

FUNCTIONAL BLOCK DIAGRAM

OE

 

 

 

 

 

 

 

WE

 

 

 

 

 

 

 

LCAS

CAS

 

 

WE

 

OE

 

 

CLOCK

CAS

 

CONTROL

CONTROL

 

UCAS

GENERATOR

 

LOGICS

WE

LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

OE

RAS

RAS

RAS

 

 

DATA I/O BUS

 

 

 

 

 

 

 

CLOCK

 

 

 

 

 

 

 

 

 

 

 

 

GENERATOR

 

 

 

 

 

 

 

 

COLUMN DECODERS

 

 

 

 

 

 

 

 

 

REFRESH

 

 

SENSE AMPLIFIERS

I/O BUFFERS

 

 

 

 

 

 

 

 

COUNTER

 

 

 

 

I/O0-I/O15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DECODER

MEMORY ARRAY

DATA

 

 

 

 

 

1,048,576 x 16

 

 

ADDRESS

 

 

 

 

 

 

ROW

 

 

 

 

A0-A9

BUFFERS

 

 

 

 

 

 

 

 

 

 

 

2

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. F

03/08/00

IS41C16100

 

 

 

 

 

 

 

ISSI

®

IS41LV16100

 

 

 

 

 

 

 

 

 

TRUTH TABLE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Function

 

RAS

LCAS

UCAS

WE

OE

Address tR/tC

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

Standby

 

H

H

H

X

X

X

High-Z

 

 

 

 

 

 

 

 

 

 

 

 

 

Read:Word

 

L

L

L

H

L

ROW/COL

DOUT

 

 

 

 

 

 

 

 

 

 

 

 

 

Read:LowerByte

 

L

L

H

H

L

ROW/COL

Lower Byte, DOUT

 

 

 

 

 

 

 

 

 

 

UpperByte,High-Z

 

 

 

 

 

 

 

 

 

 

 

 

 

Read:UpperByte

 

L

H

L

H

L

ROW/COL

LowerByte,High-Z

 

 

 

 

 

 

 

 

 

 

Upper Byte, DOUT

 

 

 

 

 

 

 

 

 

 

 

 

 

Write:Word(EarlyWrite)

 

L

L

L

L

X

ROW/COL

DIN

 

 

 

 

 

 

 

 

 

 

 

 

Write:LowerByte(EarlyWrite)

L

L

H

L

X

ROW/COL

Lower Byte, DIN

 

 

 

 

 

 

 

 

 

 

UpperByte,High-Z

 

 

 

 

 

 

 

 

 

 

 

 

Write:UpperByte(EarlyWrite)

L

H

L

L

X

ROW/COL

LowerByte,High-Z

 

 

 

 

 

 

 

 

 

 

Upper Byte, DIN

 

 

 

 

 

 

 

 

 

 

 

 

 

Read-Write(1,2)

 

L

L

L

H→L

L→H

ROW/COL

DOUT, DIN

 

 

 

 

 

 

 

 

 

 

 

 

 

EDOPage-ModeRead(2)

1stCycle:

L

H→L

H→L

H

L

ROW/COL

DOUT

 

 

 

2ndCycle:

L

H→L

H→L

H

L

NA/COL

DOUT

 

 

 

AnyCycle:

L

L→H

L→H

H

L

NA/NA

DOUT

 

 

 

 

 

 

 

 

 

 

 

 

 

EDOPage-ModeWrite(1)

1stCycle:

L

H→L

H→L

L

X

ROW/COL

DIN

 

 

 

2ndCycle:

L

H→L

H→L

L

X

NA/COL

DIN

 

 

 

 

 

 

 

 

 

 

 

 

 

EDO Page-Mode(1,2)

1stCycle:

L

H→L

H→L

H→L

L→H

ROW/COL

DOUT, DIN

 

 

Read-Write

2ndCycle:

L

H→L

H→L

H→L

L→H

NA/COL

DOUT, DIN

 

 

 

 

 

 

 

 

 

 

 

 

 

HiddenRefresh

Read(2)

L→H→L

L

L

H

L

ROW/COL

DOUT

 

 

 

Write(1,3)

L→H→L

L

L

L

X

ROW/COL

DOUT

 

 

 

 

 

 

 

 

 

 

 

 

 

RAS-OnlyRefresh

 

L

H

H

X

X

ROW/NA

High-Z

 

 

 

 

 

 

 

 

 

 

 

 

 

CBR Refresh(4)

 

H→L

L

L

X

X

X

High-Z

 

 

Notes:

1.These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).

2.These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).

3.EARLY WRITE only.

4.At least one of the two CAS signals must be active (LCAS or UCAS).

Integrated Silicon Solution, Inc. — 1-800-379-4774

3

Rev. F

03/08/00

IS41C16100

ISSI

®

IS41LV16100

 

Functional Description

The IS41C16100 and IS41LV16100 is a CMOS DRAM optimized for high-speed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 16 address bits. These are entered ten bits (A0-A9) at time. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used tolatchthefirstninebitsandCASisusedtolatchthelatterninebits.

The IS41C16100 and IS41LV16100 has two CAS controls, LCASand UCAS. The LCAS and UCASinputs internally

generates a CASsignal functioning in an identical manner to the single CAS input on the other 1M x 16 DRAMs. The key difference is that each CAS controls its corresponding I/O tristate logic (in conjunction with OE and WE and RAS). LCAS controlsI/O0throughI/O7andUCAScontrolsI/O8through I/O15.

The IS41C16100 and IS41LV16100 CAS function is determined by the first CAS (LCAS or UCAS) transitioning LOW and the last transitioning back HIGH. The two CAS controls give the IS41C16100 and IS41LV16100 both BYTE READ and BYTE WRITE cycle capabilities.

Memory Cycle

A memory cycle is initiated by bring RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP, tCP has elapsed.

Read Cycle

A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA, tCAC and tOEA are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters.

Write Cycle

A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs first.

Auto Refresh Cycle

To retain data, 1,024 refresh cycles are required in each 16 ms period. There are two ways to refresh the memory.

1.By clocking each of the 1,024 row addresses (A0 through A9) with RAS at least once every 128 ms. Any read, write, read- modify-writeorRAS-onlycyclerefreshestheaddressedrow.

2.Using a CAS-before-RAS refresh cycle. CAS-before- RAS refresh is activated by the falling edge of RAS,

while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 9-bit counter provides the row addresses and the external address inputs are ignored.

CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle.

Self Refresh Cycle

The Self Refresh allows the user a dynamic refresh, data retention mode at the extended refresh period of 128 ms. i.e., 125 µs per row when using distributed CBR refreshes. The feature also allows the user the choice of a fully static, low power data retention mode. The optional Self Refresh feature is initiated by performing a CBR Refresh cycle and holding RAS LOW for the specified tRAS.

The Self Refresh mode is terminated by driving RAS HIGH for a minimum time of tRP. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the RAS LOW-to-HIGH transition. If the DRAM controller uses a distributed refresh sequence, a burst refresh is not required upon exiting Self Refresh.

However, if the DRAM controller utilizes a RAS-only or burst refresh sequence, all 1,024 rows must be refreshed within the average internal refresh rate, prior to the resumption of normal operation.

Extended Data Out Page Mode

EDO page mode operation permits all 1,024 columns within a selected row to be randomly accessed at a high data rate.

In EDO page mode read cycle, the data-out is held to the next CAS cycle’s falling edge, instead of the rising edge. For this reason, the valid data output time in EDO page mode is extended compared with the fast page mode. In the fast page mode, the valid data output time becomes shorter as the CAS cycle time becomes shorter. Therefore, in EDO page mode, the timing margin in read cycle is larger than that of the fast page mode even if the CAS cycle time becomes shorter.

In EDO page mode, due to the extended data function, the CAS cycle time can be shorter than in the fast page mode if the timing margin is the same.

The EDO page mode allows both read and write operations during one RAS cycle, but the performance is equivalent to that of the fast page mode in that case.

Power-On

After application of the VCC supply, an initial pause of 200 µs is required followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS signal).

During power-on, it is recommended that RAS track with VCC or be held at a valid VIH to avoid current surges.

4 Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. F

03/08/00

IS41C16100

 

 

 

ISSI

®

IS41LV16100

 

 

 

 

ABSOLUTE MAXIMUM RATINGS(1)

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

Parameters

 

Rating

Unit

 

 

 

 

 

 

 

 

VT

Voltage on Any Pin Relative to GND

5V

–1.0 to +7.0

V

 

 

 

3.3V

–0.5 to +4.6

 

 

 

 

 

 

 

 

 

 

VCC

Supply Voltage

5V

–1.0 to +7.0

V

 

 

 

3.3V

–0.5 to +4.6

 

 

 

 

 

 

 

 

 

 

IOUT

Output Current

 

50

mA

 

 

 

 

 

 

 

 

PD

Power Dissipation

 

1

W

 

 

 

 

 

 

 

 

TA

Commercial Operation Temperature

 

0 to +70

°C

 

 

Extendedl Operation Temperature

 

–30 to +85

°C

 

 

Industrial Operationg Temperature

 

-40 to +85

°C

 

 

 

 

 

 

 

 

TSTG

Storage Temperature

 

–55 to +125

°C

 

 

 

 

 

 

 

 

Note:

1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)

Symbol

Parameter

 

Min.

Typ.

Max.

Unit

VCC

Supply Voltage

5V

4.5

5.0

5.5

V

 

 

3.3V

3.0

3.3

3.6

 

 

 

 

 

 

 

 

VIH

Input High Voltage

5V

2.4

VCC + 1.0

V

 

 

3.3V

2.0

VCC + 0.3

 

 

 

 

 

 

 

 

VIL

Input Low Voltage

5V

–1.0

0.8

V

 

 

3.3V

–0.3

0.8

 

 

 

 

 

 

 

 

TA

Commercial Ambient Temperature

 

0

70

°C

 

Extended Ambient Temperature

 

–30

85

°C

 

Industrial Ambient Temperature

 

–40

85

°C

 

 

 

 

 

 

 

CAPACITANCE(1,2)

Symbol

Parameter

Max.

Unit

CIN1

Input Capacitance: A0-A9

5

pF

 

 

 

 

CIN2

Input Capacitance: RAS, UCAS, LCAS, WE, OE

7

pF

 

 

 

 

CIO

Data Input/Output Capacitance: I/O0-I/O15

7

pF

 

 

 

 

Notes:

1.Tested initially and after any design or process changes that may affect these parameters.

2.Test conditions: TA = 25°C, f = 1 MHz.

Integrated Silicon Solution, Inc. — 1-800-379-4774

5

Rev. F

03/08/00

IS41C16100

 

 

 

ISSI

®

IS41LV16100

 

 

 

 

ELECTRICAL CHARACTERISTICS(1)

 

 

 

 

 

 

(Recommended Operating Conditions unless otherwise noted.)

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

Parameter

Test Condition

Speed

Min.

Max.

Unit

 

 

 

 

 

 

 

 

IIL

Input Leakage Current

Any input 0V VIN Vcc

 

–5

5

µA

 

 

 

Other inputs not under test = 0V

 

 

 

 

 

IIO

Output Leakage Current

Output is disabled (Hi-Z)

 

–5

5

µA

 

 

 

0V VOUT Vcc

 

 

 

 

 

VOH

Output High Voltage Level

IOH = –5.0 mA (5V)

 

2.4

V

 

 

 

IOH = –2.0 mA (3.3V)

 

 

 

 

 

 

 

 

 

 

 

 

 

VOL

Output Low Voltage Level

IOL = 4.2 mA (5V)

 

0.4

V

 

 

 

IOL = 2.0 mA (3.3V)

 

 

 

 

 

 

 

 

 

 

 

 

 

ICC1

Standby Current: TTL

RAS, LCAS, UCAS VIH Commerical

5V

3

mA

 

 

 

 

3.3V

3

 

 

 

 

Extended/Industrial

5V

4

mA

 

 

 

 

3.3V

4

 

 

 

 

 

 

 

 

 

 

ICC2

Standby Current: CMOS

RAS, LCAS, UCAS VCC – 0.2V

5V

2

mA

 

 

 

 

3.3V

2

 

 

ICC3

Operating Current:

RAS, LCAS, UCAS,

-50

160

mA

 

 

Random Read/Write(2,3,4)

Address Cycling, tRC = tRC (min.)

-60

145

 

 

 

Average Power Supply Current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ICC4

Operating Current:

RAS = VIL, LCAS, UCAS,

-50

90

mA

 

 

EDO Page Mode(2,3,4)

Cycling tPC = tPC (min.)

-60

80

 

 

 

Average Power Supply Current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ICC5

Refresh Current:

RAS Cycling, LCAS, UCAS VIH

-50

160

mA

 

 

RAS-Only(2,3)

tRC = tRC (min.)

-60

145

 

 

 

Average Power Supply Current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ICC6

Refresh Current:

RAS, LCAS, UCAS Cycling

-50

160

mA

 

 

CBR(2,3,5)

tRC = tRC (min.)

-60

145

 

 

 

Average Power Supply Current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes:

1.An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.

2.Dependent on cycle rates.

3.Specified values are obtained with minimum cycle time and the output open.

4.Column-address is changed once each EDO page cycle.

5.Enables on-chip refresh and address counters.

6 Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. F

03/08/00

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