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IS41C16128 |
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IS41C16128 |
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128K x 16 (2-MBIT) DYNAMIC RAM |
AUGUST 1998 |
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WITH EDO PAGE MODE
FEATURES
•Extended Data-Out (EDO) Page Mode access cycle
•TTL compatible inputs and outputs
•Refresh Interval: 512 cycles/8 ms
•Refresh Mode : RAS-Only, CAS-before-RAS (CBR), and Hidden
•JEDEC standard pinout
•Single +5V ± 10% power supply
•Byte Write and Byte Read operation via two CAS
•Available in 40-pin SOJ and TSOP (Type II)
•Industrial temperature available
DESCRIPTION
The ISSI IS41C16128 is a 131,072 x 16-bit high-performance CMOS Dynamic Random Access Memory. The IS41C16128 offers an accelerated cycle access called EDO Page Mode. EDO Page Mode allows 256 random accesses within a single row with access cycle time as short as 12 ns per 16bit word. The Byte Write control, of upper and lower byte, makes the IS41C16128 ideal for use in 16-, 32-bit wide data bus systems.
These features make the IS41C16128 ideally suited for high band-width graphics, digital signal processing, high-performance computing systems, and peripheral applications.
The IS41C16128 is packaged in a 40-pin 400-mil SOJ and TSOP (Type II).
FUNCTIONAL BLOCK DIAGRAM
OE |
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WE |
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LCAS |
CAS |
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WE |
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OE |
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CLOCK |
CAS |
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CONTROL |
CONTROL |
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UCAS |
GENERATOR |
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LOGICS |
WE |
LOGIC |
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OE |
RAS |
RAS |
RAS |
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DATA I/O BUS |
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CLOCK |
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GENERATOR |
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COLUMN DECODERS |
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REFRESH |
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SENSE AMPLIFIERS |
I/O BUFFERS |
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COUNTER |
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I/O0-I/O15 |
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DECODER |
MEMORY ARRAY |
DATA |
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131,072 x 16 |
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ADDRESS |
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ROW |
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A0-A8 |
BUFFERS |
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This document contains PRELIMINARY data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. |
1 |
PRELIMINARY DR002-1D 08/20/98
IS41C16128
KEY TIMING PARAMETERS
Parameter |
-35 |
-40 |
-45 |
-50 |
-60 |
Max. RAS Access Time (tRAC) |
35 ns |
40 ns |
45 ns |
50 ns |
60 ns |
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Max. CAS Access Time (tCAC) |
10 ns |
12 ns |
13 ns |
14 ns |
15 ns |
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Max. Column Address Access Time (tAA) |
18 ns |
20 ns |
22 ns |
25 ns |
30 ns |
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Min. EDO Page Mode Cycle Time (tPC) |
12 ns |
15 ns |
17 ns |
20 ns |
25 ns |
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Min. Read/Write Cycle Time (tRC) |
60 ns |
75 ns |
80 ns |
90 ns |
110 ns |
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PIN CONFIGURATIONS
40-Pin TSOP (Type II) 40-Pin SOJ
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40 |
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VCC |
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1 |
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GND |
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I/O0 |
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39 |
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I/O15 |
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2 |
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I/O1 |
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I/O14 |
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3 |
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I/O2 |
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I/O13 |
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4 |
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I/O3 |
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I/O12 |
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5 |
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VCC |
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35 |
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GND |
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6 |
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I/O4 |
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I/O11 |
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I/O5 |
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33 |
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I/O10 |
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I/O6 |
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I/O9 |
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I/O7 |
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I/O8 |
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10 |
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NC |
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11 |
30 |
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NC |
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NC |
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12 |
29 |
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LCAS |
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WE |
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UCAS |
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27 |
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RAS |
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OE |
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NC |
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15 |
26 |
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A8 |
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A0 |
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16 |
25 |
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A7 |
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A1 |
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17 |
24 |
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A6 |
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A2 |
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18 |
23 |
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A5 |
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A3 |
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22 |
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A4 |
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VCC |
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20 |
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GND |
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40 |
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GND |
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VCC |
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I/O0 |
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I/O15 |
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I/O1 |
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I/O14 |
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I/O2 |
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I/O13 |
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I/O3 |
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I/O12 |
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VCC |
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GND |
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I/O4 |
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I/O11 |
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I/O5 |
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33 |
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I/O10 |
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I/O6 |
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I/O9 |
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I/O7 |
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I/O8 |
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NC |
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NC |
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11 |
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NC |
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12 |
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LCAS |
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28 |
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WE |
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UCAS |
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14 |
27 |
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RAS |
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OE |
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NC |
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26 |
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A8 |
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15 |
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A0 |
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16 |
25 |
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A7 |
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A1 |
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24 |
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A6 |
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A2 |
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A5 |
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A3 |
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19 |
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A4 |
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VCC |
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20 |
21 |
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GND |
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PIN DESCRIPTIONS
A0-A8 |
Address Inputs |
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I/O0-15 |
Data Inputs/Outputs |
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WE |
Write Enable |
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OE |
Output Enable |
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RAS |
Row Address Strobe |
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UCAS |
Upper Column Address Strobe |
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LCAS |
Lower Column Address Strobe |
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Vcc |
Power |
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GND |
Ground |
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NC |
No Connection |
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2 Integrated Silicon Solution, Inc.
PRELIMINARY DR002-1D 08/20/98
IS41C16128
TRUTH TABLE
Function |
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RAS |
LCAS |
UCAS |
WE |
OE |
Address tR/tC |
I/O |
Standby |
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H |
H |
H |
X |
X |
X |
High-Z |
Read: Word |
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L |
L |
L |
H |
L |
ROW/COL |
DOUT |
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Read: Lower Byte |
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L |
L |
H |
H |
L |
ROW/COL |
Lower Byte, DOUT |
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Upper Byte, High-Z |
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Read: Upper Byte |
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L |
H |
L |
H |
L |
ROW/COL |
Lower Byte, High-Z |
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Upper Byte, DOUT |
Write: Word (Early Write) |
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L |
L |
L |
L |
X |
ROW/COL |
DIN |
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Write: Lower Byte (Early Write) |
L |
L |
H |
L |
X |
ROW/COL |
Lower Byte, DIN |
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Upper Byte, High-Z |
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Write: Upper Byte (Early Write) |
L |
H |
L |
L |
X |
ROW/COL |
Lower Byte, High-Z |
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Upper Byte, DIN |
Read-Write(1,2) |
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L |
L |
L |
H→L |
L→H |
ROW/COL |
DOUT, DIN |
EDO Page-Mode Read(2) |
1st Cycle: |
L |
H→L |
H→L |
H |
L |
ROW/COL |
DOUT |
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2nd Cycle: |
L |
H→L |
H→L |
H |
L |
NA/COL |
DOUT |
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Any Cycle: |
L |
L→H |
L→H |
H |
L |
NA/NA |
DOUT |
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EDO Page-Mode Write(1) |
1st Cycle: |
L |
H→L |
H→L |
L |
X |
ROW/COL |
DIN |
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2nd Cycle: |
L |
H→L |
H→L |
L |
X |
NA/COL |
DIN |
EDO Page-Mode |
1st Cycle: |
L |
H→L |
H→L |
H→L |
L→H |
ROW/COL |
DOUT, DIN |
Read-Write(1,2) |
2nd Cycle: |
L |
H→L |
H→L |
H→L |
L→H |
NA/COL |
DOUT, DIN |
Hidden Refresh2) |
Read L→H→L |
L |
L |
H |
L |
ROW/COL |
DOUT |
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Write L→H→L |
L |
L |
L |
X |
ROW/COL |
DOUT |
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RAS-Only Refresh |
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L |
H |
H |
X |
X |
ROW/NA |
High-Z |
CBR Refresh(3) |
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H→L |
L |
L |
X |
X |
X |
High-Z |
Notes:
1.These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2.These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3.At least one of the two CAS signals must be active (LCAS or UCAS).
Integrated Silicon Solution, Inc. |
3 |
PRELIMINARY DR002-1D 08/20/98
IS41C16128
Functional Description
The IS41C16128 is a CMOS DRAM optimized for highspeed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 17 address bits. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first nine bits and CAS is used to latch the latter nine bits.
The IS41C16128 has two CAScontrols, LCASand UCAS. The LCAS and UCAS inputs internally generates a CAS signal functioning in an identical manner to the single CAS input on the other 128K x 16 DRAMs. The key difference is that each CAS controls its corresponding I/O tristate logic (in conjunction with OE and WE and RAS). LCAS controls I/O0 through I/O7 and UCAS controls I/O8 through I/O15.
The IS41C16128 CAS function is determined by the first CAS (LCAS or UCAS) transitioning LOW and the last transitioning back HIGH. The two CAS controls give the IS41C16128 both BYTE READ and BYTE WRITE cycle capabilities.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA, tCAC and tOEA are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters.
Write Cycle
A write cycle is initiated by the falling edge of CASand WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs last.
Refresh Cycle
To retain data, 512 refresh cycles are required in each 8 ms period. There are two ways to refresh the memory.
1.By clocking each of the 512 row addresses (A0 through A8) with RAS at least once every 8 ms. Any read, write, read-modify-write or RAS-only cycle refreshes the addressed row.
2.Using a CAS-before-RAS refresh cycle. CAS-before- RAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 9-bit counter provides the row addresses and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle.
Extended Data Out Page Mode
EDO page mode operation permits all 256 columns within a selected row to be randomly accessed at a high data rate.
In EDO page mode read cycle, the data-out is held to the next CAS cycle’s falling edge, instead of the rising edge. For this reason, the valid data output time in EDO page mode is extended compared with the fast page mode. In the fast page mode, the valid data output time becomes shorter as the CAS cycle time becomes shorter. Therefore, in EDO page mode, the timing margin in read cycle is larger than that of the fast page mode even if the CAS cycle time becomes shorter.
In EDO page mode, due to the extended data function, the CAS cycle time can be shorter than in the fast page mode if the timing margin is the same.
The EDO page mode allows both read and write operations during one RAS cycle, but the performance is equivalent to that of the fast page mode in that case.
Power-On
After application of the VCC supply, an initial pause of 200 μs is required followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS signal).
During power-on, it is recommended that RAS track with VCC or be held at a valid VIH to avoid current surges.
4 Integrated Silicon Solution, Inc.
PRELIMINARY DR002-1D 08/20/98
IS41C16128
ABSOLUTE MAXIMUM RATINGS(1)
Symbol |
Parameters |
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Rating |
Unit |
VT |
Voltage on Any Pin Relative to GND |
–1.0 to +7.0 |
V |
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VCC |
Supply Voltage |
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–1.0 to +7.0 |
V |
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IOUT |
Output Current |
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50 |
mA |
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PD |
Power Dissipation |
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1 |
W |
TA |
Operation Temperature |
Com. |
0 to +70 |
°C |
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Ind. |
–40 to +85 |
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TSTG |
Storage Temperature |
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–55 to +125 |
°C |
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Note:
1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol |
Parameter |
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Min. |
Typ. |
Max. |
Unit |
VCC |
Supply Voltage |
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4.5 |
5.0 |
5.5 |
V |
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VIH |
Input High Voltage |
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2.4 |
— |
VCC + 1.0 |
V |
VIL |
Input Low Voltage |
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–1.0 |
— |
+0.8 |
V |
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TA |
Ambient Temperature |
Com. |
0 |
— |
+70 |
°C |
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Ind. |
–40 |
— |
+85 |
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CAPACITANCE(1,2)
Symbol |
Parameter |
Max. |
Unit |
CIN1 |
Input Capacitance: A0-A8 |
5 |
pF |
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CIN2 |
Input Capacitance: RAS, UCAS, LCAS, WE, OE |
7 |
pF |
CIO |
Data Input/Output Capacitance: I/O0-I/O15 |
7 |
pF |
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Notes:
1.Tested initially and after any design or process changes that may affect these parameters.
2.Test conditions: TA = 25°C, f = 1 MHz, VCC = 5.0V + 10%.
Integrated Silicon Solution, Inc. |
5 |
PRELIMINARY DR002-1D 08/20/98
IS41C16128
ELECTRICAL CHARACTERISTICS(1) (Recommended Operation Conditions unless otherwise noted.)
Symbol |
Parameter |
Test Condition |
Speed |
Min. |
Max. |
Unit |
IIL |
Input Leakage Current |
Any input 0V < VIN < 5.5V |
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–10 |
10 |
mA |
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Other inputs not under test = 0V |
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IIO |
Output Leakage Current |
Output is disabled (Hi-Z) |
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–10 |
10 |
mA |
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0V < VOUT < 5.5V |
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VOH |
Output High Voltage Level |
IOH = –2.5 mA |
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2.4 |
— |
V |
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VOL |
Output Low Voltage Level |
IOL = +2.1 mA |
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— |
0.4 |
V |
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ICC1 |
Stand-by Current: TTL |
RAS, LCAS, UCAS ³ VIH |
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— |
2 |
mA |
ICC2 |
Stand-by Current: CMOS |
RAS, LCAS, UCAS ³ VCC – 0.2V |
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— |
1 |
mA |
ICC3 |
Operating Current: |
RAS, LCAS, UCAS, |
-35 |
— |
230 |
mA |
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Random Read/Write(2,3,4) |
Address Cycling, tRC = tRC (min.) |
-40 |
— |
130 |
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Average Power Supply Current |
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-45 |
— |
120 |
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-50 |
— |
110 |
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-60 |
— |
100 |
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ICC4 |
Operating Current: |
RAS = VIL, LCAS, UCAS, |
-35 |
— |
220 |
mA |
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EDO Page Mode(2,3,4) |
Cycling tPC = tPC (min.) |
-40 |
— |
90 |
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Average Power Supply Current |
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-45 |
— |
85 |
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-50 |
— |
80 |
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-60 |
— |
70 |
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ICC5 |
Refresh Current: |
RAS Cycling, LCAS, UCAS ³ VIH |
-35 |
— |
230 |
mA |
|
RAS-Only(2,3) |
tRC = tRC (min.) |
-40 |
— |
130 |
|
|
Average Power Supply Current |
|
-45 |
— |
120 |
|
|
|
|
-50 |
— |
100 |
|
|
|
|
-60 |
— |
100 |
|
|
|
|
|
|
|
|
ICC6 |
Refresh Current: |
RAS, LCAS, UCAS Cycling |
-35 |
— |
230 |
mA |
|
CBR(2,3,5) |
tRC = tRC (min.) |
-40 |
— |
130 |
|
|
Average Power Supply Current |
|
-45 |
— |
120 |
|
|
|
|
-50 |
— |
100 |
|
|
|
|
-60 |
— |
100 |
|
Notes:
1.An initial pause of 200 μs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2.Dependent on cycle rates.
3.Specified values are obtained with minimum cycle time and the output open.
4.Column-address is changed once each EDO page cycle.
5.Enables on-chip refresh and address counters.
6 Integrated Silicon Solution, Inc.
PRELIMINARY DR002-1D 08/20/98
IS41C16128
AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.)
|
|
-35 |
-40 |
-45 |
-50 |
-60 |
|
|||||
Symbol |
Parameter |
Min. |
Max. |
Min. |
Max. |
Min. |
Max. |
Min. |
Max. |
Min. |
Max. |
Units |
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|
|
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|
|
|
|
|
|
|
|
|
tRC |
Random READ or WRITE Cycle Time |
60 |
— |
75 |
— |
80 |
— |
90 |
— |
110 |
— |
ns |
|
|
|
|
|
|
|
|
|
|
|
|
|
tRAC |
Access Time from RAS(6, 7) |
— |
35 |
— |
40 |
— |
45 |
— |
50 |
— |
60 |
ns |
tCAC |
Access Time from CAS(6, 8, 15) |
— |
10 |
— |
12 |
— |
13 |
— |
14 |
— |
15 |
ns |
tAA |
Access Time from Column-Address(6) |
— |
18 |
— |
20 |
— |
22 |
— |
25 |
— |
30 |
ns |
tRAS |
RAS Pulse Width |
35 |
10K |
40 |
10K |
45 |
10K |
50 |
10K |
60 |
10K |
ns |
|
|
|
|
|
|
|
|
|
|
|
|
|
tRP |
RAS Precharge Time |
20 |
— |
25 |
— |
25 |
— |
30 |
— |
40 |
— |
ns |
|
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|
|
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|
|
|
|
|
|
|
|
tCAS |
CAS Pulse Width(26) |
6 |
10K |
6 |
10K |
7 |
10K |
8 |
10K |
10 |
10K |
ns |
tCP |
CAS Precharge Time(9, 25) |
5 |
— |
5 |
— |
7 |
— |
8 |
— |
10 |
— |
ns |
tCSH |
CAS Hold Time (21) |
35 |
— |
40 |
— |
45 |
— |
50 |
— |
60 |
— |
ns |
tRCD |
RAS to CAS Delay Time(10, 20) |
11 |
28 |
17 |
28 |
18 |
32 |
19 |
36 |
20 |
45 |
ns |
tASR |
Row-Address Setup Time |
0 |
— |
0 |
— |
0 |
— |
0 |
— |
0 |
— |
ns |
|
|
|
|
|
|
|
|
|
|
|
|
|
tRAH |
Row-Address Hold Time |
6 |
— |
6 |
— |
7 |
— |
8 |
— |
10 |
— |
ns |
|
|
|
|
|
|
|
|
|
|
|
|
|
tASC |
Column-Address Setup Time(20) |
0 |
— |
0 |
— |
0 |
— |
0 |
— |
0 |
— |
ns |
tCAH |
Column-Address Hold Time(20) |
6 |
— |
6 |
— |
7 |
— |
8 |
— |
10 |
— |
ns |
tAR |
Column-Address Hold Time |
30 |
— |
30 |
— |
35 |
— |
40 |
— |
40 |
— |
ns |
|
(referenced to RAS) |
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
tRAD |
RAS to Column-Address Delay Time(11) |
12 |
20 |
12 |
20 |
13 |
22 |
14 |
25 |
15 |
30 |
ns |
tRAL |
Column-Address to RAS Lead Time |
18 |
— |
20 |
— |
22 |
— |
25 |
— |
30 |
— |
ns |
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|
|
|
|
|
|
|
|
|
|
|
|
tRPC |
RAS to CAS Precharge Time |
0 |
— |
0 |
— |
0 |
— |
0 |
— |
0 |
— |
ns |
|
|
|
|
|
|
|
|
|
|
|
|
|
tRSH |
RAS Hold Time(27) |
8 |
— |
12 |
— |
13 |
— |
14 |
— |
15 |
— |
ns |
tCLZ |
CAS to Output in Low-Z(15, 29) |
3 |
— |
3 |
— |
3 |
— |
3 |
— |
3 |
— |
ns |
tCRP |
CAS to RAS Precharge Time(21) |
5 |
— |
5 |
— |
5 |
— |
5 |
— |
5 |
— |
ns |
tOD |
Output Disable Time(19, 28, 29) |
3 |
15 |
3 |
15 |
3 |
15 |
3 |
15 |
3 |
15 |
ns |
tOE |
Output Enable Time(15, 16) |
— |
10 |
— |
10 |
— |
12 |
— |
15 |
— |
15 |
ns |
tOEHC |
OE HIGH Hold Time from CAS HIGH |
10 |
— |
10 |
— |
10 |
— |
10 |
— |
10 |
— |
ns |
|
|
|
|
|
|
|
|
|
|
|
|
|
tOEP |
OE HIGH Pulse Width |
10 |
— |
10 |
— |
10 |
— |
10 |
— |
10 |
— |
ns |
|
|
|
|
|
|
|
|
|
|
|
|
|
tOES |
OE LOW to CAS HIGH Setup Time |
5 |
— |
5 |
— |
5 |
— |
5 |
— |
5 |
— |
ns |
|
|
|
|
|
|
|
|
|
|
|
|
|
tRCS |
Read Command Setup Time(17, 20) |
0 |
— |
0 |
— |
0 |
— |
0 |
— |
0 |
— |
ns |
tRRH |
Read Command Hold Time |
0 |
— |
0 |
— |
0 |
— |
0 |
— |
0 |
— |
ns |
|
(referenced to RAS)(12) |
|
|
|
|
|
|
|
|
|
|
|
tRCH |
Read Command Hold Time |
0 |
— |
0 |
— |
0 |
— |
0 |
— |
0 |
— |
ns |
|
(referenced to CAS)(12, 17, 21) |
|
|
|
|
|
|
|
|
|
|
|
tWCH |
Write Command Hold Time(17, 27) |
5 |
— |
6 |
— |
7 |
— |
8 |
— |
10 |
— |
ns |
tWCR |
Write Command Hold Time |
30 |
— |
30 |
— |
35 |
— |
40 |
— |
50 |
— |
ns |
|
(referenced to RAS)(17) |
|
|
|
|
|
|
|
|
|
|
|
tWP |
Write Command Pulse Width(17) |
5 |
— |
6 |
— |
7 |
— |
8 |
— |
10 |
— |
ns |
tWPZ |
WE Pulse Widths to Disable Outputs |
10 |
— |
10 |
— |
10 |
— |
10 |
— |
10 |
— |
ns |
|
|
|
|
|
|
|
|
|
|
|
|
|
tRWL |
Write Command to RAS Lead Time(17) |
8 |
— |
12 |
— |
13 |
— |
14 |
— |
15 |
— |
ns |
tCWL |
Write Command to CAS Lead Time(17, 21) |
8 |
— |
12 |
— |
13 |
— |
14 |
— |
15 |
— |
ns |
tWCS |
Write Command Setup Time(14, 17, 20) |
0 |
— |
0 |
— |
0 |
— |
0 |
— |
0 |
— |
ns |
tDHR |
Data-in Hold Time (referenced to RAS) |
30 |
— |
30 |
— |
35 |
— |
40 |
— |
40 |
— |
ns |
Integrated Silicon Solution, Inc. |
7 |
PRELIMINARY DR002-1D 08/20/98