IS41C16100 |
® |
IS41LV16100 |
ISSI |
1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
FEBRUARY 2000
FEATURES
•TTL compatible inputs and outputs; tristate I/O
•Refresh Interval:
—Auto refresh Mode: 1,024 cycles /16 ms
—RAS-Only, CAS-before-RAS (CBR), and Hidden
—Self refresh Mode - 1,024 cycles / 128ms
•JEDEC standard pinout
•Single power supply:
—5V ± 10% (IS41C16100)
—3.3V ± 10% (IS41LV16100)
•Byte Write and Byte Read operation via two CAS
• Extended Temperature Range -30oC to 85oC
• Industrail Temperature Range -40oC to 85oC
PIN CONFIGURATIONS
50(44)-Pin TSOP (Type II) |
42-Pin SOJ |
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44 |
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VCC |
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1 |
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GND |
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I/O0 |
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43 |
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I/O15 |
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2 |
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I/O1 |
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42 |
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I/O14 |
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3 |
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I/O2 |
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41 |
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I/O13 |
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4 |
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I/O3 |
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40 |
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I/O12 |
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5 |
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VCC |
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GND |
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6 |
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I/O4 |
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I/O11 |
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7 |
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I/O5 |
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I/O10 |
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I/O6 |
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I/O9 |
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I/O7 |
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35 |
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I/O8 |
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10 |
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NC |
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34 |
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NC |
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11 |
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NC |
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12 |
33 |
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NC |
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NC |
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13 |
32 |
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LCAS |
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14 |
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WE |
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UCAS |
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30 |
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RAS |
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OE |
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NC |
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29 |
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A9 |
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NC |
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17 |
28 |
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A8 |
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A0 |
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27 |
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A7 |
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A1 |
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26 |
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A6 |
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A2 |
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25 |
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A5 |
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A3 |
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24 |
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A4 |
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VCC |
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GND |
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42 |
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GND |
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VCC |
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1 |
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I/O0 |
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I/O15 |
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2 |
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I/O1 |
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I/O14 |
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3 |
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I/O2 |
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39 |
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I/O13 |
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I/O3 |
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I/O12 |
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VCC |
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GND |
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I/O4 |
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36 |
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I/O11 |
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7 |
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I/O5 |
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35 |
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I/O10 |
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I/O6 |
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I/O9 |
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I/O7 |
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33 |
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I/O8 |
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10 |
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NC |
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32 |
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NC |
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11 |
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NC |
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31 |
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12 |
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LCAS |
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30 |
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WE |
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13 |
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UCAS |
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29 |
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RAS |
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14 |
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OE |
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NC |
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28 |
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A9 |
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15 |
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NC |
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27 |
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A8 |
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A0 |
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26 |
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A7 |
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A1 |
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25 |
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A6 |
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A2 |
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24 |
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A5 |
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A3 |
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23 |
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A4 |
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VCC |
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GND |
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DESCRIPTION
The ISSI IS41C16100 and IS41LV16100 are 1,048,576 x 16-bit high-performance CMOS Dynamic Random Access Memories. ThesedevicesofferanacceleratedcycleaccesscalledEDOPage Mode. EDO Page Mode allows 1,024 random accesses within a singlerowwithaccesscycletimeasshortas20nsper16-bitword. The Byte Write control, of upper and lower byte, makes the IS41C16100idealforusein16-bitand32-bitwidedatabussystems.
These features make the IS41C16100and IS41LV16100 ideally suited for high-bandwidth graphics, digital signal processing, high-performancecomputingsystems,andperipheralapplications.
The IS41C16100 and IS41LV16100 are packaged in a 42-pin 400-mil SOJ and 400-mil 50- (44-) pin TSOP (Type II).
KEY TIMING PARAMETERS
Parameter |
-50 |
-60 |
Unit |
Max. RAS Access Time (tRAC) |
50 |
60 |
ns |
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Max. CAS Access Time (tCAC) |
13 |
15 |
ns |
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Max. Column Address Access Time (tAA) |
25 |
30 |
ns |
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Min. EDO Page Mode Cycle Time (tPC) |
20 |
25 |
ns |
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Min. Read/Write Cycle Time (tRC) |
84 |
104 |
ns |
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PIN DESCRIPTIONS
A0-A9 |
Address Inputs |
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I/O0-15 |
Data Inputs/Outputs |
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WE |
Write Enable |
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OE |
Output Enable |
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RAS |
Row Address Strobe |
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UCAS |
Upper Column Address Strobe |
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LCAS |
Lower Column Address Strobe |
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Vcc |
Power |
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GND |
Ground |
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NC |
No Connection |
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ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
1 |
Rev. F
03/08/00
IS41C16100 |
ISSI |
® |
IS41LV16100 |
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FUNCTIONAL BLOCK DIAGRAM
OE |
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WE |
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LCAS |
CAS |
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WE |
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OE |
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CLOCK |
CAS |
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CONTROL |
CONTROL |
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UCAS |
GENERATOR |
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LOGICS |
WE |
LOGIC |
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OE |
RAS |
RAS |
RAS |
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DATA I/O BUS |
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CLOCK |
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GENERATOR |
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COLUMN DECODERS |
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REFRESH |
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SENSE AMPLIFIERS |
I/O BUFFERS |
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COUNTER |
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I/O0-I/O15 |
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DECODER |
MEMORY ARRAY |
DATA |
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1,048,576 x 16 |
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ADDRESS |
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ROW |
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A0-A9 |
BUFFERS |
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2 |
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
Rev. F
03/08/00
IS41C16100 |
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ISSI |
® |
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IS41LV16100 |
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TRUTH TABLE |
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Function |
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RAS |
LCAS |
UCAS |
WE |
OE |
Address tR/tC |
I/O |
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Standby |
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H |
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H |
X |
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X |
High-Z |
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Read:Word |
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L |
L |
L |
H |
L |
ROW/COL |
DOUT |
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Read:LowerByte |
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L |
L |
H |
H |
L |
ROW/COL |
Lower Byte, DOUT |
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UpperByte,High-Z |
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Read:UpperByte |
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L |
H |
L |
H |
L |
ROW/COL |
LowerByte,High-Z |
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Upper Byte, DOUT |
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Write:Word(EarlyWrite) |
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L |
L |
L |
L |
X |
ROW/COL |
DIN |
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Write:LowerByte(EarlyWrite) |
L |
L |
H |
L |
X |
ROW/COL |
Lower Byte, DIN |
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UpperByte,High-Z |
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Write:UpperByte(EarlyWrite) |
L |
H |
L |
L |
X |
ROW/COL |
LowerByte,High-Z |
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Upper Byte, DIN |
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Read-Write(1,2) |
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L |
L |
L |
H→L |
L→H |
ROW/COL |
DOUT, DIN |
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EDOPage-ModeRead(2) |
1stCycle: |
L |
H→L |
H→L |
H |
L |
ROW/COL |
DOUT |
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2ndCycle: |
L |
H→L |
H→L |
H |
L |
NA/COL |
DOUT |
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AnyCycle: |
L |
L→H |
L→H |
H |
L |
NA/NA |
DOUT |
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EDOPage-ModeWrite(1) |
1stCycle: |
L |
H→L |
H→L |
L |
X |
ROW/COL |
DIN |
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2ndCycle: |
L |
H→L |
H→L |
L |
X |
NA/COL |
DIN |
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EDO Page-Mode(1,2) |
1stCycle: |
L |
H→L |
H→L |
H→L |
L→H |
ROW/COL |
DOUT, DIN |
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Read-Write |
2ndCycle: |
L |
H→L |
H→L |
H→L |
L→H |
NA/COL |
DOUT, DIN |
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HiddenRefresh |
Read(2) |
L→H→L |
L |
L |
H |
L |
ROW/COL |
DOUT |
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Write(1,3) |
L→H→L |
L |
L |
L |
X |
ROW/COL |
DOUT |
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RAS-OnlyRefresh |
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L |
H |
H |
X |
X |
ROW/NA |
High-Z |
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CBR Refresh(4) |
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H→L |
L |
L |
X |
X |
X |
High-Z |
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Notes:
1.These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2.These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3.EARLY WRITE only.
4.At least one of the two CAS signals must be active (LCAS or UCAS).
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
3 |
Rev. F
03/08/00
IS41C16100 |
ISSI |
® |
IS41LV16100 |
|
Functional Description
The IS41C16100 and IS41LV16100 is a CMOS DRAM optimized for high-speed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 16 address bits. These are entered ten bits (A0-A9) at time. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used tolatchthefirstninebitsandCASisusedtolatchthelatterninebits.
The IS41C16100 and IS41LV16100 has two CAS controls, LCASand UCAS. The LCAS and UCASinputs internally
generates a CASsignal functioning in an identical manner to the single CAS input on the other 1M x 16 DRAMs. The key difference is that each CAS controls its corresponding I/O tristate logic (in conjunction with OE and WE and RAS). LCAS controlsI/O0throughI/O7andUCAScontrolsI/O8through I/O15.
The IS41C16100 and IS41LV16100 CAS function is determined by the first CAS (LCAS or UCAS) transitioning LOW and the last transitioning back HIGH. The two CAS controls give the IS41C16100 and IS41LV16100 both BYTE READ and BYTE WRITE cycle capabilities.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA, tCAC and tOEA are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs first.
Auto Refresh Cycle
To retain data, 1,024 refresh cycles are required in each 16 ms period. There are two ways to refresh the memory.
1.By clocking each of the 1,024 row addresses (A0 through A9) with RAS at least once every 128 ms. Any read, write, read- modify-writeorRAS-onlycyclerefreshestheaddressedrow.
2.Using a CAS-before-RAS refresh cycle. CAS-before- RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 9-bit counter provides the row addresses and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle.
Self Refresh Cycle
The Self Refresh allows the user a dynamic refresh, data retention mode at the extended refresh period of 128 ms. i.e., 125 µs per row when using distributed CBR refreshes. The feature also allows the user the choice of a fully static, low power data retention mode. The optional Self Refresh feature is initiated by performing a CBR Refresh cycle and holding RAS LOW for the specified tRAS.
The Self Refresh mode is terminated by driving RAS HIGH for a minimum time of tRP. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the RAS LOW-to-HIGH transition. If the DRAM controller uses a distributed refresh sequence, a burst refresh is not required upon exiting Self Refresh.
However, if the DRAM controller utilizes a RAS-only or burst refresh sequence, all 1,024 rows must be refreshed within the average internal refresh rate, prior to the resumption of normal operation.
Extended Data Out Page Mode
EDO page mode operation permits all 1,024 columns within a selected row to be randomly accessed at a high data rate.
In EDO page mode read cycle, the data-out is held to the next CAS cycle’s falling edge, instead of the rising edge. For this reason, the valid data output time in EDO page mode is extended compared with the fast page mode. In the fast page mode, the valid data output time becomes shorter as the CAS cycle time becomes shorter. Therefore, in EDO page mode, the timing margin in read cycle is larger than that of the fast page mode even if the CAS cycle time becomes shorter.
In EDO page mode, due to the extended data function, the CAS cycle time can be shorter than in the fast page mode if the timing margin is the same.
The EDO page mode allows both read and write operations during one RAS cycle, but the performance is equivalent to that of the fast page mode in that case.
Power-On
After application of the VCC supply, an initial pause of 200 µs is required followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS signal).
During power-on, it is recommended that RAS track with VCC or be held at a valid VIH to avoid current surges.
4 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
03/08/00
IS41C16100 |
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ISSI |
® |
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IS41LV16100 |
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ABSOLUTE MAXIMUM RATINGS(1) |
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Symbol |
Parameters |
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Rating |
Unit |
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VT |
Voltage on Any Pin Relative to GND |
5V |
–1.0 to +7.0 |
V |
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3.3V |
–0.5 to +4.6 |
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VCC |
Supply Voltage |
5V |
–1.0 to +7.0 |
V |
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3.3V |
–0.5 to +4.6 |
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IOUT |
Output Current |
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50 |
mA |
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PD |
Power Dissipation |
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1 |
W |
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TA |
Commercial Operation Temperature |
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0 to +70 |
°C |
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Extendedl Operation Temperature |
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–30 to +85 |
°C |
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Industrial Operationg Temperature |
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-40 to +85 |
°C |
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TSTG |
Storage Temperature |
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–55 to +125 |
°C |
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Note:
1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol |
Parameter |
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Min. |
Typ. |
Max. |
Unit |
VCC |
Supply Voltage |
5V |
4.5 |
5.0 |
5.5 |
V |
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3.3V |
3.0 |
3.3 |
3.6 |
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VIH |
Input High Voltage |
5V |
2.4 |
— |
VCC + 1.0 |
V |
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3.3V |
2.0 |
— |
VCC + 0.3 |
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VIL |
Input Low Voltage |
5V |
–1.0 |
— |
0.8 |
V |
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3.3V |
–0.3 |
— |
0.8 |
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TA |
Commercial Ambient Temperature |
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0 |
— |
70 |
°C |
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Extended Ambient Temperature |
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–30 |
— |
85 |
°C |
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Industrial Ambient Temperature |
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–40 |
— |
85 |
°C |
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CAPACITANCE(1,2)
Symbol |
Parameter |
Max. |
Unit |
CIN1 |
Input Capacitance: A0-A9 |
5 |
pF |
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CIN2 |
Input Capacitance: RAS, UCAS, LCAS, WE, OE |
7 |
pF |
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CIO |
Data Input/Output Capacitance: I/O0-I/O15 |
7 |
pF |
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Notes:
1.Tested initially and after any design or process changes that may affect these parameters.
2.Test conditions: TA = 25°C, f = 1 MHz.
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
5 |
Rev. F
03/08/00
IS41C16100 |
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ISSI |
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IS41LV16100 |
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ELECTRICAL CHARACTERISTICS(1) |
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(Recommended Operating Conditions unless otherwise noted.) |
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Symbol |
Parameter |
Test Condition |
Speed |
Min. |
Max. |
Unit |
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IIL |
Input Leakage Current |
Any input 0V ≤ VIN ≤ Vcc |
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–5 |
5 |
µA |
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Other inputs not under test = 0V |
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IIO |
Output Leakage Current |
Output is disabled (Hi-Z) |
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–5 |
5 |
µA |
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0V ≤ VOUT ≤ Vcc |
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VOH |
Output High Voltage Level |
IOH = –5.0 mA (5V) |
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2.4 |
— |
V |
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IOH = –2.0 mA (3.3V) |
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VOL |
Output Low Voltage Level |
IOL = 4.2 mA (5V) |
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— |
0.4 |
V |
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IOL = 2.0 mA (3.3V) |
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ICC1 |
Standby Current: TTL |
RAS, LCAS, UCAS ≥ VIH Commerical |
5V |
— |
3 |
mA |
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3.3V |
— |
3 |
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Extended/Industrial |
5V |
— |
4 |
mA |
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3.3V |
— |
4 |
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ICC2 |
Standby Current: CMOS |
RAS, LCAS, UCAS ≥ VCC – 0.2V |
5V |
— |
2 |
mA |
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3.3V |
— |
2 |
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ICC3 |
Operating Current: |
RAS, LCAS, UCAS, |
-50 |
— |
160 |
mA |
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Random Read/Write(2,3,4) |
Address Cycling, tRC = tRC (min.) |
-60 |
— |
145 |
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Average Power Supply Current |
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ICC4 |
Operating Current: |
RAS = VIL, LCAS, UCAS, |
-50 |
— |
90 |
mA |
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EDO Page Mode(2,3,4) |
Cycling tPC = tPC (min.) |
-60 |
— |
80 |
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Average Power Supply Current |
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ICC5 |
Refresh Current: |
RAS Cycling, LCAS, UCAS ≥ VIH |
-50 |
— |
160 |
mA |
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RAS-Only(2,3) |
tRC = tRC (min.) |
-60 |
— |
145 |
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Average Power Supply Current |
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ICC6 |
Refresh Current: |
RAS, LCAS, UCAS Cycling |
-50 |
— |
160 |
mA |
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CBR(2,3,5) |
tRC = tRC (min.) |
-60 |
— |
145 |
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Average Power Supply Current |
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Notes:
1.An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2.Dependent on cycle rates.
3.Specified values are obtained with minimum cycle time and the output open.
4.Column-address is changed once each EDO page cycle.
5.Enables on-chip refresh and address counters.
6 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
03/08/00