TCA 785
Phase Control IC |
TCA 785 |
Features
●Reliable recognition of zero passage
●Large application scope
●May be used as zero point switch
●LSL compatible
●Three-phase operation possible (3 ICs)
●Output current 250 mA
●Large ramp current range
●Wide temperature range
Type |
Ordering Code |
Package |
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TCA 785 |
Q67000-A2321 |
P-DIP-16-1 |
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Bipolar IC
P-DIP-16-1
This phase control IC is intended to control thyristors, triacs, and transistors. The trigger pulses can be shifted within a phase angle between 0 ˚ and 180 ˚. Typical applications include converter circuits, AC controllers and three-phase current controllers.
This IC replaces the previous types TCA 780 and TCA 780 D.
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Pin Definitions and Functions |
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Pin |
Symbol |
Function |
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1 |
GND |
Ground |
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2 |
Q2 |
Output 2 inverted |
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3 |
Q U |
Output U |
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4 |
Q2 |
Output 1 inverted |
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5 |
VSYNC |
Synchronous voltage |
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6 |
I |
Inhibit |
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7 |
Q Z |
Output Z |
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8 |
V REF |
Stabilized voltage |
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9 |
R9 |
Ramp resistance |
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10 |
C10 |
Ramp capacitance |
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11 |
V11 |
Control voltage |
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12 |
C12 |
Pulse extension |
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13 |
L |
Long pulse |
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14 |
Q 1 |
Output 1 |
Pin Configuration |
15 |
Q 2 |
Output 2 |
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(top view) |
16 |
VS |
Supply voltage |
Semiconductor Group |
1 |
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09.94 |
TCA 785
Functional Description
The synchronization signal is obtained via a high-ohmic resistance from the line voltage (voltage V5). A zero voltage detector evaluates the zero passages and transfers them to the synchronization register.
This synchronization register controls a ramp generator, the capacitor C10 of which is charged by a constant current (determined by R9). If the ramp voltage V10 exceeds the control voltage V11 (triggering angle ϕ), a signal is processed to the logic. Dependent on the magnitude of the control voltage V11, the triggering angle ϕ can be shifted within a phase angle of 0˚ to 180˚.
For every half wave, a positive pulse of approx. 30 μs duration appears at the outputs Q 1 and Q 2. The pulse duration can be prolonged up to 180˚ via a capacitor C12. If pin 12 is connected to ground, pulses with a duration between ϕ and 180˚ will result.
Outputs Q 1 and Q 2 supply the inverse signals of Q 1 and Q 2.
A signal of ϕ +180˚ which can be used for controlling an external logic,is available at pin 3. A signal which corresponds to the NOR link of Q 1 and Q 2 is available at output Q Z (pin 7). The inhibit input can be used to disable outputs Q1, Q2 and Q 1 , Q 2 .
Pin 13 can be used to extend the outputs Q 1 and Q 2 to full pulse length (180˚ – ϕ).
Block Diagram |
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Semiconductor Group |
2 |
TCA 785
Pulse Diagram
Semiconductor Group |
3 |
TCA 785
Absolute Maximum Ratings
Parameter |
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Symbol |
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Limit Values |
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Unit |
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min. |
max. |
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Supply voltage |
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VS |
– 0.5 |
18 |
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V |
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Output current at pin 14, 15 |
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IQ |
– 10 |
400 |
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mA |
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Inhibit voltage |
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V6 |
– 0.5 |
VS |
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V |
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Control voltage |
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V11 |
– 0.5 |
VS |
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V |
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Voltage short-pulse circuit |
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V13 |
– 0.5 |
VS |
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V |
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Synchronization input current |
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V5 |
– 200 |
± 200 |
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μA |
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Output voltage at pin 14, 15 |
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VQ |
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VS |
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V |
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Output current at pin 2, 3, 4, 7 |
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IQ |
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10 |
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mA |
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Output voltage at pin 2, 3, 4, 7 |
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VQ |
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VS |
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V |
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Junction temperature |
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Tj |
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150 |
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˚C |
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Storage temperature |
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Tstg |
– 55 |
125 |
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˚C |
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Thermal resistance |
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system - air |
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Rth SA |
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80 |
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K/W |
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Operating Range |
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Supply voltage |
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VS |
8 |
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18 |
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V |
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Operating frequency |
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f |
10 |
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500 |
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Hz |
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Ambient temperature |
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TA |
– 25 |
85 |
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˚C |
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Characteristics |
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8 ≤ VS ≤ 18 V; – 25 ˚C ≤ TA ≤ 85 ˚C; f = 50 Hz |
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Parameter |
Symbol |
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Limit Values |
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Unit |
Test |
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Circuit |
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min. |
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typ. |
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max. |
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Supply current consumption |
IS |
4.5 |
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6.5 |
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10 |
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mA |
1 |
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S1 … S6 open |
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V11 = 0 V |
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C 10 = 47 nF; R 9 = 100 kΩ |
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Synchronization pin 5 |
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μA |
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Input current |
I5 rms |
30 |
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200 |
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1 |
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R 2 varied |
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Offset voltage |
V5 |
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30 |
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75 |
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mV |
4 |
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Control input pin 11 |
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Control voltage range |
V11 |
0.2 |
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V10 peak |
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V |
1 |
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Input resistance |
R11 |
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15 |
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kΩ |
5 |
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Semiconductor Group |
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4 |
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TCA 785
Characteristics (cont’d)
8 ≤ VS ≤ 18 V; – 25 ˚C ≤ TA ≤ 85 ˚C; f = 50 Hz
Parameter |
Symbol |
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Limit Values |
Unit |
Test |
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Circuit |
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min. |
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typ. |
max. |
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Ramp generator |
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μA |
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Charge current |
I10 |
10 |
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1000 |
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Max. ramp voltage |
V10 |
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V2 – 2 |
V |
1 |
Saturation voltage at capacitor |
V10 |
100 |
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225 |
350 |
mV |
1.6 |
Ramp resistance |
R9 |
3 |
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300 |
kΩ |
1 |
Sawtooth return time |
tf |
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80 |
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μs |
1 |
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Inhibit pin 6 |
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switch-over of pin 7 |
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Outputs disabled |
V6 L |
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3.3 |
2.5 |
V |
1 |
Outputs enabled |
V6 H |
4 |
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3.3 |
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V |
1 |
Signal transition time |
tr |
1 |
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5 |
μs |
1 |
Input current |
I6 H |
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500 |
800 |
μA |
1 |
V6 = 8 V |
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μA |
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Input current |
– I6 L |
80 |
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150 |
200 |
1 |
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V6 = 1.7 V |
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Deviation of I10 |
I10 |
– 5 |
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5 |
% |
1 |
R 9 = const. |
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VS = 12 V; C10 = 47 nF |
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% |
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Deviation of I10 |
I10 |
– 20 |
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20 |
1 |
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R 9 = const. |
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VS = 8 V to 18 V |
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Deviation of the ramp voltage |
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between 2 following |
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± 1 |
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% |
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half-waves, VS = const. |
V10 max |
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Long pulse switch-over |
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pin 13 |
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switch-over of S8 |
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Short pulse at output |
V13 H |
3.5 |
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2.5 |
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V |
1 |
Long pulse at output |
V13 L |
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2.5 |
2 |
V |
1 |
Input current |
I13 H |
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10 |
μA |
1 |
V13 = 8 V |
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μA |
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Input current |
– 13I L |
45 |
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65 |
100 |
1 |
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V13 = 1.7 V |
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Outputs pin 2, 3, 4, 7 |
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μA |
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Reverse current |
ICEO |
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10 |
2.6 |
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VQ = VS |
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Saturation voltage |
Vsat |
0.1 |
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0.4 |
2 |
V |
2.6 |
IQ = 2 mA |
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Semiconductor Group |
5 |
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