Microcomputer Components
8-Bit CMOS Microcontroller
C501
Data Sheet 04.97
C501 Data Sheet |
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Revision History : |
1997-04-01 |
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Previous Releases : |
11.92, 11.93, 08.94, 08.95, 10.96 |
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Subjects (changes since last revision) |
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(previous |
(new |
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version) |
version) |
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general |
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C501G-1E OTP version included |
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4 |
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Ordering information resorted and C501G-1E types added |
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Table with literature hints added |
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5-7 |
5-7 |
Pin configuration logic symbol for pins |
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EA/Vpp and ALE/PROG updated |
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11 |
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Pin description for ALE/PROG |
and EA/Vpp completed |
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8, 9, 10 |
8, 9, 10 |
Port 1, 3, 2 pin description: “bidirectional” replaced by “quasi- |
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bidirectional” |
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Block diagram updated for C501G-1E |
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New design of register (PSW) description |
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“Memory organization” added |
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15-18 |
16-18 |
Actualized design of the SFR tables |
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Reset value of T2CON corrected |
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25-28 |
Description for the C501-1E OTP version added |
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31 |
DC characteristics for C501-1E added |
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41 |
41 |
Timing “External Clock Drive” now behind “Data Memory Cycle” |
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43, 44 |
AC characteristics for C501-1E added |
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Edition 1997-04-01
Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München
© Siemens AG 1997.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
Packing
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred.
Components used in life-support devices or systems must be expressly authorized for such purpose!
Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG.
1A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.
2Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
8-Bit CMOS Microcontroller |
C501 |
Preliminary
•Fully compatible to standard 8051 microcontroller
•Versions for 12/24/40 MHz operating frequency
•Program memory : completely external (C501-L)
8K × 8 ROM (C501-1R)
8K × 8 OTP memory (C501-1E)
•256 × 8 RAM
•Four 8-bit ports
•Three 16-bit timers / counters (timer 2 with up/down counter feature)
•USART
•Six interrupt sources, two priority levels
•Power saving modes
•Quick Pulse programming algorithm (C501-1E only)
•2-Level program memory lock (C501-1E only)
•P-DIP-40, P-LCC-44, and P-MQFP-44 package
• Temperature ranges : SAB-C501 |
TA |
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0 ˚C to 70 ˚C |
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SAF-C501 |
TA |
: – 40 ˚C to 85 |
˚C |
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Power |
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RAM |
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Port 0 |
Ι/O |
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Saving |
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256 x 8 |
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Modes |
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T0 |
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Port 1 |
Ι/O |
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T2 |
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CPU |
USART |
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Ι/O |
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Port 2 |
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T1 |
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8K x 8 ROM (C501-1R) |
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Port 3 |
Ι/O |
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8K x 8 OTP (C501-1E) |
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MCA03238 |
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Figure 1
C501G Functional Units
Semiconductor Group |
3 |
1997-04-01 |
C501
The C501-1R contains a non-volatile 8K × 8 read-only program memory, a volatile 256 × 8 read/ write data memory, four ports, three 16-bit timers counters, a seven source, two priority level interrupt structure and a serial port. The C501-L is identical, except that it lacks the program memory on chip. The C501-1E contains a one-time programmable (OTP) program memory on chip. The term C501 refers to all versions within this specification unless otherwise noted. Further, the term C501 refers to all versions which are available in the different temperature ranges, marked with SAB-C501... or SAF-C501.... .
Ordering Information
Type |
Ordering Code |
Package |
Description |
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(8-Bit CMOS microcontroller) |
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SAB-C501G-LN |
Q67120-C969 |
P-LCC-44 |
for external memory (12 MHz) |
SAB-C501G-LP |
Q67120-C968 |
P-DIP-40 |
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SAB-C501G-LM |
Q67127-C970 |
P-MQFP-44 |
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SAB-C501G-L24N |
Q67120-C1001 |
P-LCC-44 |
for external memory (24 MHz) |
SAB-C501G-L24P |
Q67120-C999 |
P-DIP-40 |
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SAB-C501G-L24M |
Q67127-C1014 |
P-MQFP-44 |
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SAB-C501G-L40N |
Q67120-C1002 |
P-LCC-44 |
for external memory (40 MHz) |
SAB-C501G-L40P |
Q67120-C1000 |
P-DIP-40 |
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SAB-C501G-L40M |
Q67127-C1009 |
P-MQFP-44 |
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SAF-C501G-L24N |
Q67120-C1011 |
P-LCC-44 |
for external memory (24 MHz) |
SAF-C501G-L24P |
Q67120-C1010 |
P-MQFP-44 |
ext. temp. – 40 ˚C to 85 ˚C |
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SAB-C501G-1RN |
Q67120-DXXX |
P-LCC-44 |
with mask-programmable ROM (12 MHz) |
SAB-C501G-1RP |
Q67120-DXXX |
P-DIP-40 |
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SAB-C501G-1RM |
Q67127-DXXX |
P-MQFP-44 |
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SAB-C501G-1R24N |
Q67120-DXXX |
P-LCC-44 |
with mask-programmable ROM (24 MHz) |
SAB-C501G-1R24P |
Q67120-DXXX |
P-DIP-40 |
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SAB-C501G-1R24M |
Q67127-DXXX |
P-MQFP-44 |
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SAB-C501G-1R40N |
Q67120-DXXX |
P-LCC-44 |
with mask-programmable ROM (40 MHz) |
SAB-C501G-1R40P |
Q67120-DXXX |
P-DIP-40 |
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SAB-C501G-1R40M |
Q67127-DXXX |
P-MQFP-44 |
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SAF-C501G-1R24N |
Q67120-DXXX |
P-LCC-44 |
with mask-programmable ROM (24 MHz) |
SAF-C501G-1R24P |
Q67120-DXXX |
P-DIP-40 |
ext. temp. – 40 ˚C to 85 ˚C |
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SAB-C501G-1EN |
Q67120-C1054 |
P-LCC-44 |
with OTP memory (12 MHz) |
SAB-C501G-1EP |
Q67120-C1056 |
P-DIP-40 |
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SAF-C501G-1EN |
Q67120-C2002 |
P-LCC-44 |
with OTP memory (12 MHz)) |
SAF-C501G-1EP |
Q67120-C2003 |
P-DIP-40 |
ext. temp. – 40 ˚C to 85 ˚C |
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SAB-C501G-1E24N |
Q67120-C2005 |
P-LCC-44 |
with OTP memory (24 MHz) |
SAB-C501G-1E24P |
Q67120-C2006 |
P-DIP-40 |
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SAF-C501G-1E24N |
Q67120-C2008 |
P-LCC-44 |
with OTP memory (24 MHz)) |
SAF-C501G-1E24P |
Q67120-C2009 |
P-DIP-40 |
ext. temp. – 40 ˚C to 85 ˚C |
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Semiconductor Group |
4 |
1997-04-01 |
C501
Note: Versions for extended temperature range – 40 ˚C to 110 ˚C (SAH-C501G) on request. The ordering number of ROM types (DXXX extensions) is defined after program release (verification) of the customer.
Additional Literature
For further information about the C501 the following literature is available :
Title |
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Ordering Number |
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C501 |
8-Bit CMOS Microcontroller User’s Manual |
B158-H6723-X-X-7600 |
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C500 |
Microcontroller Family |
B158-H6987-X-X-7600 |
Architecture and Instruction Set User’s Manual |
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C500 |
Microcontroller Family - Pocket Guide |
B158-H6986-X-X-7600 |
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P1.4 |
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P1.3 |
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P1.2 |
P1.1/T2EX |
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P1.0/T2 |
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N.C |
V |
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P0.1/AD1 |
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P0.2/AD2 |
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P0.3/AD3 |
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CC |
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P1.5 |
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P0.4/AD4 |
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P1.6 |
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P0.5/AD5 |
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P1.7 |
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P0.6/AD6 |
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RESET |
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10 |
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36 |
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P0.7/AD7 |
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RxD/P3.0 |
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35 |
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VPP |
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C501 |
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EA/ |
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N.C. |
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12 |
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34 |
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N.C. |
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TxD/P3.1 |
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ALE/PROG |
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INT0/P3.2 |
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PSEN |
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P2.7/A15 |
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INT1/P3.3 |
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T0/P3.4 |
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30 |
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P2.6/A14 |
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T1/P3.5 |
17 |
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P2.5/A13 |
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WR/P3.6 |
RD/P3.7 |
XTAL2 |
XTAL1 |
V |
N.C. |
P2.0/A8 |
P2.1/A9 |
P2.2/A10 |
P2.3/A11 |
P2.4/A12 |
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SS |
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MCP03214
Figure 2
Pin Configuration P-LCC-44 Package (Top view)
Semiconductor Group |
5 |
1997-04-01 |
C501
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1 |
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T2/P1.0 |
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VCC |
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T2EX/P1.1 |
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39 |
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P0.0/AD0 |
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P0.1/AD1 |
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P1.2 |
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P0.2/AD2 |
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P1.3 |
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P1.4 |
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36 |
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P0.3/AD3 |
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P1.5 |
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35 |
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P0.4/AD4 |
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P1.6 |
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P0.5/AD5 |
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P0.6/AD6 |
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P1.7 |
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32 |
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RESET |
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P0.7/AD7 |
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31 |
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RxD/P3.0 |
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10 |
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EA/VPP |
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C501 |
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TxD/P3.1 |
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30 |
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ALE/PROG |
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INT0/P3.2 |
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PSEN |
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P2.7/A15 |
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INT1/P3.3 |
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27 |
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T0/P3.4 |
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P2.6/A14 |
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T1/P3.5 |
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16 |
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P2.3/A11 |
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RD/P3.7 |
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XTAL2 |
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P2.2/A10 |
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XTAL1 |
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P2.1/A9 |
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P2.0/A8 |
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VSS |
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MCP03215 |
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Figure 3
Pin Configuration P-DIP-40 Package (top view)
Semiconductor Group |
6 |
1997-04-01 |
C501
P0.4/AD4 P0.5/AD5 P0.6/AD6 |
P0.7/AD7 |
EA/V |
N.C. |
ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 |
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33 32 31 30 29 28 27 26 25 24 23 |
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P0.3/AD3 |
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34 |
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P2.4/A12 |
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P0.2/AD2 |
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35 |
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P2.3/A11 |
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P0.1/AD1 |
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36 |
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P2.2/A10 |
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P0.0/AD0 |
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37 |
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P2.1/A9 |
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VCC |
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38 |
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18 |
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P2.0/A8 |
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N.C. |
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39 |
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N.C. |
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P1.0/T2 |
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40 |
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VSS |
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P1.1/T2EX |
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41 |
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15 |
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XTAL1 |
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P1.2 |
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42 |
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14 |
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XTAL2 |
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P1.3 |
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43 |
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RD/P3.7 |
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P1.4 |
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44 |
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WR/P3.6 |
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1 |
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P1.5 P1.6 P1.7 RESET RxD/P3.0 N.C. TxD/P3.1 |
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INT0/P3.2 |
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INT1/P3.3 T0/P3.4 |
T1/P3.5 |
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MCP03216
Figure 4
Pin Configuration P-MQFP-44 Package (top view)
VCC VSS
XTAL1 |
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Port 0 |
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XTAL2 |
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8-Bit Digital Ι /O |
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Port 1 |
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8-Bit Digital Ι /O |
RESET |
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C501 |
Port 2 |
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EA/VPP |
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8-Bit Digital Ι /O |
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ALE/PROG |
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Port 3 |
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PSEN |
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8-Bit Digital Ι /O |
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MCL03217 |
Figure 5
Logic Symbol
Semiconductor Group |
7 |
1997-04-01 |
C501
Table 1
Pin Definitions and Functions
Symbol |
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Pin Number |
I/O*) |
Function |
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P-LCC-44 |
P-DIP-40 |
P-MQFP-44 |
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P1.0 – P1.7 |
2–9 |
1–8 |
40–44, |
I/O |
Port 1 |
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1–3, |
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is a quasi-bidirectional I/O port with |
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internal pull-up resistors. Port 1 pins that |
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have 1s written to them are pulled high by |
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the internal pullup resistors, and in that |
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state can be used as inputs. As inputs, |
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port 1 pins being externally pulled low will |
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source current (IIL, in the DC character- |
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istics) because of the internal pull-up |
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resistors. Port 1 also contains the timer 2 |
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pins as secondary function. The output |
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latch corresponding to a secondary |
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function must be pro-grammed to a one |
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(1) for that function to operate. |
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The secondary functions are assigned to |
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the pins of port 1, as follows: |
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2 |
1 |
40 |
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P1.0 |
T2 |
Input to counter 2 |
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3 |
2 |
41 |
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P1.1 |
T2EX |
Capture - Reload trigger of |
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timer 2 / Up-Down count |
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*) I |
= Input |
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O |
= Output |
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Semiconductor Group |
8 |
1997-04-01 |
C501
Table 1
Pin Definitions and Functions (cont’d)
Symbol |
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Pin Number |
I/O*) |
Function |
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P-LCC-44 |
P-DIP-40 |
P-MQFP-44 |
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P3.0 – P3.7 |
11, |
10–17 |
5, 7–13 |
I/O |
Port 3 |
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13–19 |
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is a quasi-bidirectional I/O port with |
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internal pull-up resistors. Port 3 pins that |
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have 1s written to them are pulled high by |
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the internal pull-up resistors, and in that |
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state they can be used as inputs. As |
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inputs, port 3 pins being externally pulled |
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low will source current (IIL, in the DC |
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characteristics) because of the internal |
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pull-up resistors. Port 3 also contains the |
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interrupt, timer, serial port 0 and external |
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memory strobe pins which are used by |
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various options. The output latch |
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corresponding to a secondary function |
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must be programmed to a one (1) for that |
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function to operate. |
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The secondary functions are assigned to |
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the pins of port 3, as follows: |
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11 |
10 |
5 |
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P3.0 |
R×D |
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receiver data input (asyn- |
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chronous) or data input |
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output (synchronous) of |
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serial interface 0 |
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13 |
11 |
7 |
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P3.1 |
T×D |
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transmitter data output |
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(asynchronous) or clock |
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output (synchronous) of |
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the serial interface 0 |
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14 |
12 |
8 |
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P3.2 |
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INT0 |
interrupt 0 input/timer 0 |
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gate control |
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15 |
13 |
9 |
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P3.3 |
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INT1 |
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interrupt 1 input/timer 1 |
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gate control |
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16 |
14 |
10 |
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P3.4 |
T0 |
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counter 0 input |
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17 |
15 |
11 |
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P3.5 |
T1 |
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counter 1 input |
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18 |
16 |
12 |
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P3.6 |
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the write control signal lat- |
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WR |
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ches the data byte from |
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port 0 into the external |
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data memory |
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19 |
17 |
13 |
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P3.7 |
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the read control signal |
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RD |
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enables the external data |
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memory to port 0 |
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*) I |
= Input |
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O |
= Output |
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Semiconductor Group |
9 |
1997-04-01 |
C501
Table 1
Pin Definitions and Functions (cont’d)
Symbol |
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Pin Number |
I/O*) |
Function |
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P-LCC-44 |
P-DIP-40 |
P-MQFP-44 |
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XTAL2 |
20 |
18 |
14 |
– |
XTAL2 |
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Output of the inverting oscillator |
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amplifier. |
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XTAL1 |
21 |
19 |
15 |
– |
XTAL1 |
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Input to the inverting oscillator amplifier |
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and input to the internal clock generator |
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circuits. |
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To drive the device from an external |
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clock source, XTAL1 should be driven, |
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while XTAL2 is left unconnected. There |
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are no requirements on the duty cycle of |
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the external clock signal, since the input |
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to the internal clocking circuitry is divided |
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down by a divide-by-two flip-flop. |
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Minimum and maximum high and low |
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times as well as rise fall times specified |
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in the AC characteristics must be |
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observed. |
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P2.0 – P2.7 |
24–31 |
21–28 |
18–25 |
I/O |
Port 2 |
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is a quasi-bidirectional I/O port with |
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internal pull-up resistors. Port 2 pins that |
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have 1s written to them are pulled high |
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by the internal pull-up resistors, and in |
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that state they can be used as inputs. As |
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inputs, port 2 pins being externally pulled |
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low will source current (IIL, in the DC |
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characteristics) because of the internal |
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pull-up resistors. Port 2 emits the high- |
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order address byte during fetches from |
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external program memory and during |
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accesses to external data memory that |
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use 16-bit addresses (MOVX @DPTR). |
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In this application it uses strong internal |
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pull-up resistors when issuing 1s. During |
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accesses to external data memory that |
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use 8-bit addresses (MOVX @Ri), port |
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2 issues the contents of the P2 special |
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function register. |
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*) I |
= Input |
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O |
= Output |
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|
Semiconductor Group |
10 |
1997-04-01 |
C501
Table 1
Pin Definitions and Functions (cont’d)
Symbol |
|
Pin Number |
I/O*) |
|
Function |
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P-LCC-44 |
P-DIP-40 |
P-MQFP-44 |
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32 |
29 |
26 |
O |
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The |
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PSEN |
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Program Store Enable |
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output is a control signal that enables the |
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external program memory to the bus |
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during external fetch operations. It is |
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activated every six oscillator periods |
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except during external data memory |
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accesses. Remains high during internal |
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program execution. |
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RESET |
10 |
9 |
4 |
I |
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RESET |
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A high level on this pin for two machine |
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cycles while the oscillator is running |
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resets the device. An internal diffused |
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resistor to VSS permits power-on reset |
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using only an external capacitor to VCC. |
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33 |
30 |
27 |
I/O |
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The Address Latch Enable |
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ALE/PROG |
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output is used for latching the low-byte of |
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the address into external memory during |
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normal operation. It is activated every six |
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oscillator periods except during an |
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external data memory access. |
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For the C501-1E this pin is also the |
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program pulse input |
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during OTP |
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(PROG) |
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memory programming. |
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VPP |
35 |
31 |
29 |
I |
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EA/ |
External Access Enable |
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When held at high level, instructions are |
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fetched from the internal ROM (C501-1R |
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and C501-1E) when the PC is less than |
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2000H. When held at low level, the C501 |
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fetches all instructions from external |
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program memory. For the C501-L this |
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pin must be tied low. |
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This pin also receives the programming |
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supply voltage VPP during OTP memory |
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programming (C501-1E) only). |
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||||
*) I |
= Input |
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||||
|
O |
= Output |
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|
Semiconductor Group |
11 |
1997-04-01 |
C501
Table 1
Pin Definitions and Functions (cont’d)
Symbol |
|
Pin Number |
I/O*) |
Function |
||
|
|
|
|
|
|
|
|
|
P-LCC-44 |
P-DIP-40 |
P-MQFP-44 |
|
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|
P0.0 – P0.7 |
43–36 |
39–32 |
37–30 |
I/O |
Port 0 |
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is an 8-bit open-drain bidirectional I/O |
|
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port. Port 0 pins that have 1s written to |
|
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|
them float, and in that state can be used |
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as high-impedance inputs. Port 0 is also |
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the multiplexed low-order address and |
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data bus during accesses to external |
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program or data memory. In this |
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application it uses strong internal pull-up |
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|
resistors when issuing 1s. |
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Port 0 also outputs the code bytes during |
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program verification in the C501-1R and |
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C501-1E. External pull-up resistors are |
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required during program verification. |
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VSS |
|
22 |
20 |
16 |
– |
Circuit ground potential |
VCC |
|
44 |
40 |
38 |
– |
Supply terminal for all operating modes |
N.C. |
|
1, 12, |
– |
6, 17, |
– |
No connection |
|
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23, 34 |
|
28, 39 |
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|
*) I |
= Input |
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O |
= Output |
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|
Semiconductor Group |
12 |
1997-04-01 |
C501
Functional Description
The C501 is fully compatible to the standard 8051 microcontroller family.
It is compatible with the 80C32/52/82C52. While maintaining all architectural and operational characteristics of the 8051microcontroller family, the C501 incorporates some enhancements in the timer 2 unit.
Figure 6 shows a block diagram of the C501.
VCC |
C501 |
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RAM |
C501-1R : ROM |
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VSS |
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C501-1E : OTP |
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XTAL1 |
OSC & Timing |
256 x 8 |
8K x 8 |
|
XTAL2 |
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RESET |
CPU |
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ALE/PROG |
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Port 0 |
|
Timer 0 |
|
Port 0 |
|
PSEN |
|
8-Bit Digit. Ι /O |
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||
EA/VPP |
Timer 1 |
|
Port 1 |
Port 1 |
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8-Bit Digit. Ι /O |
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Timer 2 |
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Port 2 |
Port 2 |
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8-Bit Digit. Ι /O |
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Interrupt Unit |
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Port 3 |
Port 3 |
|
Serial Channel |
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8-Bit Digit. Ι /O |
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||
|
(USART) |
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MCB03219 |
|
Figure 6
Block Diagram of the C501
Semiconductor Group |
13 |
1997-04-01 |
C501
CPU
The C501 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 1.0 s 24 MHz: 500 ns, 40 MHz : 300 ns).
Special Function Register PSW (Address D0H) |
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Reset Value : 00H |
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Bit No. |
MSB |
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LSB |
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D7H |
D6H |
D5H |
D4H |
D3H |
D2H |
D1H |
D0H |
|
D0H |
CY |
AC |
F0 |
RS1 |
RS0 |
OV |
F1 |
P |
PSW |
Bit |
Function |
CY |
Carry Flag |
|
Used by arithmetic instruction. |
|
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AC |
Auxiliary Carry Flag |
|
Used by instructions which execute BCD operations. |
|
|
F0 |
General Purpose Flag |
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RS1 |
Register Bank select control bits |
RS0 |
These bits are used to select one of the four register banks. |
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RS1 |
RS0 |
Function |
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0 |
0 |
Bank 0 selected, data address 00H-07H |
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0 |
1 |
Bank 1 selected, data address 08H-0FH |
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1 |
0 |
Bank 2 selected, data address 10H-17H |
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1 |
1 |
Bank 3 selected, data address 18H-1FH |
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OV |
Overflow Flag |
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Used by arithmetic instruction. |
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F1 |
General Purpose Flag |
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P |
Parity Flag |
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Set/cleared by hardware after each instruction to indicate an odd/even |
|||||
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number of "one" bits in the accumulator, i.e. even parity. |
Semiconductor Group |
14 |
1997-04-01 |
C501
Memory Organization
The C501 CPU manipulates data and operands in the following four address spaces:
–up to 64 Kbyte of internal/external program memory
–up to 64 Kbyte of external data memory
–256 bytes of internal data memory
–a 128 byte special function register area
Figure 7 illustrates the memory address spaces of the C501.
FFFF H |
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FFFF H |
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External |
External |
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Indirect |
Direct |
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Address |
Address |
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FFH |
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FFH |
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Internal |
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Special |
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Function |
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RAM |
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Register |
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2000 H |
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80 H |
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80 H |
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1FFFH |
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7F H |
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Internal |
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External |
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Internal |
||||||
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||||||
(EA = 1) |
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(EA = 0) |
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RAM |
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0000 H |
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0000 H |
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00 H |
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|||||
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||||
|
"Code Space" |
"Data Space" |
"Internal Data Space" |
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|
MCD03224 |
Figure 7
C501 Memory Map
Semiconductor Group |
15 |
1997-04-01 |