Siemens SAB-C501G-L24N, SAB-C501G-L24P, SAB-C501G-L40M, SAB-C501G-L40N, SAB-C501G-L40P Datasheet

...
0 (0)

Microcomputer Components

8-Bit CMOS Microcontroller

C501

Data Sheet 04.97

C501 Data Sheet

 

 

 

 

 

 

 

 

 

Revision History :

1997-04-01

 

 

 

 

 

 

 

 

 

 

 

 

Previous Releases :

11.92, 11.93, 08.94, 08.95, 10.96

 

 

 

 

 

Page

Page

Subjects (changes since last revision)

(previous

(new

 

 

 

 

 

 

 

 

 

version)

version)

 

 

 

 

 

 

 

 

 

 

 

 

general

 

C501G-1E OTP version included

 

 

 

4

4

Ordering information resorted and C501G-1E types added

5

5

Table with literature hints added

5-7

5-7

Pin configuration logic symbol for pins

 

 

 

 

EA/Vpp and ALE/PROG updated

11

11

 

 

 

 

 

Pin description for ALE/PROG

and EA/Vpp completed

8, 9, 10

8, 9, 10

Port 1, 3, 2 pin description: “bidirectional” replaced by “quasi-

 

 

bidirectional”

13

13

Block diagram updated for C501G-1E

14

14

New design of register (PSW) description

-

15

“Memory organization” added

15-18

16-18

Actualized design of the SFR tables

17

17

Reset value of T2CON corrected

-

25-28

Description for the C501-1E OTP version added

-

31

DC characteristics for C501-1E added

41

41

Timing “External Clock Drive” now behind “Data Memory Cycle”

-

43, 44

AC characteristics for C501-1E added

 

 

 

 

 

 

 

 

 

 

 

Edition 1997-04-01

Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München

© Siemens AG 1997.

All Rights Reserved.

Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved.

For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list).

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group.

Siemens AG is an approved CECC manufacturer.

Packing

Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.

For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred.

Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG.

1A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

2Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.

8-Bit CMOS Microcontroller

C501

Preliminary

Fully compatible to standard 8051 microcontroller

Versions for 12/24/40 MHz operating frequency

Program memory : completely external (C501-L)

8K × 8 ROM (C501-1R)

8K × 8 OTP memory (C501-1E)

256 × 8 RAM

Four 8-bit ports

Three 16-bit timers / counters (timer 2 with up/down counter feature)

USART

Six interrupt sources, two priority levels

Power saving modes

Quick Pulse programming algorithm (C501-1E only)

2-Level program memory lock (C501-1E only)

P-DIP-40, P-LCC-44, and P-MQFP-44 package

Temperature ranges : SAB-C501

TA

:

0 ˚C to 70 ˚C

 

SAF-C501

TA

: – 40 ˚C to 85

˚C

 

Power

 

RAM

 

Port 0

Ι/O

 

Saving

 

 

 

 

256 x 8

 

 

Modes

 

 

 

 

 

 

 

 

 

 

 

 

 

T0

 

Port 1

Ι/O

 

 

 

 

T2

 

 

 

CPU

USART

 

Ι/O

 

 

 

Port 2

 

 

 

T1

 

 

 

 

8K x 8 ROM (C501-1R)

 

Port 3

Ι/O

 

 

 

 

 

 

 

8K x 8 OTP (C501-1E)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MCA03238

 

 

 

 

 

 

 

Figure 1

C501G Functional Units

Semiconductor Group

3

1997-04-01

C501

The C501-1R contains a non-volatile 8K × 8 read-only program memory, a volatile 256 × 8 read/ write data memory, four ports, three 16-bit timers counters, a seven source, two priority level interrupt structure and a serial port. The C501-L is identical, except that it lacks the program memory on chip. The C501-1E contains a one-time programmable (OTP) program memory on chip. The term C501 refers to all versions within this specification unless otherwise noted. Further, the term C501 refers to all versions which are available in the different temperature ranges, marked with SAB-C501... or SAF-C501.... .

Ordering Information

Type

Ordering Code

Package

Description

 

 

 

(8-Bit CMOS microcontroller)

 

 

 

 

SAB-C501G-LN

Q67120-C969

P-LCC-44

for external memory (12 MHz)

SAB-C501G-LP

Q67120-C968

P-DIP-40

 

SAB-C501G-LM

Q67127-C970

P-MQFP-44

 

 

 

 

 

SAB-C501G-L24N

Q67120-C1001

P-LCC-44

for external memory (24 MHz)

SAB-C501G-L24P

Q67120-C999

P-DIP-40

 

SAB-C501G-L24M

Q67127-C1014

P-MQFP-44

 

 

 

 

 

SAB-C501G-L40N

Q67120-C1002

P-LCC-44

for external memory (40 MHz)

SAB-C501G-L40P

Q67120-C1000

P-DIP-40

 

SAB-C501G-L40M

Q67127-C1009

P-MQFP-44

 

 

 

 

 

SAF-C501G-L24N

Q67120-C1011

P-LCC-44

for external memory (24 MHz)

SAF-C501G-L24P

Q67120-C1010

P-MQFP-44

ext. temp. – 40 ˚C to 85 ˚C

 

 

 

 

 

 

 

 

SAB-C501G-1RN

Q67120-DXXX

P-LCC-44

with mask-programmable ROM (12 MHz)

SAB-C501G-1RP

Q67120-DXXX

P-DIP-40

 

SAB-C501G-1RM

Q67127-DXXX

P-MQFP-44

 

 

 

 

 

SAB-C501G-1R24N

Q67120-DXXX

P-LCC-44

with mask-programmable ROM (24 MHz)

SAB-C501G-1R24P

Q67120-DXXX

P-DIP-40

 

SAB-C501G-1R24M

Q67127-DXXX

P-MQFP-44

 

 

 

 

 

SAB-C501G-1R40N

Q67120-DXXX

P-LCC-44

with mask-programmable ROM (40 MHz)

SAB-C501G-1R40P

Q67120-DXXX

P-DIP-40

 

SAB-C501G-1R40M

Q67127-DXXX

P-MQFP-44

 

 

 

 

 

SAF-C501G-1R24N

Q67120-DXXX

P-LCC-44

with mask-programmable ROM (24 MHz)

SAF-C501G-1R24P

Q67120-DXXX

P-DIP-40

ext. temp. – 40 ˚C to 85 ˚C

 

 

 

 

 

 

 

 

SAB-C501G-1EN

Q67120-C1054

P-LCC-44

with OTP memory (12 MHz)

SAB-C501G-1EP

Q67120-C1056

P-DIP-40

 

 

 

 

 

SAF-C501G-1EN

Q67120-C2002

P-LCC-44

with OTP memory (12 MHz))

SAF-C501G-1EP

Q67120-C2003

P-DIP-40

ext. temp. – 40 ˚C to 85 ˚C

 

 

 

 

SAB-C501G-1E24N

Q67120-C2005

P-LCC-44

with OTP memory (24 MHz)

SAB-C501G-1E24P

Q67120-C2006

P-DIP-40

 

 

 

 

 

SAF-C501G-1E24N

Q67120-C2008

P-LCC-44

with OTP memory (24 MHz))

SAF-C501G-1E24P

Q67120-C2009

P-DIP-40

ext. temp. – 40 ˚C to 85 ˚C

 

 

 

 

Semiconductor Group

4

1997-04-01

C501

Note: Versions for extended temperature range – 40 ˚C to 110 ˚C (SAH-C501G) on request. The ordering number of ROM types (DXXX extensions) is defined after program release (verification) of the customer.

Additional Literature

For further information about the C501 the following literature is available :

Title

 

Ordering Number

 

 

 

C501

8-Bit CMOS Microcontroller User’s Manual

B158-H6723-X-X-7600

 

 

 

C500

Microcontroller Family

B158-H6987-X-X-7600

Architecture and Instruction Set User’s Manual

 

 

 

 

C500

Microcontroller Family - Pocket Guide

B158-H6986-X-X-7600

 

 

 

 

 

 

 

 

P1.4

 

P1.3

 

P1.2

P1.1/T2EX

 

P1.0/T2

 

N.C

V

 

P0.0/AD0

 

P0.1/AD1

 

P0.2/AD2

 

P0.3/AD3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

5

4

 

3

 

2

 

1

 

44

43

42

41

40

 

 

 

 

 

 

 

 

 

 

P1.5

 

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

39

 

P0.4/AD4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.6

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

38

 

P0.5/AD5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.7

 

9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

37

 

P0.6/AD6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RESET

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

36

 

P0.7/AD7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RxD/P3.0

 

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

35

 

 

 

VPP

 

 

 

 

 

 

 

 

 

C501

 

 

 

 

 

 

 

 

 

 

 

 

EA/

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N.C.

 

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

34

 

N.C.

 

TxD/P3.1

 

13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

33

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ALE/PROG

 

 

 

 

 

14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

32

 

 

 

 

 

 

INT0/P3.2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PSEN

 

 

 

 

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

 

P2.7/A15

INT1/P3.3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T0/P3.4

 

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

30

 

P2.6/A14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T1/P3.5

17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

29

 

P2.5/A13

 

 

 

 

18

19

20

21

22

23

24

25

26

27

28

 

 

 

 

 

 

 

WR/P3.6

RD/P3.7

XTAL2

XTAL1

V

N.C.

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

 

 

 

 

SS

 

 

 

 

 

 

MCP03214

Figure 2

Pin Configuration P-LCC-44 Package (Top view)

Semiconductor Group

5

1997-04-01

C501

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

T2/P1.0

 

40

 

VCC

 

 

 

 

 

 

 

 

 

 

 

 

T2EX/P1.1

 

2

39

 

P0.0/AD0

 

 

 

 

 

 

 

38

 

P0.1/AD1

 

 

 

 

 

P1.2

 

3

 

 

 

 

 

 

 

 

37

 

P0.2/AD2

 

 

 

 

 

P1.3

 

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.4

 

5

36

 

P0.3/AD3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.5

 

6

35

 

P0.4/AD4

 

 

 

 

 

P1.6

 

7

34

 

P0.5/AD5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

33

 

P0.6/AD6

 

 

 

 

 

P1.7

 

8

 

 

 

 

 

 

 

 

 

32

 

 

 

 

 

 

 

 

 

 

RESET

 

9

 

P0.7/AD7

 

 

 

 

 

 

 

 

31

 

 

 

 

 

 

 

 

RxD/P3.0

 

10

 

 

EA/VPP

 

 

 

 

 

 

 

 

C501

 

 

 

 

 

 

 

 

TxD/P3.1

 

11

30

 

ALE/PROG

 

 

 

 

 

 

 

 

12

29

 

 

 

 

 

 

 

 

INT0/P3.2

 

 

 

PSEN

 

 

 

 

 

 

 

 

 

13

28

 

P2.7/A15

 

 

 

 

 

 

 

INT1/P3.3

 

 

 

 

 

 

 

 

 

 

27

 

 

 

 

 

 

 

 

 

 

T0/P3.4

 

14

 

P2.6/A14

 

 

 

 

 

 

 

15

26

 

 

 

 

 

 

 

 

 

 

T1/P3.5

 

 

P2.5/A13

 

 

 

 

 

 

 

16

25

 

P2.4/A12

 

 

WR/P3.6

 

 

 

 

 

 

 

 

 

17

24

 

P2.3/A11

 

 

 

RD/P3.7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XTAL2

 

18

23

 

P2.2/A10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XTAL1

 

19

22

 

P2.1/A9

 

 

 

 

 

 

 

20

21

 

P2.0/A8

 

 

 

 

 

VSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MCP03215

 

 

 

 

 

 

 

Figure 3

Pin Configuration P-DIP-40 Package (top view)

Semiconductor Group

6

1997-04-01

C501

P0.4/AD4 P0.5/AD5 P0.6/AD6

P0.7/AD7

EA/V

N.C.

ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13

 

 

 

 

 

 

 

 

 

PP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

33 32 31 30 29 28 27 26 25 24 23

 

 

 

 

 

 

P0.3/AD3

 

 

34

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

22

 

 

 

 

P2.4/A12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P0.2/AD2

 

 

 

35

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

21

 

 

 

 

P2.3/A11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P0.1/AD1

 

 

 

36

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20

 

 

 

 

P2.2/A10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P0.0/AD0

 

 

 

37

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

19

 

 

 

 

P2.1/A9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

 

 

 

38

 

 

 

 

 

 

 

 

C501

 

 

 

 

 

 

18

 

 

 

 

P2.0/A8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N.C.

 

 

 

39

 

 

 

 

 

 

 

 

 

 

 

 

 

 

17

 

 

 

 

N.C.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.0/T2

 

 

 

40

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16

 

 

 

VSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.1/T2EX

 

 

 

41

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

 

 

 

 

XTAL1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.2

 

 

 

42

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14

 

 

 

 

XTAL2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.3

 

 

 

43

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RD/P3.7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.4

 

 

 

44

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WR/P3.6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

2

 

3

 

4

 

5

 

6

 

7

 

8

 

9

10

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.5 P1.6 P1.7 RESET RxD/P3.0 N.C. TxD/P3.1

 

INT0/P3.2

 

INT1/P3.3 T0/P3.4

T1/P3.5

 

 

 

 

 

MCP03216

Figure 4

Pin Configuration P-MQFP-44 Package (top view)

VCC VSS

XTAL1

 

 

 

 

 

 

Port 0

 

 

 

 

 

 

 

 

 

 

 

XTAL2

 

 

 

 

 

8-Bit Digital Ι /O

 

 

 

 

Port 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8-Bit Digital Ι /O

RESET

 

 

 

C501

Port 2

 

 

 

 

 

 

 

 

 

 

 

 

EA/VPP

 

 

 

 

 

8-Bit Digital Ι /O

 

 

 

 

ALE/PROG

 

 

 

 

Port 3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PSEN

 

 

 

 

 

 

8-Bit Digital Ι /O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MCL03217

Figure 5

Logic Symbol

Semiconductor Group

7

1997-04-01

C501

Table 1

Pin Definitions and Functions

Symbol

 

Pin Number

I/O*)

Function

 

 

 

 

 

 

 

 

 

 

 

P-LCC-44

P-DIP-40

P-MQFP-44

 

 

 

 

 

 

 

 

 

 

 

 

P1.0 – P1.7

2–9

1–8

40–44,

I/O

Port 1

 

 

 

 

 

 

1–3,

 

is a quasi-bidirectional I/O port with

 

 

 

 

 

 

internal pull-up resistors. Port 1 pins that

 

 

 

 

 

 

have 1s written to them are pulled high by

 

 

 

 

 

 

the internal pullup resistors, and in that

 

 

 

 

 

 

state can be used as inputs. As inputs,

 

 

 

 

 

 

port 1 pins being externally pulled low will

 

 

 

 

 

 

source current (IIL, in the DC character-

 

 

 

 

 

 

istics) because of the internal pull-up

 

 

 

 

 

 

resistors. Port 1 also contains the timer 2

 

 

 

 

 

 

pins as secondary function. The output

 

 

 

 

 

 

latch corresponding to a secondary

 

 

 

 

 

 

function must be pro-grammed to a one

 

 

 

 

 

 

(1) for that function to operate.

 

 

 

 

 

 

The secondary functions are assigned to

 

 

 

 

 

 

the pins of port 1, as follows:

 

 

2

1

40

 

P1.0

T2

Input to counter 2

 

 

3

2

41

 

P1.1

T2EX

Capture - Reload trigger of

 

 

 

 

 

 

 

 

timer 2 / Up-Down count

 

 

 

 

 

 

 

 

 

*) I

= Input

 

 

 

 

 

 

O

= Output

 

 

 

 

 

 

Semiconductor Group

8

1997-04-01

C501

Table 1

Pin Definitions and Functions (cont’d)

Symbol

 

Pin Number

I/O*)

Function

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P-LCC-44

P-DIP-40

P-MQFP-44

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P3.0 – P3.7

11,

10–17

5, 7–13

I/O

Port 3

 

 

 

 

 

 

 

 

13–19

 

 

 

is a quasi-bidirectional I/O port with

 

 

 

 

 

 

internal pull-up resistors. Port 3 pins that

 

 

 

 

 

 

have 1s written to them are pulled high by

 

 

 

 

 

 

the internal pull-up resistors, and in that

 

 

 

 

 

 

state they can be used as inputs. As

 

 

 

 

 

 

inputs, port 3 pins being externally pulled

 

 

 

 

 

 

low will source current (IIL, in the DC

 

 

 

 

 

 

characteristics) because of the internal

 

 

 

 

 

 

pull-up resistors. Port 3 also contains the

 

 

 

 

 

 

interrupt, timer, serial port 0 and external

 

 

 

 

 

 

memory strobe pins which are used by

 

 

 

 

 

 

various options. The output latch

 

 

 

 

 

 

corresponding to a secondary function

 

 

 

 

 

 

must be programmed to a one (1) for that

 

 

 

 

 

 

function to operate.

 

 

 

 

 

 

The secondary functions are assigned to

 

 

 

 

 

 

the pins of port 3, as follows:

 

 

11

10

5

 

P3.0

R×D

 

receiver data input (asyn-

 

 

 

 

 

 

 

 

 

 

 

chronous) or data input

 

 

 

 

 

 

 

 

 

 

 

output (synchronous) of

 

 

 

 

 

 

 

 

 

 

 

serial interface 0

 

 

13

11

7

 

P3.1

T×D

 

transmitter data output

 

 

 

 

 

 

 

 

 

 

 

(asynchronous) or clock

 

 

 

 

 

 

 

 

 

 

 

output (synchronous) of

 

 

 

 

 

 

 

 

 

 

 

the serial interface 0

 

 

14

12

8

 

P3.2

 

 

 

 

 

 

 

 

INT0

interrupt 0 input/timer 0

 

 

 

 

 

 

 

 

 

 

 

gate control

 

 

15

13

9

 

P3.3

 

 

 

 

 

 

 

 

INT1

 

interrupt 1 input/timer 1

 

 

 

 

 

 

 

 

 

 

 

gate control

 

 

16

14

10

 

P3.4

T0

 

counter 0 input

 

 

17

15

11

 

P3.5

T1

 

counter 1 input

 

 

18

16

12

 

P3.6

 

 

 

 

the write control signal lat-

 

 

WR

 

 

 

 

 

 

 

 

 

 

 

 

ches the data byte from

 

 

 

 

 

 

 

 

 

 

 

port 0 into the external

 

 

 

 

 

 

 

 

 

 

 

data memory

 

 

19

17

13

 

P3.7

 

 

 

the read control signal

 

 

RD

 

 

 

 

 

 

 

 

 

 

 

 

enables the external data

 

 

 

 

 

 

 

 

 

 

 

memory to port 0

 

 

 

 

 

 

 

 

 

 

 

 

 

*) I

= Input

 

 

 

 

 

 

 

 

 

 

O

= Output

 

 

 

 

 

 

 

 

 

 

Semiconductor Group

9

1997-04-01

C501

Table 1

Pin Definitions and Functions (cont’d)

Symbol

 

Pin Number

I/O*)

Function

 

 

 

 

 

 

 

 

P-LCC-44

P-DIP-40

P-MQFP-44

 

 

 

 

 

 

 

 

XTAL2

20

18

14

XTAL2

 

 

 

 

 

 

Output of the inverting oscillator

 

 

 

 

 

 

amplifier.

 

 

 

 

 

 

XTAL1

21

19

15

XTAL1

 

 

 

 

 

 

Input to the inverting oscillator amplifier

 

 

 

 

 

 

and input to the internal clock generator

 

 

 

 

 

 

circuits.

 

 

 

 

 

 

To drive the device from an external

 

 

 

 

 

 

clock source, XTAL1 should be driven,

 

 

 

 

 

 

while XTAL2 is left unconnected. There

 

 

 

 

 

 

are no requirements on the duty cycle of

 

 

 

 

 

 

the external clock signal, since the input

 

 

 

 

 

 

to the internal clocking circuitry is divided

 

 

 

 

 

 

down by a divide-by-two flip-flop.

 

 

 

 

 

 

Minimum and maximum high and low

 

 

 

 

 

 

times as well as rise fall times specified

 

 

 

 

 

 

in the AC characteristics must be

 

 

 

 

 

 

observed.

 

 

 

 

 

 

P2.0 – P2.7

24–31

21–28

18–25

I/O

Port 2

 

 

 

 

 

 

is a quasi-bidirectional I/O port with

 

 

 

 

 

 

internal pull-up resistors. Port 2 pins that

 

 

 

 

 

 

have 1s written to them are pulled high

 

 

 

 

 

 

by the internal pull-up resistors, and in

 

 

 

 

 

 

that state they can be used as inputs. As

 

 

 

 

 

 

inputs, port 2 pins being externally pulled

 

 

 

 

 

 

low will source current (IIL, in the DC

 

 

 

 

 

 

characteristics) because of the internal

 

 

 

 

 

 

pull-up resistors. Port 2 emits the high-

 

 

 

 

 

 

order address byte during fetches from

 

 

 

 

 

 

external program memory and during

 

 

 

 

 

 

accesses to external data memory that

 

 

 

 

 

 

use 16-bit addresses (MOVX @DPTR).

 

 

 

 

 

 

In this application it uses strong internal

 

 

 

 

 

 

pull-up resistors when issuing 1s. During

 

 

 

 

 

 

accesses to external data memory that

 

 

 

 

 

 

use 8-bit addresses (MOVX @Ri), port

 

 

 

 

 

 

2 issues the contents of the P2 special

 

 

 

 

 

 

function register.

 

 

 

 

 

 

 

*) I

= Input

 

 

 

 

 

O

= Output

 

 

 

 

Semiconductor Group

10

1997-04-01

C501

Table 1

Pin Definitions and Functions (cont’d)

Symbol

 

Pin Number

I/O*)

 

Function

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P-LCC-44

P-DIP-40

P-MQFP-44

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

32

29

26

O

 

The

 

 

 

 

 

PSEN

 

 

Program Store Enable

 

 

 

 

 

 

 

 

 

 

 

output is a control signal that enables the

 

 

 

 

 

 

 

 

 

 

 

external program memory to the bus

 

 

 

 

 

 

 

 

 

 

 

during external fetch operations. It is

 

 

 

 

 

 

 

 

 

 

 

activated every six oscillator periods

 

 

 

 

 

 

 

 

 

 

 

except during external data memory

 

 

 

 

 

 

 

 

 

 

 

accesses. Remains high during internal

 

 

 

 

 

 

 

 

 

 

 

program execution.

 

 

 

 

 

 

 

RESET

10

9

4

I

 

RESET

 

 

 

 

 

 

 

 

 

 

 

A high level on this pin for two machine

 

 

 

 

 

 

 

 

 

 

 

cycles while the oscillator is running

 

 

 

 

 

 

 

 

 

 

 

resets the device. An internal diffused

 

 

 

 

 

 

 

 

 

 

 

resistor to VSS permits power-on reset

 

 

 

 

 

 

 

 

 

 

 

using only an external capacitor to VCC.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

33

30

27

I/O

 

The Address Latch Enable

ALE/PROG

 

 

 

 

 

 

 

 

 

 

 

output is used for latching the low-byte of

 

 

 

 

 

 

 

 

 

 

 

the address into external memory during

 

 

 

 

 

 

 

 

 

 

 

normal operation. It is activated every six

 

 

 

 

 

 

 

 

 

 

 

oscillator periods except during an

 

 

 

 

 

 

 

 

 

 

 

external data memory access.

 

 

 

 

 

 

 

 

 

 

 

For the C501-1E this pin is also the

 

 

 

 

 

 

 

 

 

 

 

program pulse input

 

 

during OTP

 

 

 

 

 

 

 

 

 

 

 

(PROG)

 

 

 

 

 

 

 

 

 

 

 

memory programming.

 

 

 

 

 

 

 

 

 

 

VPP

35

31

29

I

 

 

 

 

 

EA/

External Access Enable

 

 

 

 

 

 

 

 

 

 

 

When held at high level, instructions are

 

 

 

 

 

 

 

 

 

 

 

fetched from the internal ROM (C501-1R

 

 

 

 

 

 

 

 

 

 

 

and C501-1E) when the PC is less than

 

 

 

 

 

 

 

 

 

 

 

2000H. When held at low level, the C501

 

 

 

 

 

 

 

 

 

 

 

fetches all instructions from external

 

 

 

 

 

 

 

 

 

 

 

program memory. For the C501-L this

 

 

 

 

 

 

 

 

 

 

 

pin must be tied low.

 

 

 

 

 

 

 

 

 

 

 

This pin also receives the programming

 

 

 

 

 

 

 

 

 

 

 

supply voltage VPP during OTP memory

 

 

 

 

 

 

 

 

 

 

 

programming (C501-1E) only).

 

 

 

 

 

 

 

 

 

 

 

 

 

*) I

= Input

 

 

 

 

 

 

 

 

 

 

 

 

O

= Output

 

 

 

 

 

 

 

 

 

 

Semiconductor Group

11

1997-04-01

C501

Table 1

Pin Definitions and Functions (cont’d)

Symbol

 

Pin Number

I/O*)

Function

 

 

 

 

 

 

 

 

P-LCC-44

P-DIP-40

P-MQFP-44

 

 

 

 

 

 

 

 

P0.0 – P0.7

43–36

39–32

37–30

I/O

Port 0

 

 

 

 

 

 

is an 8-bit open-drain bidirectional I/O

 

 

 

 

 

 

port. Port 0 pins that have 1s written to

 

 

 

 

 

 

them float, and in that state can be used

 

 

 

 

 

 

as high-impedance inputs. Port 0 is also

 

 

 

 

 

 

the multiplexed low-order address and

 

 

 

 

 

 

data bus during accesses to external

 

 

 

 

 

 

program or data memory. In this

 

 

 

 

 

 

application it uses strong internal pull-up

 

 

 

 

 

 

resistors when issuing 1s.

 

 

 

 

 

 

Port 0 also outputs the code bytes during

 

 

 

 

 

 

program verification in the C501-1R and

 

 

 

 

 

 

C501-1E. External pull-up resistors are

 

 

 

 

 

 

required during program verification.

 

 

 

 

 

 

 

VSS

 

22

20

16

Circuit ground potential

VCC

 

44

40

38

Supply terminal for all operating modes

N.C.

 

1, 12,

6, 17,

No connection

 

 

23, 34

 

28, 39

 

 

 

 

 

 

 

 

 

*) I

= Input

 

 

 

 

O

= Output

 

 

 

 

Semiconductor Group

12

1997-04-01

Siemens SAB-C501G-L24N, SAB-C501G-L24P, SAB-C501G-L40M, SAB-C501G-L40N, SAB-C501G-L40P Datasheet

C501

Functional Description

The C501 is fully compatible to the standard 8051 microcontroller family.

It is compatible with the 80C32/52/82C52. While maintaining all architectural and operational characteristics of the 8051microcontroller family, the C501 incorporates some enhancements in the timer 2 unit.

Figure 6 shows a block diagram of the C501.

VCC

C501

 

 

 

 

RAM

C501-1R : ROM

 

VSS

 

 

 

 

C501-1E : OTP

 

 

 

 

 

XTAL1

OSC & Timing

256 x 8

8K x 8

 

XTAL2

 

 

 

 

 

 

 

RESET

CPU

 

 

 

ALE/PROG

 

 

 

Port 0

 

Timer 0

 

Port 0

PSEN

 

8-Bit Digit. Ι /O

 

 

 

EA/VPP

Timer 1

 

Port 1

Port 1

 

 

 

 

 

 

8-Bit Digit. Ι /O

 

 

 

 

 

Timer 2

 

 

 

 

 

 

Port 2

Port 2

 

 

 

8-Bit Digit. Ι /O

 

 

 

 

 

Interrupt Unit

 

 

 

 

 

 

Port 3

Port 3

 

Serial Channel

 

8-Bit Digit. Ι /O

 

 

 

 

(USART)

 

 

 

 

 

 

MCB03219

 

Figure 6

Block Diagram of the C501

Semiconductor Group

13

1997-04-01

C501

CPU

The C501 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 1.0 s 24 MHz: 500 ns, 40 MHz : 300 ns).

Special Function Register PSW (Address D0H)

 

 

Reset Value : 00H

Bit No.

MSB

 

 

 

 

 

 

LSB

 

D7H

D6H

D5H

D4H

D3H

D2H

D1H

D0H

D0H

CY

AC

F0

RS1

RS0

OV

F1

P

PSW

Bit

Function

CY

Carry Flag

 

Used by arithmetic instruction.

 

 

AC

Auxiliary Carry Flag

 

Used by instructions which execute BCD operations.

 

 

F0

General Purpose Flag

 

 

RS1

Register Bank select control bits

RS0

These bits are used to select one of the four register banks.

 

 

 

 

 

 

 

 

 

RS1

RS0

Function

 

 

 

 

 

 

 

 

 

 

 

0

0

Bank 0 selected, data address 00H-07H

 

 

 

 

0

1

Bank 1 selected, data address 08H-0FH

 

 

 

 

1

0

Bank 2 selected, data address 10H-17H

 

 

 

 

1

1

Bank 3 selected, data address 18H-1FH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OV

Overflow Flag

 

 

 

 

Used by arithmetic instruction.

 

 

 

 

 

 

 

F1

General Purpose Flag

 

 

 

 

 

 

 

 

 

 

P

Parity Flag

 

 

 

 

 

Set/cleared by hardware after each instruction to indicate an odd/even

 

number of "one" bits in the accumulator, i.e. even parity.

Semiconductor Group

14

1997-04-01

C501

Memory Organization

The C501 CPU manipulates data and operands in the following four address spaces:

up to 64 Kbyte of internal/external program memory

up to 64 Kbyte of external data memory

256 bytes of internal data memory

a 128 byte special function register area

Figure 7 illustrates the memory address spaces of the C501.

FFFF H

 

FFFF H

 

 

External

External

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Indirect

Direct

 

 

 

 

 

 

 

 

Address

Address

 

 

 

 

 

 

 

 

 

 

FFH

 

 

FFH

 

 

 

 

 

 

 

 

Internal

 

Special

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Function

 

 

 

 

 

 

 

 

 

RAM

 

 

 

 

 

 

 

 

 

 

 

 

 

Register

 

 

 

 

 

2000 H

 

 

 

 

80 H

 

80 H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1FFFH

 

 

 

 

 

 

7F H

Internal

 

External

 

 

 

 

Internal

 

 

 

 

 

 

 

 

(EA = 1)

 

(EA = 0)

 

 

 

 

 

RAM

 

 

 

 

 

 

 

0000 H

 

0000 H

 

 

 

 

00 H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

"Code Space"

"Data Space"

"Internal Data Space"

 

 

 

 

 

 

 

 

 

 

 

 

MCD03224

Figure 7

C501 Memory Map

Semiconductor Group

15

1997-04-01

Loading...
+ 33 hidden pages