RED PLCD5580 YELLOW PLCD5581
HIGH EFFICIENCY RED PLCD5582
GREEN PLCD5583
HIGH EFFICIENCY GREEN PLCD5584 Low Power 0.145” 8-Character, 5x5 Dot Matrix Parallel Input Alphanumeric Intelligent Display
FEATURES
•Eight 0.145” (3.68 mm) High 5 x 5 Dot Matrix Characters in Red, Yellow, High Efficiency Red, Green, or High Efficiency Green
•Built-in 2 Page, 256 Character ROM. Both Pages Mask Programmable for Custom Fonts
•Built-in Decoders, Multiplexers and Drivers
•Wide Viewing Angle, X Axis ±50°, Y Axis ±65°
•Programmable Features:
–Individual Flashing Character
–Full Display Blinking
–Multi-Level Dimming and Blanking
–Clear Function
–Lamp Test
•Internal or External Clock
•End Stackable Dual-In-Line Plastic Package
•Low Power: 20% Less Power Consumption Than 5 X 7 Format
Package Dimensions in inches (mm)
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1.680 (42.67) max. |
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0.105 |
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0.086 |
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0.210 |
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(2.19) |
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(5.34) |
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(2.67) |
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0.145 |
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(3.68) |
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0.771 |
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0.600 |
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(19.58) |
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0.386 |
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(15.24) |
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(9.8) |
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Pin 1 Indicator |
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0.012 (0.30) typ. |
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Part Number |
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Intensity Code |
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Color Bin |
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EIA Date |
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(For Yellow Only) |
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Code |
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0.209 (5.31) |
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PLCD558X WW |
Z |
1 |
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SIEMENS |
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0.189 |
0.018 typ. |
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0.100 |
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0.160±.020 |
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(4.79) |
(.46) |
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(4.06±.50) |
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(2.54) typ. |
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DESCRIPTION
The PLCD5580 (Red), PLCD5581 (Yellow), PLCD5582 (High Efficiency Red), PLCD5583 (Green), and PLCD5584 (High Efficiency Green) are eight digit, 5x5 dot matrix, alphanumeric Programmable Displays. The 0.145 inch high digits are packaged in a rugged, high quality, optically transparent, standard 0.6 inch 28 pin plastic DIP.
The on-board CMOS has a built-in two page, 256 character ROM. Both pages are mask programmable for 256 custom characters. The first page of ROM of the standard product contains 128 characters including ASCII, selected European and Scientific symbols. The second page contains Katakana Japanese characters, more European characters, Avionics, and other graphic symbols.
The PLCD558X is designed for standard microprocessor interface techniques and is fully TTL compatible. The Clock I/O and Clock Select pins allow the user to synchronize multiple display modules.
2–131
Maximum Rating |
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DC Supply Voltage ........................................ |
–0.5 to +7.0 Vdc |
Input Voltage Levels Relative |
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to Ground............................................... |
–0.5 to VCC+0.5 Vdc |
Operating Temperature ................................. |
–40°C to +85°C |
Storage Temperature .................................... |
–40°C to +100°C |
Maximum Solder Temperature 0.063" |
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below Seating Plane, t<5 sec...................................... |
260°C |
Relative Humidity at 85°C................................................. |
85% |
Note: Maximum voltage is with no LEDs illuminated.
Enlarged Character Font
0.100
0.033 
(2.54)
(0.84)
typ. C0 C1 C2 C3 C4
R0
R1
0.145
R2 (3.68)
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R3 |
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0.011 |
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R4 |
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(0.28) |
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0.022 |
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typ. |
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(0.56) typ. |
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Dimensions in inches (mm)
Tolerance: .XXX=± .010 (.25)
Switching Specifications
(over operating temperature range and VCC=4.5 V).
Symbol |
Description |
Min. |
Units |
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Tbw |
Time Between Writes |
30 |
ns |
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Tacc(2) |
Display Access Time |
130 |
ns |
Tas |
Address Setup Time |
10 |
ns |
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Tces |
Chip Enable Hold Time |
0 |
ns |
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Tah |
Address Hold Time |
20 |
ns |
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Tceh |
Chip Enable Hold Time |
0 |
ns |
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Tw |
Write Active Time |
100 |
ns |
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Tds |
Data Valid Prior to |
50 |
ns |
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Rising Edge of Write |
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Tdh |
Data Hold Time |
20 |
ns |
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Trc(1) |
Reset Active Time |
300 |
ns |
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Tclr(3) |
Clear Cycle Time |
3 |
s |
1.Wait 300 ns min. after the reset function is turned off.
2.Tacc=Tas + Tw + Tah
3.The Clear Cycle Time may be shortened by writing a second Control Word with the Clear Bit disabled, 160 ns after the first control word that enabled the Clear Bit.
data |
wait |
data |
write control |
wait 130 ns |
write control |
word-clear bit |
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word-clear bit |
enabled |
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enabled |
The Flash RAM and Character RAM may not be accessed until the Clear Cycle is complete.
Write Cycle Timing Diagram
Tacc
Tas |
Tah |
FL, A3-A0 
see Notes
CE
see Notes
Tces |
Tceh |
WR
see Notes
Tw 
Tbw 
D7-D0 |
see Notes |
Tdh 
Tds
Notes
1.All input voltages are (VIL=0.8 V, VIH=2.0 V)
2.These wave forms are not edge triggered.
3.Tbw=Tas + Tah
PLCD5580/1/2/3/4
2–132
Optical Characteristics at 25°C
VCC=5.0 V at Full Brightness
Red PLCD5580
Description |
Symbol |
Min. |
Typ. |
Units |
Peak Luminous Intensity(1) |
IVpeak |
70 |
90 |
cd/dot |
Peak Wavelength |
λ(peak) |
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660 |
nm |
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Dominant Wavelength |
λ(d) |
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639 |
nm |
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Yellow PLCD5581 |
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Description |
Symbol |
Min. |
Typ. |
Units |
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Peak Luminous Intensity(1) |
IVpeak |
130 |
210 |
cd/dot |
Peak Wavelength |
λ(peak) |
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583 |
nm |
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Dominant Wavelength |
λ(d) |
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585 |
nm |
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High Efficiency Red PLCD5582 |
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Description |
Symbol |
Min. |
Typ. |
Units |
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Peak Luminous Intensity(1) |
IVpeak |
150 |
330 |
cd/dot |
Peak Wavelength |
λ(peak) |
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630 |
nm |
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Dominant Wavelength |
λ(d) |
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626 |
nm |
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Green PLCD5583 |
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Description |
Symbol |
Min. |
Typ. |
Units |
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Peak Luminous Intensity(1) |
IVpeak |
150 |
260 |
cd/dot |
Peak Wavelength |
λ(peak) |
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565 |
nm |
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Dominant Wavelength |
λ(d) |
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570 |
nm |
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High Efficiency Green PLCD5584 |
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Description |
Symbol |
Min. |
Typ. |
Units |
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Peak Luminous Intensity(1) |
IVpeak |
200 |
510 |
cd/dot |
Peak Wavelength |
λ(peak) |
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568 |
nm |
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Dominant Wavelength |
λ(d) |
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574 |
nm |
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Note
1. Peak luminous intensity is meaaured at TA=TJ=25°C. No time is allowed for the device to warm up prior to measurement.
PLCD5580/1/2/3/4
2–133
Electrical Characteristics at 25°C
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Limits |
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Parameters |
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Conditions |
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Min. |
Typ. |
Max. |
Units |
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VCC |
4.5 |
5.0 |
5.5 |
V |
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ICC Blank |
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0.5 |
1.0 |
mA |
VCC=5 V, VIN=5 V |
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I |
8 digits (1), 16 dots/character |
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240 |
290 |
mA |
V =5 V, “#” displayed in all |
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CC |
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CC |
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eight digits |
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IIP Current |
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11 |
18 |
µA |
VCC=5 V, VIN=0 V to VCC, |
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(with pull-up) |
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(WR, |
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CE, |
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FL, |
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RST, |
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ClkSel) |
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II Input leakage current |
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±1 |
µA |
VCC=5 V, VIN=0 V to VCC, |
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(without pull-up) |
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(Clk I/O, A0–A3, D0–D7) |
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VIH Input Voltage High |
2.0 |
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VCC |
V |
VCC=4.5 V to 5.5 V |
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+0.3 |
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VIL Input Voltage Low |
GND |
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0.8 |
V |
VCC=4.5 V to 5.5 V |
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–0.3 |
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VOL Output Voltage Low |
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0.4 |
V |
VCC=4.5 V to 5.5 V, |
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(Clock Pin) |
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IOL=1.6 mA |
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VOH Output Voltage High |
2.4 |
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V |
VCC=4.5 V to 5.5 V, |
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(Clock Pin) |
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IOH=40 µA |
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IOH Output Current High |
–0.9 |
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mA |
VCC=4.5 V, VOH=2.4 V |
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(Clock I/O) |
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IOL Output Current Low |
1.6 |
2 |
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mA |
VCC=4.5 V, VOL=0.4 V |
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(Clock I/O) |
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θJC Thermal Resistance, |
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25 |
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°C/W |
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Junction to Case |
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Fext External Clock, |
28 |
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81.14 |
KHz |
VCC=5.0 V, |
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CLKSEL=0 |
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Input Frequency(2) |
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Fosc Internal Clock, |
28 |
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81.14 |
KHz |
VCC=5.0 V, |
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CLKSEL=1 |
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Output Frequency(2) |
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Clock I/O Buss Loading |
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240 |
pF |
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Clock Out Rise Time |
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500 |
ns |
VCC=4.5 V, VOH=2.4 V |
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Clock Out Fall Time |
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500 |
ns |
VCC=4.5 V, VOL=0.4 V |
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FM, Digit Multiplex Frequency |
125 |
256 |
362.5 |
Hz |
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Blinking Rate |
0.98 |
2 |
2.83 |
Hz |
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Notes:
1.Average ICC measured at full brightness. Peak ICC=5⁄8 x IAVG ICC (# displayed).
2.Internal/external frequency duty factor is 50%.
PLCD5580/1/2/3/4
2–134
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