Data Sheet, Rev. 1.0, Mar. 2004
HYS64D32020[H/G]DL–5–C
HYS64D[32020/16000][H/G]DL–6–C
200-Pin Small Outline Dual-In-Line Memory Modules SO-DIMM
DDR SDRAM
Memory Products
N e v e r s t o p t h i n k i n g .
Edition 2004-03
Published by Infineon Technologies AG, St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004. All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Data Sheet, Rev. 1.0, Mar. 2004
HYS64D32020[H/G]DL–5–C
HYS64D[32020/16000][H/G]DL–6–C
200-Pin Small Outline Dual-In-Line Memory Modules SO-DIMM
DDR SDRAM
Memory Products
N e v e r s t o p t h i n k i n g .
HYS64D32020[H/G]DL–5–C,HYS64D[32020/16000][H/G]DL–6–C |
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Revision History: |
Rev. 1.0 |
2004-03 |
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Previous Version: |
Rev. 0.5 |
2003-11 |
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Page |
Subjects (major changes since last revision) |
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6,7 |
Added DDR400 |
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18 |
Updated Idd Currents and added DDR400 Idd Currents |
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24 |
Updated SPD Code Bytes 99 - 127 to FF and added SPD Codes for DDR400 |
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13,14 |
editorial changes |
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Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to:
techdoc.mp@infineon.com
Template: mp_a4_v2.0_2003-06-06.fm
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
Table of Contents |
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1 |
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 6 |
1.1 |
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
6 |
2 |
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
6 |
3 |
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
8 |
4 |
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
15 |
4.1 |
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
15 |
4.2 |
Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
17 |
4.3 |
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
19 |
5 |
SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
22 |
6 |
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
28 |
Data Sheet |
5 |
Rev. 1.0, 2004-03 |
200-Pin Small Outline Dual-In-Line Memory Modules |
HYS64D32020[H/G]DL–5–C |
SO-DIMM |
HYS64D[32020/16000][H/G]DL–6–C |
•Non-parity 200-Pin Small Outline Dual-In-Line Memory Modules
•One rank 16M ×64 and two ranks 32M ×64 organization
•JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM)
•Single +2.5 V (± 0.2 V) power supply
•Built with 256 Mbit DDR SDRAMs organised as ×16 in P–TSOPII–66–1 packages
•Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
•Auto Refresh (CBR) and Self Refresh
•All inputs and outputs SSTL_2 compatible
•Serial Presence Detect with E2PROM
•Jedec standard form factor: 67.60 mm × 31.75 mm × 2.4 / 3.80 mm
•Jedec standard reference layout Raw Cards A and C
•Gold plated contacts
Table 1 |
Performance |
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Part Number Speed Code |
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–5 |
–6 |
Unit |
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Speed Grade |
Component |
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DDR400B |
DDR333B |
— |
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Module |
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PC3200–3033 |
PC2700–2533 |
— |
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max. Clock Frequency |
@CL3 |
fCK3 |
200 |
166 |
MHz |
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@CL2.5 |
fCK2.5 |
166 |
166 |
MHz |
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@CL2 |
fCK2 |
133 |
133 |
MHz |
The HYS64D32020[H/G]DL–5–C and HYS64D[32020/16000][H/G]DL–6–C are industry standard 200-Pin Small Outline Dual-In-Line Memory Modules (SO-DIMMs) organized as 32M × 64 and 16M × 64. The memory array is designed with Double Data Rate Synchronous DRAMs (DDR SDRAM). A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
Data Sheet |
6 |
Rev. 1.0, 2004-03 |
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
Description
Table 2 |
Ordering Information |
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Type |
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Compliance Code |
Description |
SDRAM |
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Technology |
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PC3200 (CL=3.0) |
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HYS64D32020GDL–5–C |
PC3200S–3033–1–A1 |
two ranks 256 MB SO-DIMM |
256 MBit (×16) |
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PC2700 (CL=2.5) |
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HYS64D16000GDL–6–C |
PC2700S–2533–0–C1 |
one rank 128 MB SO-DIMM |
256 MBit (×16) |
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HYS64D32020GDL–6–C |
PC2700S–2533–0–A1 |
two ranks 256 MB SO-DIMM |
256 MBit (×16) |
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PC3200 (CL=3.0) |
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HYS64D32020HDL–5–C |
PC3200S–3033–1–A1 |
two ranks 256 MB SO-DIMM |
256 MBit (×16) |
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PC2700 (CL=2.5) |
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HYS64D16000HDL–6–C |
PC2700S–2533–0–C1 |
one rank 128 MB SO-DIMM |
256 MBit (×16) |
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HYS64D32020HDL–6–C |
PC2700S–2533–0–A1 |
two ranks 256 MB SO-DIMM |
256 MBit (×16) |
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1.All part numbers end with a place code designating the silicon-die revision. Reference information available on request. Example: HYS64D32020GDL-6-B, indicating rev. B dies are used for SDRAM components.
2.The Compliance Code is printed on the module labels describing the speed sort (for example “PC2700”), the latencies and SPD code definition (for example “2033–0” means CAS latency of 2.0 clocks, RCD1) latency of 3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card used for this module.
1) RCD: Row-Column-Delay
Data Sheet |
7 |
Rev. 1.0, 2004-03 |
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
Pin Configuration
3 Pin Configuration
The pin configuration of the Unbuffered Small Outline DDR SDRAM DIMM is listed by function in Table 3 (184 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 4 and Table 5 respectively. The pin numbering is depicted in
Figure 1.
Table 3 |
Pin Configuration of SO-DIMM |
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Pin# |
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Name |
Pin |
Buffer |
Function |
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Type |
Type |
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Clock Signals |
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35 |
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CK0 |
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I |
SSTL |
Clock Signal |
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160 |
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CK1 |
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I |
SSTL |
Clock Signal |
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89 |
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CK2 |
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I |
SSTL |
Clock Signal |
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Note: ECC type |
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module |
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NC |
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NC |
– |
Note: non-ECC type |
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module |
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37 |
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I |
SSTL |
Complement Clock |
CK0 |
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158 |
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I |
SSTL |
Complement Clock |
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CK1 |
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91 |
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I |
SSTL |
Complement Clock |
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CK2 |
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Note: ECC type |
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module |
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NC |
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NC |
– |
Note: non-ECC type |
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module |
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96 |
CKE0 |
I |
SSTL |
Clock Enable Rank 0 |
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95 |
CKE1 |
I |
SSTL |
Clock Enable Rank 1 |
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Note: 2-rank module |
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NC |
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NC |
– |
Note: 1-rank module |
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Control Signals |
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121 |
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S0 |
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I |
SSTL |
Chip Select Rank 0 |
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122 |
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I |
SSTL |
Chip Select Rank 1 |
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S1 |
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Note: 2-ranks module |
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NC |
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NC |
– |
Note: 1-rank module |
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118 |
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I |
SSTL |
Row Address |
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RAS |
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Strobe |
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120 |
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I |
SSTL |
Column Address |
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CAS |
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Strobe |
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119 |
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I |
SSTL |
Write Enable |
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WE |
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Address Signals |
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117 |
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BA0 |
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I |
SSTL |
Bank Address Bus |
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1:0 |
116 |
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BA1 |
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I |
SSTL |
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Table 3 |
Pin Configuration of SO-DIMM (cont’d) |
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Pin# |
Name |
Pin |
Buffer |
Function |
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Type |
Type |
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112 |
A0 |
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I |
SSTL |
Address Bus 11:0 |
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111 |
A1 |
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I |
SSTL |
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110 |
A2 |
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I |
SSTL |
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109 |
A3 |
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I |
SSTL |
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108 |
A4 |
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I |
SSTL |
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107 |
A5 |
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I |
SSTL |
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106 |
A6 |
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I |
SSTL |
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105 |
A7 |
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I |
SSTL |
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102 |
A8 |
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I |
SSTL |
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101 |
A9 |
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I |
SSTL |
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115 |
A10 |
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I |
SSTL |
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AP |
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I |
SSTL |
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100 |
A11 |
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I |
SSTL |
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99 |
A12 |
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I |
SSTL |
Address Signal 12 |
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Note: Module based |
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on 256 Mbit or |
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larger dies |
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NC |
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NC |
– |
Note: 128 Mbit based |
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module |
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123 |
A13 |
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I |
SSTL |
Address Signal 13 |
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Note: 1 Gbit based |
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module |
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NC |
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NC |
– |
Note: Module based |
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on 512 Mbit or |
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smaller dies |
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Data Signals |
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5 |
DQ0 |
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I/O |
SSTL |
Data Bus 63:0 |
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7 |
DQ1 |
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I/O |
SSTL |
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13 |
DQ2 |
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I/O |
SSTL |
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17 |
DQ3 |
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I/O |
SSTL |
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6 |
DQ4 |
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I/O |
SSTL |
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8 |
DQ5 |
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I/O |
SSTL |
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14 |
DQ6 |
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I/O |
SSTL |
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18 |
DQ7 |
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I/O |
SSTL |
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19 |
DQ8 |
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I/O |
SSTL |
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23 |
DQ9 |
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I/O |
SSTL |
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29 |
DQ10 |
I/O |
SSTL |
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31 |
DQ11 |
I/O |
SSTL |
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20 |
DQ12 |
I/O |
SSTL |
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24 |
DQ13 |
I/O |
SSTL |
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Data Sheet |
8 |
Rev. 1.0, 2004-03 |
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
Table 3 |
Pin Configuration of SO-DIMM (cont’d) |
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Pin# |
Name |
Pin |
Buffer |
Function |
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Type |
Type |
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30 |
DQ14 |
I/O |
SSTL |
Data Bus 63:0 |
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32 |
DQ15 |
I/O |
SSTL |
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41 |
DQ16 |
I/O |
SSTL |
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43 |
DQ17 |
I/O |
SSTL |
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49 |
DQ18 |
I/O |
SSTL |
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53 |
DQ19 |
I/O |
SSTL |
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42 |
DQ20 |
I/O |
SSTL |
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44 |
DQ21 |
I/O |
SSTL |
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50 |
DQ22 |
I/O |
SSTL |
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54 |
DQ23 |
I/O |
SSTL |
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55 |
DQ24 |
I/O |
SSTL |
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59 |
DQ25 |
I/O |
SSTL |
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65 |
DQ26 |
I/O |
SSTL |
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67 |
DQ27 |
I/O |
SSTL |
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56 |
DQ28 |
I/O |
SSTL |
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60 |
DQ29 |
I/O |
SSTL |
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66 |
DQ30 |
I/O |
SSTL |
|
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68 |
DQ31 |
I/O |
SSTL |
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127 |
DQ32 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
129 |
DQ33 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
135 |
DQ34 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
139 |
DQ35 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
128 |
DQ36 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
130 |
DQ37 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
136 |
DQ38 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
140 |
DQ39 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
141 |
DQ40 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
145 |
DQ41 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
151 |
DQ42 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
153 |
DQ43 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
142 |
DQ44 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
146 |
DQ45 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
152 |
DQ46 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
154 |
DQ47 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
163 |
DQ48 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
165 |
DQ49 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
171 |
DQ50 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
175 |
DQ51 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
164 |
DQ52 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
166 |
DQ53 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
|
|
|
|
|
Pin Configuration |
Table 3 |
Pin Configuration of SO-DIMM (cont’d) |
||||
|
|
|
|
|
|
Pin# |
Name |
Pin |
Buffer |
Function |
|
|
|
|
Type |
Type |
|
|
|
|
|
|
|
172 |
DQ54 |
I/O |
SSTL |
Data Bus 63:0 |
|
|
|
|
|
|
|
176 |
DQ55 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
177 |
DQ56 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
181 |
DQ57 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
187 |
DQ58 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
189 |
DQ59 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
178 |
DQ60 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
182 |
DQ61 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
188 |
DQ62 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
190 |
DQ63 |
I/O |
SSTL |
|
|
|
|
|
|
|
|
71 |
CB0 |
|
I/O |
SSTL |
Check Bit 0 |
|
|
|
|
|
Note: ECC type |
|
|
|
|
|
module |
|
|
|
|
|
|
|
NC |
|
NC |
– |
Note: Non-ECC |
|
|
|
|
|
module |
|
|
|
|
|
|
73 |
CB1 |
|
I/O |
SSTL |
Check Bit 1 |
|
|
|
|
|
Note: ECC type |
|
|
|
|
|
module |
|
|
|
|
|
|
|
NC |
|
NC |
– |
Note: Non-ECC |
|
|
|
|
|
module |
|
|
|
|
|
|
79 |
CB2 |
|
I/O |
SSTL |
Check Bit 2 |
|
|
|
|
|
Note: ECC type |
|
|
|
|
|
module |
|
|
|
|
|
|
|
NC |
|
NC |
– |
Note: Non-ECC |
|
|
|
|
|
module |
|
|
|
|
|
|
83 |
CB3 |
|
I/O |
SSTL |
Check Bit 3 |
|
|
|
|
|
Note: ECC type |
|
|
|
|
|
module |
|
|
|
|
|
|
|
NC |
|
NC |
– |
Note: Non-ECC |
|
|
|
|
|
module |
|
|
|
|
|
|
72 |
CB4 |
|
I/O |
SSTL |
Check Bit 4 |
|
|
|
|
|
Note: ECC type |
|
|
|
|
|
module |
|
|
|
|
|
|
|
NC |
|
NC |
– |
Note: Non-ECC |
|
|
|
|
|
module |
|
|
|
|
|
|
74 |
CB5 |
|
I/O |
SSTL |
Check Bit 5 |
|
|
|
|
|
Note: ECC type |
|
|
|
|
|
module |
|
|
|
|
|
|
|
NC |
|
NC |
– |
Note: Non-ECC |
|
|
|
|
|
module |
|
|
|
|
|
|
Data Sheet |
9 |
Rev. 1.0, 2004-03 |