HYB39S256160DC-6 |
Data Sheet, Rev. 1.02, Feb. 2004 |
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HYB39S256400D[C/T](L)
HYB39S256800D[C/T](L)
HYB39S256160D[C/T](L)
256-MBit Synchronous DRAM
SDRAM
Memory Products
N e v e r s t o p t h i n k i n g .
Edition 2004-02
Published by Infineon Technologies AG, St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004. All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Data Sheet, Rev. 1.02, Feb. 2004
Data Sheet, Rev. 1.02, Feb. 2004
HYB39S256400D[C/T](L)
HYB39S256800D[C/T](L)
HYB39S256160D[C/T](L)
256-MBit Synchronous DRAM
SDRAM
MemoryProducts
N e v e r s t o p t h i n k i n g .
HYB39S256[40/80/16]0D[C/T](L) |
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Revision History: |
Rev. 1.02 |
2004-02 |
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Page |
Subjects (major changes since last revision) |
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17 |
Corrected Mode Register Definition in chapter 3 |
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all |
Various layout and editorial changes |
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Previous Version: |
Rev. 1.01 |
2004-01 |
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all |
Various layout and editorial changes |
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Previous Version: |
Rev. 1.0 |
2002-06 |
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We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to:
techdoc.mp@infineon.com
Template: mp_a4_v2.0_2003-06-06.fm
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HYB39S256[40/80/16]0D[C/T](L) |
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256-MBit Synchronous DRAM |
Table of Contents |
Page |
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1 |
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 |
1.1 |
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 |
1.2 |
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 |
2 |
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 |
2.1 |
Signal Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 |
2.2 |
Package P–TSOPII–54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 |
2.3 |
Package P–TFBGA–54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 |
2.4 |
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 |
3 |
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 |
3.1 |
Operation Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 |
3.2 |
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 |
3.3 |
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 |
3.3.1 |
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 |
3.4 |
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 |
3.5 |
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 |
3.5.1 |
Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 |
3.5.2 |
DQM Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 |
3.5.3 |
Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 |
3.5.4 |
Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 |
4 |
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 |
4.1 |
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 |
4.2 |
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 |
5 |
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 |
Data Sheet |
5 |
Rev. 1.02, 2004-02 |
HYB39S256[40/80/16]0D[C/T](L)
256-MBit Synchronous DRAM
Overview
1 Overview
1.1Features
•Fully Synchronous to Positive Clock Edge
•0 to 70 °C operating temperature
•Four Banks controlled by BA0 & BA1
•Programmable CAS Latency: 2 & 3
•Programmable Wrap Sequence: Sequential or Interleave
•Programmable Burst Length: 1, 2, 4, 8 and full page
•Multiple Burst Read with Single Write Operation
•Automatic and Controlled Precharge Command
•Data Mask for Read / Write control (x4, x8)
•Data Mask for byte control (x16)
•Auto Refresh (CBR) and Self Refresh
•Power Down and Clock Suspend Mode
•8192 refresh cycles / 64 ms (7,8 µs)
•Random Column Address every CLK (1-N Rule)
•Single 3.3 V ± 0.3 V Power Supply
•LVTTL Interface versions
•Plastic Packages: P–TSOPII–54 400mil width (x4, x8, x16)
•Chipsize Packages: P–TFBGA–54 (12 mm x 8 mm)
Table 1 |
Performance |
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Part Number Speed Code |
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–6 |
–7 |
-7.5 |
–8 |
Unit |
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Speed Grade |
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PC166 3–3–3 |
PC133 2–2–2 |
PC133 3–3–3 |
PC100 2–2–2 |
— |
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max. Clock Frequency |
@CL3 |
fCK3 |
166 |
143 |
133 |
125 |
MHz |
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tCK3 |
6 |
7 |
7.5 |
8 |
ns |
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tAC3 |
5 |
5.4 |
5.4 |
6 |
ns |
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@CL2 |
tCK2 |
7.5 |
7.5 |
10 |
10 |
ns |
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tAC2 |
5.4 |
5.4 |
6 |
6 |
ns |
1.2Description
The HYB39S256[40/80/16]0D[C/T](L) are four bank Synchronous DRAM’s organized as 4 banks x 16 MBit x4, 4 banks x 8 MBit x8 and 4 banks x 4 Mbit x16 respectively. These synchronous devices achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with INFINEON’s advanced 0.14 µm 256-MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single 3.3 V ± 0.3 V power supply. All 256-Mbit components are available in P–TSOPII–54 and P–TFBGA–54 packages.
Data Sheet |
6 |
Rev. 1.02, 2004-02 |
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10072003-13LE-FGQQ |
HYB39S256[40/80/16]0D[C/T](L)
256-MBit Synchronous DRAM
Overview
Table 2 |
Ordering Information |
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Type |
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Speed Grade |
Package |
Description |
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HYB 39S256400DT-6 |
PC166-333-520 |
P-TSOP-54-2 (400mil) |
166MHz 4B x 16M x 4 SDRAM |
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HYB 39S256400DT-7 |
PC133-222-520 |
P-TSOP-54-2 (400mil) |
143MHz 4B x 16M x 4 SDRAM |
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HYB 39S256400DT-7.5 |
PC133-333-520 |
P-TSOP-54-2 (400mil) |
133MHz 4B x 16M x 4 SDRAM |
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HYB 39S256400DT-8 |
PC100-222-620 |
P-TSOP-54-2 (400mil) |
125MHz 4B x 16M x 4 SDRAM |
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HYB 39S256800DT-6 |
PC166-333-520 |
P-TSOP-54-2 (400mil) |
166MHz 4B x 8M x 8 SDRAM |
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HYB 39S256800DT-7 |
PC133-222-520 |
P-TSOP-54-2 (400mil) |
143MHz 4B x 8M x 8 SDRAM |
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HYB 39S256800DT-7.5 |
PC133-333-520 |
P-TSOP-54-2 (400mil) |
133MHz 4B x 8M x 8 SDRAM |
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HYB 39S256800DT-8 |
PC100-222-620 |
P-TSOP-54-2 (400mil) |
125MHz 4B x 8M x 8 SDRAM |
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HYB 39S256160DT-6 |
PC166-333-520 |
P-TSOP-54-2 (400mil) |
166MHz 4B x 4M x 16 SDRAM |
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HYB 39S256160DT-7 |
PC133-222-520 |
P-TSOP-54-2 (400mil) |
143MHz 4B x 4M x 16 SDRAM |
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HYB 39S256160DT-7.5 |
PC133-333-520 |
P-TSOP-54-2 (400mil) |
133MHz 4B x 4M x 16 SDRAM |
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HYB 39S256160DT-8 |
PC100-222-620 |
P-TSOP-54-2 (400mil) |
125MHz 4B x 4M x 16 SDRAM |
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HYB39S256400DTL-x |
– |
P-TSOP-54-2 (400mil) |
4B x 16M x 4 SDRAM Low Power |
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Versions (on request) |
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HYB39S256800DTL-x |
– |
P-TSOP-54-2 (400mil) |
4B x 8M x 8 SDRAM Low Power |
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Versions (on request) |
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HYB39S256160DTL-x |
– |
P-TSOP-54-2 (400mil) |
4B x 4M x 16 SDRAM Low Power |
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Versions (on request) |
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HYB39S256xx0DC(L)-x |
– |
P-TFBGA-54 |
(on request) |
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Data Sheet |
7 |
Rev. 1.02, 2004-02 |
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10072003-13LE-FGQQ |
HYB39S256[40/80/16]0D[C/T](L)
256-MBit Synchronous DRAM
Pin Configuration
2 Pin Configuration
2.1Signal Pin Description
Table 3 |
Signal Pin Description |
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Pin |
Type |
Signal |
Polarity |
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Function |
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CLK |
Input |
Pulse |
Positive |
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Clock Input |
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Edge |
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The system clock input. All of the SDRAM inputs are sampled on the rising |
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edge of the clock. |
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CKE |
Input |
Level |
Active |
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Clock Enable |
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High |
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Activates the CLK signal when high and deactivates the CLK signal when |
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low, thereby initiating either the Power Down mode, Suspend mode, or the |
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Self Refresh mode. |
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Input |
Pulse |
Active |
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Chip Select |
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CS |
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Low |
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CS |
enables the command decoder when low and disables the command |
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decoder when high. When the command decoder is disabled, new |
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commands are ignored but previous operations continue. |
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Input |
Pulse |
Active |
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Command Signals |
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RAS |
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CAS |
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Low |
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When sampled at the positive rising edge of the clock, |
CAS, |
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RAS, |
and |
WE |
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WE |
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define the command to be executed by the SDRAM. |
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A0 - A12 |
Input |
Level |
– |
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Address Inputs |
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During a Bank Activate command cycle, A0-A12 define the row address |
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(RA0-RA12) when sampled at the rising clock edge. |
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During a Read or Write command cycle, A0-An define the column address |
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(CA0-CAn) when sampled at the rising clock edge. CAn depends upon the |
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SDRAM organization: |
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64M x4 SDRAM CAn = CA9, CA11 (Page Length = 2048 bits) |
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32M x8 SDRAM CAn = CA9 (Page Length = 1024 bits) |
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16M x16 SDRAM CAn = CA8 (Page Length = 512 bits) |
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In addition to the column address, A10 (= AP) is used to invoke the |
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autoprecharge operation at the end of the burst read or write cycle. If A10 |
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is high, autoprecharge is selected and BA0, BA1 defines the bank to be |
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precharged. If A10 is low, autoprecharge is disabled. |
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During a Precharge command cycle, A10 (= AP) is used in conjunction |
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with BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all |
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four banks will be precharged regardless of the state of BA0 and BA1. If |
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A10 is low, then BA0 and BA1 are used to define which bank to precharge. |
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BA0, BA1 |
Input |
Level |
– |
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Bank Select |
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Bank Select Inputs. Bank address inputs selects which of the four banks a |
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command applies to. |
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DQx |
Input |
Level |
– |
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Data Input/Output |
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Output |
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Data Input/Output pins operate in the same manner as on EDO or FPM |
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DRAMs. |
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DQM |
Input |
Pulse |
Active |
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Data Mask |
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LDQM |
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High |
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The Data Input/Output mask places the DQ buffers in a high impedance |
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UDQM |
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state when sampled high. In Read mode, DQM has a latency of two clock |
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cycles and controls the output buffers like an output enable. In Write mode, |
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DQM has a latency of zero and operates as a word mask by allowing input |
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data to be written if it is low but blocks the write operation if DQM is high. |
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One DQM input is present in x4 and x8 SDRAMs, LDQM and UDQM |
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controls the lower and upper bytes in x16 SDRAMs. |
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Data Sheet |
8 |
Rev. 1.02, 2004-02 |
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10072003-13LE-FGQQ |
HYB39S256[40/80/16]0D[C/T](L)
256-MBit Synchronous DRAM
Pin Configuration
Table 3 |
Signal Pin Description |
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Pin |
Type |
Signal |
Polarity |
Function |
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VDD VSS |
Supply |
– |
– |
Power and Ground |
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Power and ground for the input buffers and the core logic (3.3 V) |
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VDDQ VSSQ |
Supply |
– |
– |
Power and Ground for DQs |
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Isolated power supply and ground for the output buffers to provide |
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improved noise immunity. |
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NC |
– |
– |
– |
Not Connected |
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No internal electrical connection is present. |
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2.2Package P–TSOPII–54
16 M x 16
32 M x 8
64 M x 4
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VDD |
VDD |
VDD |
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1 |
54 |
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VSS |
VSS |
VSS |
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DQ0 |
DQ0 |
N.C. |
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2 |
53 |
|
N.C. |
DQ7 |
DQ15 |
||
VDDQ |
VDDQ |
VDDQ |
|
3 |
52 |
|
VSSQ |
VSSQ |
VSSQ |
||
|
|
||||||||||
|
|
||||||||||
DQ1 |
N.C. |
N.C. |
|
4 |
51 |
|
N.C. |
N.C. |
DQ14 |
||
DQ2 |
DQ1 |
DQ0 |
|
5 |
50 |
|
DQ3 |
DQ6 |
DQ13 |
||
|
|
||||||||||
VSSQ |
VSSQ |
VSSQ |
|
6 |
49 |
|
VDDQ |
VDDQ |
VDDQ |
||
|
|
||||||||||
|
|
||||||||||
DQ3 |
N.C. |
N.C. |
|
7 |
48 |
|
N.C. |
N.C. |
DQ12 |
||
DQ4 |
DQ2 |
N.C. |
|
8 |
47 |
|
N.C. |
DQ5 |
DQ11 |
||
|
|
||||||||||
VDDQ |
VDDQ |
VDDQ |
|
9 |
46 |
|
VSSQ |
VSSQ |
VSSQ |
||
|
|
||||||||||
|
|
||||||||||
DQ5 |
N.C. |
N.C. |
|
10 |
45 |
|
N.C. |
N.C. |
DQ10 |
||
DQ6 |
DQ3 |
DQ1 |
|
11 |
44 |
|
DQ2 |
DQ4 |
DQ9 |
||
|
|
||||||||||
VSSQ |
VSSQ |
VSSQ |
|
12 |
43 |
|
VDDQ |
VDDQ |
VDDQ |
||
|
|
||||||||||
|
|
||||||||||
DQ7 |
N.C. |
N.C. |
|
13 |
42 |
|
N.C. |
N.C. |
DQ8 |
||
|
|
||||||||||
VDD |
VDD |
VDD |
|
14 |
41 |
|
VSS |
VSS |
VSS |
||
|
|
||||||||||
|
|
||||||||||
LDQM |
N.C. |
N.C. |
|
15 |
40 |
|
N.C. |
N.C. |
N.C. |
||
WE |
WE |
WE |
|
16 |
39 |
|
DQM |
DQM |
UDQM |
||
|
|
||||||||||
CAS |
CAS |
CAS |
|
17 |
38 |
|
CLK |
CLK |
CLK |
||
|
|
||||||||||
RAS |
RAS |
RAS |
|
18 |
37 |
|
CKE |
CKE |
CKE |
||
|
|
||||||||||
CS |
CS |
CS |
|
19 |
36 |
|
A12 |
A12 |
A12 |
||
|
|
||||||||||
BA0 |
BA0 |
BA0 |
|
20 |
35 |
|
A11 |
A11 |
A11 |
||
|
|
||||||||||
BA1 |
BA1 |
BA1 |
|
21 |
34 |
|
A9 |
A9 |
A9 |
||
|
|
||||||||||
A10/AP |
A10/AP |
A10/AP |
|
22 |
33 |
|
A8 |
A8 |
A8 |
||
|
|
||||||||||
A0 |
A0 |
A0 |
|
23 |
32 |
|
A7 |
A7 |
A7 |
||
|
|
||||||||||
A1 |
A1 |
A1 |
|
24 |
31 |
|
A6 |
A6 |
A6 |
||
|
|
||||||||||
A2 |
A2 |
A2 |
|
25 |
30 |
|
A5 |
A5 |
A5 |
||
|
|
||||||||||
A3 |
A3 |
A3 |
|
26 |
29 |
|
A4 |
A4 |
A4 |
||
|
|
||||||||||
VDD |
VDD |
VDD |
|
27 |
28 |
|
VSS |
VSS |
VSS |
||
|
|
||||||||||
|
|
TSOPII-54 (400 mil x 875 mil, 0.8 mm pitch)
SPP04126
Figure 1 Pinouts P–TSOPII–54
Data Sheet |
9 |
Rev. 1.02, 2004-02 |
|
|
10072003-13LE-FGQQ |