Data Sheet, V2.0, May 2001
C164CI/SI
C164CL/SL
16-Bit Single-Chip Microcontroller
Microcontrollers
N e v e r s t o p t h i n k i n g .
Edition 2001-05
Published by Infineon Technologies AG, St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 2001. All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Data Sheet, V2.0, May 2001
C164CI/SI
C164CL/SL
16-Bit Single-Chip Microcontroller
Microcontrollers
N e v e r s t o p t h i n k i n g .
C164CI |
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Revision History: |
2001-05 |
V2.0 |
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Previous Version: |
1999-08 |
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1998-02 |
(Preliminary) |
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04.97 |
(Advance Information) |
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Subjects (major changes since last revision)1) |
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All |
Converted to Infineon layout |
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1 |
Operating frequency up to 25 MHz |
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1 et al. |
References to Flash removed |
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1 |
Timer Unit with three timers |
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1, 12, 73 |
On-chip XRAM described |
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2 |
Derivative table updated |
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10 |
Supply voltage is 5 V |
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21 |
Functionality of reduced CAPCOM6 corrected |
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22f |
Timer description improved |
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29, 30 |
Sections “Oscillator Watchdog” and “Power Management” added |
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37 |
POCON reset values adjusted |
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41 to 73 |
Parameter section reworked |
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1)These changes refer to the last two versions. Version 1998-02 covers OTP and ROM derivatives, while version 1999-08 ist the most recent one.
Controller Area Network (CAN): License of Robert Bosch GmbH
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to:
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16-Bit Single-Chip Microcontroller |
C164CI |
C166 Family |
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C164CI/SI, C164CL/SL
•High Performance 16-bit CPU with 4-Stage Pipeline
–80 ns Instruction Cycle Time at 25 MHz CPU Clock
–400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit)
–Enhanced Boolean Bit Manipulation Facilities
–Additional Instructions to Support HLL and Operating Systems
–Register-Based Design with Multiple Variable Register Banks
–Single-Cycle Context Switching Support
–16 MBytes Total Linear Address Space for Code and Data
–1024 Bytes On-Chip Special Function Register Area
•16-Priority-Level Interrupt System with 32 Sources, Sample-Rate down to 40 ns
•8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC)
•Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5), via prescaler or via direct clock input
•On-Chip Memory Modules
–2 KBytes On-Chip Internal RAM (IRAM)
–2 KBytes On-Chip Extension RAM (XRAM)
–up to 64 KBytes On-Chip Program Mask ROM or OTP Memory
•On-Chip Peripheral Modules
–8-Channel 10-bit A/D Converter with Programmable Conversion Time down to 7.8 µs
–8-Channel General Purpose Capture/Compare Unit (CAPCOM2)
–Capture/Compare Unit for flexible PWM Signal Generation (CAPCOM6) (3/6 Capture/Compare Channels and 1 Compare Channel)
–Multi-Functional General Purpose Timer Unit with 3 Timers
–Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
–On-Chip CAN Interface (Rev. 2.0B active) with 15 Message Objects (Full CAN/Basic CAN)
–On-Chip Real Time Clock
•Up to 4 MBytes External Address Space for Code and Data
–Programmable External Bus Characteristics for Different Address Ranges
–Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit Data Bus Width
–Four Optional Programmable Chip-Select Signals
•Idle, Sleep, and Power Down Modes with Flexible Power Management
•Programmable Watchdog Timer and Oscillator Watchdog
•Up to 59 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis
Data Sheet |
1 |
V2.0, 2001-05 |
C164CI/SI
C164CL/SL
•Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards
•On-Chip Bootstrap Loader
•80-Pin MQFP Package, 0.65 mm pitch
This document describes several derivatives of the C164 group. Table 1 enumerates these derivatives and summarizes the differences. As this document refers to all of these derivatives, some descriptions may not apply to a specific product.
Table 1 |
C164CI Derivative Synopsis |
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Derivative1) |
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Program |
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CAPCOM6 |
CAN Interf. |
Operating |
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Memory |
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Frequency |
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SAK-C164CI-8R[25]M |
64 |
KByte ROM |
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Full function |
CAN1 |
20 |
MHz, |
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SAF-C164CI-8R[25]M |
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[25 MHz] |
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SAK-C164SI-8R[25]M |
64 |
KByte ROM |
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Full function |
--- |
20 |
MHz, |
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SAF-C164SI-8R[25]M |
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[25 MHz] |
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SAK-C164CL-8R[25]M |
64 |
KByte ROM |
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Reduced fct. |
CAN1 |
20 |
MHz, |
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SAF-C164CL-8R[25]M |
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[25 MHz] |
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SAK-C164SL-8R[25]M |
64 |
KByte ROM |
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Reduced fct. |
--- |
20 |
MHz, |
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SAF-C164SL-8R[25]M |
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[25 MHz] |
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SAK-C164CL-6R[25]M |
48 |
KByte ROM |
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Reduced fct. |
CAN1 |
20 |
MHz, |
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SAF-C164CL-6R[25]M |
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[25 MHz] |
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SAK-C164SL-6R[25]M |
48 |
KByte ROM |
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Reduced fct. |
--- |
20 |
MHz, |
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SAF-C164SL-6R[25]M |
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[25 MHz] |
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SAK-C164CI-L[25]M |
--- |
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Full function |
CAN1 |
20 |
MHz, |
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SAF-C164CI-L[25]M |
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[25 MHz] |
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SAK-C164CI-8EM |
64 |
KByte OTP |
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Full function |
CAN1 |
20 |
MHz |
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SAF-C164CI-8EM |
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1)This Data Sheet is valid for ROM(less) devices starting with and including design step AB, and for OTP devices starting with and including design step DA.
For simplicity all versions are referred to by the term C164CI throughout this document.
Data Sheet |
2 |
V2.0, 2001-05 |
C164CI/SI
C164CL/SL
The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies:
•the derivative itself, i.e. its function set, the temperature range, and the supply voltage
•the package and the type of delivery.
For the available ordering codes for the C164CI please refer to the “Product Catalog Microcontrollers”, which summarizes all available microcontroller variants.
Note: The ordering codes for Mask-ROM versions are defined for each product after verification of the respective ROM code.
The C164CI derivatives of the Infineon C166 Family of full featured single-chip CMOS microcontrollers are especially suited for cost sensitive applications. They combine high CPU performance (up to 12.5 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. They also provide clock generation via PLL and various on-chip memory modules such as program ROM or OTP, internal RAM, and extension RAM.
VAREF VAGND VDD VSS
Port 0
XTAL1
16 Bit
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XTAL2 |
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Port 1 |
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16 Bit |
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RSTIN |
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Port 3 |
RSTOUT |
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C164CI |
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9 Bit |
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NMI |
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Port 4 |
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EA |
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6 Bit |
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ALE |
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Port 8 |
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4 Bit |
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RD |
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Port 5 |
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WR/WRL |
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8 Bit |
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MCL04869 |
Figure 1 Logic Symbol
Data Sheet |
3 |
V2.0, 2001-05 |
C164CI/SI
C164CL/SL
Pin Configuration
(top view)
AGND
V
80
VAREF 1
P5.4/AN4/T2EUD 2 P5.5/AN5/T4EUD 3 P5.6/AN6/T2IN 4 P5.7/AN7/T4IN 5
VSS 6
VDD 7
P3.4/T3EUD 8 P3.6/T3IN 9
P3.8/MRST 10
P3.9/MTSR 11
P3.10/TxD0 12
P3.11/RxD0 13 P3.12/BHE/WRH 14 P3.13/SCLK 15 P3.15/CLKOUT/FOUT 16 P4.0/A16/CS3 17 P4.1/A17/CS2 18
P4.2/A18/CS1 19
VSS 20
21
DD
V
P5.3/AN3 |
P5.2/AN2 |
P5.1/AN1 |
P5.0/AN0 |
P8.3/CC19IO/* |
P8.2/CC18IO/* |
P8.1/CC17IO/* |
P8.0/CC16IO/* |
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NMI |
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RSTOUT |
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RSTIN |
P1H.7/A15/CC27IO |
P1H.6/A14/CC26IO |
P1H.5/A13/CC25IO |
P1H.4/A12/CC24IO |
P1H.3/A11/EXIN/T7IN |
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P1H.2/A10/CC6POS2/EX2IN |
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79 |
78 |
77 |
76 |
75 |
74 |
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72 |
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67 |
66 |
65 |
64 |
63 |
C164CI
22 |
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25 |
26 |
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28 |
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31 |
32 |
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34 |
35 |
36 |
37 |
38 |
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P4.3/A19/CS0 |
*/P4.5/A20 |
*/P4.6/A21 |
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WR/WRL |
ALE |
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Vpp/EA |
P0L.0/AD0 |
P0L.1/AD1 |
P0L.2/AD2 |
P0L.3/AD3 |
P0L.4/AD4 |
P0L.5/AD5 |
P0L.6/AD6 |
P0L.7/AD7 |
P0H.0/AD8 |
P0H.1/AD9 |
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62 P1H.1/A9/CC6POS1/EX1IN
P0H.2/AD10 39
DD
V
61
60 VSS
59 P1H.0/A8/CC6POS0/EX0IN
58 P1L.7/A7/CTRAP
57 P1L.6/A6/COUT63
56 VSS
55 XTAL1
54 XTAL2
53 VDD
52 P1L.5/A5/COUT62
51 P1L.4/A4/CC62
50 P1L.3/A3/COUT61
49 P1L.2/A2/CC61
48 P1L.1/A1/COUT60
47 P1L.0/A0/CC60
46 P0H.7/AD15
45 P0H.6/AD14
44 P0H.5/AD13
43 P0H.4/AD12
42 P0H.3/AD11
41 VSS
40
DD
V
MCP04870
Figure 2
*) The marked pins of Port 4 and Port 8 can have CAN interface lines assigned to them. Table 2 on the pages below lists the possible assignments.
The marked input signals are available only in devices with a full-function CAPCOM6. They are not available in devices with a reduced-function CAPCOM6.
Data Sheet |
4 |
V2.0, 2001-05 |
C164CI/SI
C164CL/SL
Table 2 |
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Pin Definitions and Functions |
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Symbol |
Pin |
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Input |
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Function |
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No. |
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Outp. |
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P5 |
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Port 5 is an 8-bit input-only port with Schmitt-Trigger charact. |
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The pins of Port 5 also serve as analog input channels for the |
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A/D converter, or they serve as timer inputs: |
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P5.0 |
76 |
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AN0 |
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P5.1 |
77 |
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AN1 |
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P5.2 |
78 |
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AN2 |
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P5.3 |
79 |
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AN3 |
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P5.4 |
2 |
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AN4, |
T2EUD |
GPT1 Timer T2 Ext. Up/Down Ctrl. Inp. |
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P5.5 |
3 |
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AN5, |
T4EUD |
GPT1 Timer T4 Ext. Up/Down Ctrl. Inp. |
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P5.6 |
4 |
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AN6, |
T2IN |
GPT1 Timer T2 Input for |
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Count/Gate/Reload/Capture |
P5.7 |
5 |
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AN7, |
T4IN |
GPT1 Timer T4 Input for |
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Count/Gate/Reload/Capture |
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P3 |
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IO |
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Port 3 is a 9-bit bidirectional I/O port. It is bit-wise |
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programmable for input or output via direction bits. For a pin |
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configured as input, the output driver is put into high- |
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impedance state. Port 3 outputs can be configured as push/ |
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pull or open drain drivers. The input threshold of Port 3 is |
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selectable (TTL or special). |
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The following Port 3 pins also serve for alternate functions: |
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P3.4 |
8 |
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T3EUD |
GPT1 Timer T3 External Up/Down Control Input |
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P3.6 |
9 |
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T3IN |
GPT1 Timer T3 Count/Gate Input |
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P3.8 |
10 |
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I/O |
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MRST |
SSC Master-Receive/Slave-Transmit Inp./Outp. |
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P3.9 |
11 |
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I/O |
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MTSR |
SSC Master-Transmit/Slave-Receive Outp./Inp. |
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P3.10 |
12 |
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O |
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TxD0 |
ASC0 Clock/Data Output (Async./Sync.) |
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P3.11 |
13 |
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I/O |
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RxD0 |
ASC0 Data Input (Async.) or Inp./Outp. (Sync.) |
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P3.12 |
14 |
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O |
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External Memory High Byte Enable Signal, |
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BHE |
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O |
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WRH |
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External Memory High Byte Write Strobe |
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P3.13 |
15 |
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I/O |
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SCLK |
SSC Master Clock Output / Slave Clock Input. |
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P3.15 |
16 |
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O |
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CLKOUT |
System Clock Output (= CPU Clock), |
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O |
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FOUT |
Programmable Frequency Output |
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Data Sheet |
5 |
V2.0, 2001-05 |
C164CI/SI
C164CL/SL
Table 2 |
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Pin Definitions and Functions (cont’d) |
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Symbol |
Pin |
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Input |
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Function |
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No. |
|
Outp. |
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||
P4 |
|
|
IO |
|
Port 4 is a 6-bit bidirectional I/O port. It is bit-wise |
|||||||||||
|
|
|
|
|
|
|
|
programmable for input or output via direction bits. For a pin |
||||||||
|
|
|
|
|
|
|
|
configured as input, the output driver is put into high- |
||||||||
|
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|
|
|
impedance state. Port 4 outputs can be configured as push/ |
||||||||
|
|
|
|
|
|
|
|
pull or open drain drivers. The input threshold of Port 4 is |
||||||||
|
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|
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|
|
|
selectable (TTL or special). |
||||||||
|
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|
|
Port 4 can be used to output the segment address lines, the |
||||||||
|
|
|
|
|
|
|
|
optional chip select lines, and for serial interface lines:1) |
||||||||
P4.0 |
17 |
|
O |
|
A16 |
Least Significant Segment Address Line, |
||||||||||
|
|
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|
|
|
O |
|
|
|
Chip Select 3 Output |
||||||
|
|
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|
|
|
CS3 |
||||||||||
P4.1 |
18 |
|
O |
|
A17 |
Segment Address Line, |
||||||||||
|
|
|
|
|
|
O |
|
|
|
Chip Select 2 Output |
||||||
|
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|
|
CS2 |
||||||||||
P4.2 |
19 |
|
O |
|
A18 |
Segment Address Line, |
||||||||||
|
|
|
|
|
|
O |
|
|
|
Chip Select 1 Output |
||||||
|
|
|
|
|
|
CS1 |
||||||||||
P4.3 |
22 |
|
O |
|
A19 |
Segment Address Line, |
||||||||||
|
|
|
|
|
|
O |
|
|
|
Chip Select 0 Output |
||||||
|
|
|
|
|
|
CS0 |
||||||||||
P4.5 |
23 |
|
O |
|
A20 |
Segment Address Line, |
||||||||||
|
|
|
|
|
|
I |
|
CAN1_RxD CAN 1 Receive Data Input |
||||||||
P4.6 |
24 |
|
O |
|
A21 |
Most Significant Segment Address Line, |
||||||||||
|
|
|
|
|
|
O |
|
CAN1_TxD CAN 1 Transmit Data Output |
||||||||
|
|
|
|
|
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|
|
|
|
|
|
|||||
|
|
|
|
25 |
|
O |
|
External Memory Read Strobe. |
|
|
is activated for every |
|||||
RD |
|
RD |
||||||||||||||
|
|
|
|
|
|
|
|
external instruction or data read access. |
||||||||
|
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|
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|
|||||||
|
|
|
|
26 |
|
O |
|
External Memory Write Strobe. In |
|
|
-mode this pin is |
|||||
WR/ |
|
WR |
||||||||||||||
|
|
|
|
|
|
activated for every external data write access. In |
|
-mode |
||||||||
WRL |
|
|
|
|
WRL |
|||||||||||
|
|
|
|
|
|
|
|
this pin is activated for low byte data write accesses on a |
||||||||
|
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|
|
|
|
|
|
16-bit bus, and for every data write access on an 8-bit bus. |
||||||||
|
|
|
|
|
|
|
|
See WRCFG in register SYSCON for mode selection. |
||||||||
|
|
|
|
|
||||||||||||
ALE |
27 |
|
O |
Address Latch Enable Output. Can be used for latching the |
||||||||||||
|
|
|
|
|
|
|
|
address into external memory or an address latch in the |
||||||||
|
|
|
|
|
|
|
|
multiplexed bus modes. |
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Data Sheet |
6 |
V2.0, 2001-05 |
C164CI/SI
C164CL/SL
Table 2 |
Pin Definitions and Functions (cont’d) |
|
|
|
||||||
Symbol |
Pin |
Input |
Function |
|
|
|
|
|||
|
|
No. |
Outp. |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
VPP |
28 |
I |
External Access Enable pin. |
|
|
|
|||
EA/ |
|
|
|
|||||||
|
|
|
|
A low level at this pin during and after Reset forces the |
||||||
|
|
|
|
C164CI to latch the configuration from PORT0 and pin |
|
|
||||
|
|
|
|
RD, |
||||||
|
|
|
|
and to begin instruction execution out of external memory. |
||||||
|
|
|
|
A high level forces the C164CI to latch the configuration |
||||||
|
|
|
|
from pins |
|
and ALE, and to begin instruction execution out |
||||
|
|
|
|
RD |
||||||
|
|
|
|
of the internal program memory. |
|
|
|
|||
|
|
|
|
“ROMless” versions must have this pin tied to ‘0’. |
||||||
|
|
|
|
Note: This pin also accepts the programming voltage for the |
||||||
|
|
|
|
OTP derivatives. |
|
|
|
|||
|
|
|
|
|||||||
PORT0 |
|
IO |
PORT0 consists of the two 8-bit bidirectional I/O ports P0L |
|||||||
P0L.0-7 |
29- |
|
and P0H. It is bit-wise programmable for input or output via |
|||||||
|
|
36 |
|
direction bits. For a pin configured as input, the output driver |
||||||
P0H.0-7 |
37-39, |
|
is put into high-impedance state. |
|
|
|
||||
|
|
42-46 |
|
In case of an external bus configuration, PORT0 serves as |
||||||
|
|
|
|
the address (A) and address/data (AD) bus in multiplexed |
||||||
|
|
|
|
bus modes and as the data (D) bus in demultiplexed bus |
||||||
|
|
|
|
modes. |
|
|
|
|
||
|
|
|
|
Demultiplexed bus modes: |
|
|
|
|||
|
|
|
|
Data Path Width: |
8-bit |
16-bit |
||||
|
|
|
|
P0L.0 – P0L.7: |
D0 – D7 |
D0 – D7 |
||||
|
|
|
|
P0H.0 – P0H.7: |
I/O |
D8 – D15 |
||||
|
|
|
|
Multiplexed bus modes: |
|
|
|
|||
|
|
|
|
Data Path Width: |
8-bit |
16-bit |
||||
|
|
|
|
P0L.0 – P0L.7: |
AD0 – AD7 |
AD0 – AD7 |
||||
|
|
|
|
P0H.0 – P0H.7: |
A8 – A15 |
AD8 – AD15 |
||||
|
|
|
|
|
|
|
|
|
|
|
Data Sheet |
7 |
V2.0, 2001-05 |
C164CI/SI
C164CL/SL
Table 2 |
Pin Definitions and Functions (cont’d) |
|||||
Symbol |
Pin |
Input |
|
Function |
|
|
|
No. |
Outp. |
|
|
|
|
|
|
|
|
|
||
PORT1 |
|
IO |
|
PORT1 consists of the two 8-bit bidirectional I/O ports P1L |
||
P1L.0-7 |
47-52, |
|
|
and P1H. It is bit-wise programmable for input or output via |
||
|
57-59 |
|
|
direction bits. For a pin configured as input, the output driver |
||
P1H.0-7 |
59, |
|
|
is put into high-impedance state. PORT1 is used as the |
||
|
62-68 |
|
|
16-bit address bus (A) in demultiplexed bus modes and also |
||
|
|
|
|
after switching from a demultiplexed bus mode to a |
||
|
|
|
|
multiplexed bus mode. |
||
|
|
|
|
The following PORT1 pins also serve for alt. functions: |
||
P1L.0 |
47 |
I/O |
|
CC60 |
CAPCOM6: Input / Output of Channel 0 |
|
P1L.1 |
48 |
O |
|
COUT60 |
CAPCOM6: Output of Channel 0 |
|
P1L.2 |
49 |
I/O |
|
CC61 |
CAPCOM6: Input / Output of Channel 1 |
|
P1L.3 |
50 |
O |
|
COUT61 |
CAPCOM6: Output of Channel 1 |
|
P1L.4 |
51 |
I/O |
|
CC62 |
CAPCOM6: Input / Output of Channel 2 |
|
P1L.5 |
52 |
O |
|
COUT62 |
CAPCOM6: Output of Channel 2 |
|
P1L.6 |
57 |
O |
|
COUT63 |
Output of 10-bit Compare Channel |
|
P1L.7 |
58 |
I |
|
|
|
CAPCOM6: Trap Input |
CTRAP |
||||||
|
|
|
|
CTRAP |
is an input pin with an internal pullup resistor. A low |
|
|
|
|
|
level on this pin switches the compare outputs of the |
||
|
|
|
|
CAPCOM6 unit to the logic level defined by software. |
||
P1H.0 |
59 |
I |
|
|
CAPCOM6: Position 0 Input, **) |
|
CC6POS0 |
||||||
|
|
I |
|
EX0IN |
Fast External Interrupt 0 Input |
|
P1H.1 |
62 |
I |
|
|
CAPCOM6: Position 1 Input, **) |
|
CC6POS1 |
||||||
|
|
I |
|
EX1IN |
Fast External Interrupt 1 Input |
|
P1H.2 |
63 |
I |
|
|
CAPCOM6: Position 2 Input, **) |
|
CC6POS2 |
||||||
|
|
I |
|
EX2IN |
Fast External Interrupt 2 Input |
|
P1H.3 |
64 |
I |
|
EX3IN |
Fast External Interrupt 3 Input, |
|
|
|
|
|
T7IN |
CAPCOM2: Timer T7 Count Input |
|
P1H.4 |
65 |
I/O |
|
CC24IO |
CAPCOM2: CC24 Capture Inp./Compare Outp. |
|
P1H.5 |
66 |
I/O |
|
CC25IO |
CAPCOM2: CC25 Capture Inp./Compare Outp. |
|
P1H.6 |
67 |
I/O |
|
CC26IO |
CAPCOM2: CC26 Capture Inp./Compare Outp. |
|
P1H.7 |
68 |
I/O |
|
CC27IO |
CAPCOM2: CC27 Capture Inp./Compare Outp. |
|
|
|
|
|
Note: The marked (**) input signals are available only in |
||
|
|
|
|
devices with a full function CAPCOM6. |
||
|
|
|
|
|
|
|
Data Sheet |
8 |
V2.0, 2001-05 |
C164CI/SI
C164CL/SL
Table 2 |
|
Pin Definitions and Functions (cont’d) |
|||||||||||||||||
Symbol |
Pin |
|
Input |
Function |
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
No. |
|
Outp. |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||||||
XTAL2 |
54 |
|
O |
XTAL2: |
Output of the oscillator amplifier circuit. |
||||||||||||||
XTAL1 |
55 |
|
I |
XTAL1: |
Input to the oscillator amplifier and input to |
||||||||||||||
|
|
|
|
|
|
|
|
|
the internal clock generator |
||||||||||
|
|
|
|
|
|
|
|
To clock the device from an external source, drive XTAL1, |
|||||||||||
|
|
|
|
|
|
|
|
while leaving XTAL2 unconnected. Minimum and maximum |
|||||||||||
|
|
|
|
|
|
|
|
high/low and rise/fall times specified in the AC |
|||||||||||
|
|
|
|
|
|
|
|
Characteristics must be observed. |
|||||||||||
|
|
|
|
|
|
|
|
|
|||||||||||
|
|
|
|
|
69 |
|
I/O |
Reset Input with Schmitt-Trigger characteristics. A low level |
|||||||||||
RSTIN |
|||||||||||||||||||
|
|
|
|
|
|
|
|
at this pin while the oscillator is running resets the C164CI. |
|||||||||||
|
|
|
|
|
|
|
|
An internal pullup resistor permits power-on reset using only |
|||||||||||
|
|
|
|
|
|
|
|
a capacitor connected to VSS. |
|||||||||||
|
|
|
|
|
|
|
|
A spike filter suppresses input pulses <10 ns. Input pulses |
|||||||||||
|
|
|
|
|
|
|
|
>100 ns safely pass the filter. The minimum duration for a |
|||||||||||
|
|
|
|
|
|
|
|
safe recognition should be 100 ns + 2 CPU clock cycles. |
|||||||||||
|
|
|
|
|
|
|
|
In bidirectional reset mode (enabled by setting bit BDRSTEN |
|||||||||||
|
|
|
|
|
|
|
|
in register SYSCON) the |
|
|
line is internally pulled low |
||||||||
|
|
|
|
|
|
|
|
RSTIN |
|||||||||||
|
|
|
|
|
|
|
|
for the duration of the internal reset sequence upon any reset |
|||||||||||
|
|
|
|
|
|
|
|
(HW, SW, WDT). See note below this table. |
|||||||||||
|
|
|
|
|
|
|
|
||||||||||||
|
|
|
|
70 |
|
O |
Internal Reset Indication Output. This pin is set to a low level |
||||||||||||
RST |
|||||||||||||||||||
OUT |
|
|
|
|
when the part is executing either a hardware-, a softwareor |
||||||||||||||
|
|
|
|
|
|
|
|
a watchdog timer reset. |
RSTOUT |
remains low until the EINIT |
|||||||||
|
|
|
|
|
|
|
|
(end of initialization) instruction is executed. |
|||||||||||
|
|
|
|
|
|
||||||||||||||
|
|
71 |
|
I |
Non-Maskable Interrupt Input. A high to low transition at this |
||||||||||||||
NMI |
|||||||||||||||||||
|
|
|
|
|
|
|
|
pin causes the CPU to vector to the NMI trap routine. When |
|||||||||||
|
|
|
|
|
|
|
|
the PWRDN (power down) instruction is executed, the |
|
|
|||||||||
|
|
|
|
|
|
|
|
NMI |
|||||||||||
|
|
|
|
|
|
|
|
pin must be low in order to force the C164CI to go into power |
|||||||||||
|
|
|
|
|
|
|
|
down mode. If |
|
|
|
is high, when PWRDN is executed, the |
|||||||
|
|
|
|
|
|
|
|
NMI |
|||||||||||
|
|
|
|
|
|
|
|
part will continue to run in normal mode. |
|||||||||||
|
|
|
|
|
|
|
|
If not used, pin |
|
should be pulled high externally. |
|||||||||
|
|
|
|
|
|
|
|
NMI |
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Data Sheet |
9 |
V2.0, 2001-05 |
C164CI/SI
C164CL/SL
Table 2 |
Pin Definitions and Functions (cont’d) |
|||
Symbol |
Pin |
Input |
Function |
|
|
No. |
Outp. |
|
|
|
|
|
|
|
P8 |
|
IO |
Port 8 is a 4-bit bidirectional I/O port. It is bit-wise |
|
|
|
|
programmable for input or output via direction bits. For a pin |
|
|
|
|
configured as input, the output driver is put into high- |
|
|
|
|
impedance state. Port 8 outputs can be configured as push/ |
|
|
|
|
pull or open drain drivers. The input threshold of Port 8 is |
|
|
|
|
selectable (TTL or special). Port 8 pins provide inputs/ |
|
|
|
|
outputs for CAPCOM2 and serial interface lines.1) |
|
P8.0 |
72 |
I/O |
CC16IO |
CAPCOM2: CC16 Capture Inp./Compare Outp., |
|
|
I |
CAN1_RxD CAN 1 Receive Data Input |
|
P8.1 |
73 |
I/O |
CC17IO |
CAPCOM2: CC17 Capture Inp./Compare Outp., |
|
|
O |
CAN1_TxD CAN 1 Transmit Data Output |
|
P8.2 |
74 |
I/O |
CC18IO |
CAPCOM2: CC18 Capture Inp./Compare Outp., |
|
|
I |
CAN1_RxD CAN 1 Receive Data Input |
|
P8.3 |
75 |
I/O |
CC19IO |
CAPCOM2: CC19 Capture Inp./Compare Outp., |
|
|
O |
CAN1_TxD CAN 1 Transmit Data Output |
|
|
|
|
|
|
VAREF |
1 |
– |
Reference voltage for the A/D converter. |
|
VAGND |
80 |
– |
Reference ground for the A/D converter. |
|
VDD |
7, 21, |
– |
Digital Supply Voltage: |
|
|
40, 53, |
|
+5 V during normal operation and idle mode. |
|
|
61 |
|
≥2.5 V during power down mode. |
|
|
|
|
|
|
VSS |
6, 20, |
– |
Digital Ground. |
|
|
41, 56, |
|
|
|
|
60 |
|
|
|
|
|
|
|
|
1)The CAN interface lines are assigned to ports P4 and P8 under software control. Within the CAN module several assignments can be selected.
Note: The following behavioural differences must be observed when the bidirectional reset is active:
•Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared automatically after a reset.
•The reset indication flags always indicate a long hardware reset.
•The PORT0 configuration is treated as if it were a hardware reset. In particular, the bootstrap loader may be activated when P0L.4 is low.
•Pin RSTIN may only be connected to external reset devices with an open drain output driver.
•A short hardware reset is extended to the duration of the internal reset sequence.
Data Sheet |
10 |
V2.0, 2001-05 |
C164CI/SI
C164CL/SL
The architecture of the C164CI combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. In addition the on-chip memory blocks allow the design of compact systems with maximum performance.
The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C164CI.
Note: All time specifications refer to a CPU clock of 25 MHz (see definition in the AC Characteristics section).
|
ProgMem |
|
|
|
|
C166-Core |
16 |
Port |
IRAM |
|
|||
|
|
|
|
|
|
|
|
|
Data |
Internal |
|
||
|
ROM: 48/64 |
|
|
32 |
|
CPU |
|
16 |
|
||||
|
|
|
|
|
Dual |
|
|||||||
|
|
|
|
|
RAM |
|
|||||||
|
|
OTP: 64 |
Instr. / Data |
|
|
Data |
|
||||||
|
|
|
|
|
|
|
|
|
|||||
|
|
KByte |
|
|
|
|
|
|
|
|
2 KByte |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
16 |
|
|
|
|
|
Osc / PLL |
|
|
|
|
XRAM |
|
|
|
|
|
PEC |
|
|
XTAL |
||
|
|
|
|
External Instr. / Data |
|
|
|
|
|||||
|
|
2 KByte |
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Interrupt Controller |
16-Level |
|
RTC |
WDT |
|
||
|
|
|
|
|
|
Priority |
|
|
|||||
|
|
|
|
|
|
|
|
16 |
|
||||
|
|
|
|
|
|
|
|
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-BitDemux) |
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Interrupt Bus |
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16 |
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Peripheral Data Bus |
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CAN |
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XBUS(16 |
ADC |
ASC0 |
SSC |
GPT1 |
CCOM2 CCOM6 |
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Rev 2.0B active |
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10-Bit |
(USART) |
(SPI) |
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T2 |
T7 |
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T12 |
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8 |
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EBC |
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T3 |
T8 |
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T13 |
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6 |
4 |
XBUS Control |
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T4 |
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Port1 |
16 |
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External Bus |
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Control |
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BRGen |
BRGen |
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Port 0 |
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Port 5 |
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Port 3 |
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Port 8 |
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16 |
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8 |
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9 |
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4 |
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MCB04323_4ci |
Figure 3 Block Diagram
The program memory, the internal RAM (IRAM) and the set of generic peripherals are connected to the CPU via separate buses. A fourth bus, the XBUS, connects external resources as well as additional on-chip resoures, the X-Peripherals (see Figure 3).
The XBUS resources (XRAM, CAN) of the C164CI can be enabled or disabled during initialization by setting the general X-Peripheral enable bit XPEN (SYSCON.2). Modules that are disabled consume neither address space nor port pins.
Data Sheet |
11 |
V2.0, 2001-05 |
C164CI/SI
C164CL/SL
The memory space of the C164CI is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bitaddressable.
The C164CI incorporates 64 KBytes of on-chip OTP memory or 64/48 KBytes of on-chip mask-programmable ROM (not in the ROM-less derivative, of course) for code or constant data. The lower 32 KBytes of the on-chip ROM/OTP can be mapped either to segment 0 or segment 1.
The OTP memory can be programmed by the CPU itself (in system, e.g. during booting) or directly via an external interface (e.g. before assembly). The programming time is approx. 100 µs per word. An external programming voltage VPP = 11.5 V must be
supplied for this purpose (via pin EA/VPP).
2 KBytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called General Purpose Registers (GPRs).
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for future members of the C166 Family.
2 KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user stacks, or code. The XRAM is accessed like external memory and therefore cannot be used for the system stack or for register banks and is not bitaddressable. The XRAM permits 16-bit accesses with maximum speed.
In order to meet the needs of designs where more memory is required than is provided on chip, up to 4 MBytes of external RAM and/or ROM can be connected to the microcontroller.
Data Sheet |
12 |
V2.0, 2001-05 |
C164CI/SI
C164CL/SL
All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follows:
–16-/18-/20-/22-bit Addresses, 16-bit Data, Demultiplexed
–16-/18-/20-/22-bit Addresses, 16-bit Data, Multiplexed
–16-/18-/20-/22-bit Addresses, 8-bit Data, Multiplexed
–16-/18-/20-/22-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1 and data is input/ output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for input/output.
Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user the adaption of a wide range of different types of memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via register pairs ADDRSELx / BUSCONx) which control the access to different resources with different bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows are controlled by BUSCON0.
Up to 4 external CS signals (3 windows plus default) can be generated in order to save external glue logic. The C164CI offers the possibility to switch the CS outputs to an unlatched mode. In this mode the internal filter logic is switched off and the CS signals are directly generated from the address. The unlatched CS mode is enabled by setting CSCFG (SYSCON.6).
For applications which require less than 4 MBytes of external memory space, this address space can be restricted to 1 MByte, 256 KByte, or to 64 KByte. In this case Port 4 outputs four, two, or no address lines at all. It outputs all 6 address lines, if an address space of 4 MBytes is used.
Note: When the on-chip CAN Module is used with the interface lines assigned to Port 4, the CAN lines override the segment address lines and the segment address output on Port 4 is therefore limited to 4 bits i.e. address lines A19 … A16.
Data Sheet |
13 |
V2.0, 2001-05 |
C164CI/SI
C164CL/SL
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the C164CI’s instructions can be executed in just one machine cycle which requires 2 CPU clocks (4 TCL). For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 × 16 bit multiplication in 5 cycles and a 32-/16-bit division in 10 cycles. Another pipeline optimization, the socalled ‘Jump Cache’, reduces the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
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CPU |
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16 |
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SP |
MDH |
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Internal |
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RAM |
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STKOV |
MDL |
R15 |
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STKUN |
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Exec. Unit |
Mul/Div-HW |
General |
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Instr. Ptr. |
Bit-Mask Gen |
R15 |
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Instr. Reg. |
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ALU |
Purpose |
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32 |
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ROM |
4-Stage |
(16-bit) |
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Pipeline |
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Registers |
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Barrel - Shifter |
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PSW |
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R0 |
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SYSCON |
Context Ptr. |
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BUSCON 0 |
ADDRSEL 1 |
R0 |
16 |
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BUSCON 1 |
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BUSCON 2 |
ADDRSEL 2 |
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BUSCON 3 |
ADDRSEL 3 |
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BUSCON 4 |
ADDRSEL 4 |
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Data Page Ptr. |
Code Seg. Ptr. |
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MCB02147 |
Figure 4 CPU Block Diagram
Data Sheet |
14 |
V2.0, 2001-05 |
C164CI/SI
C164CL/SL
The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at any time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others.
A system stack of up to 1024 words is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow.
The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly efficient C164CI instruction set which includes the following instruction classes:
–Arithmetic Instructions
–Logical Instructions
–Boolean Bit Manipulation Instructions
–Compare and Loop Control Instructions
–Shift and Rotate Instructions
–Prioritize Instruction
–Data Movement Instructions
–System Stack Instructions
–Jump and Call Instructions
–Return Instructions
–System Control Instructions
–Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands.
Data Sheet |
15 |
V2.0, 2001-05 |
C164CI/SI
C164CL/SL
With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of internal program execution), the C164CI is capable of reacting very fast to the occurrence of non-deterministic events.
The architecture of the C164CI supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicity decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data. The C164CI has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location.
Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges).
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an individual trap (interrupt) number.
Table 3 shows all of the possible C164CI interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.
Note: Interrupt nodes which are not used by associated peripherals, may be used to generate software controlled interrupt requests by setting the respective interrupt request bit (xIR).
Data Sheet |
16 |
V2.0, 2001-05 |
C164CI/SI
C164CL/SL
Table 3 |
C164CI Interrupt Nodes |
|
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||
Source of Interrupt or |
Request |
Enable |
Interrupt |
Vector |
Trap |
|
PEC Service Request |
Flag |
Flag |
Vector |
Location |
Number |
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Fast External Interrupt 0 |
CC8IR |
CC8IE |
CC8INT |
00’0060H |
18H |
|
Fast External Interrupt 1 |
CC9IR |
CC9IE |
CC9INT |
00’0064H |
19H |
|
Fast External Interrupt 2 |
CC10IR |
CC10IE |
CC10INT |
00’0068H |
1AH |
|
Fast External Interrupt 3 |
CC11IR |
CC11IE |
CC11INT |
00’006CH |
1BH |
|
GPT1 Timer 2 |
|
T2IR |
T2IE |
T2INT |
00’0088H |
22H |
GPT1 Timer 3 |
|
T3IR |
T3IE |
T3INT |
00’008CH |
23H |
GPT1 Timer 4 |
|
T4IR |
T4IE |
T4INT |
00’0090H |
24H |
A/D Conversion |
ADCIR |
ADCIE |
ADCINT |
00’00A0H |
28H |
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Complete |
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A/D Overrun Error |
ADEIR |
ADEIE |
ADEINT |
00’00A4H |
29H |
|
ASC0 Transmit |
S0TIR |
S0TIE |
S0TINT |
00’00A8H |
2AH |
|
ASC0 Transmit Buffer |
S0TBIR |
S0TBIE |
S0TBINT |
00’011CH |
47H |
|
ASC0 Receive |
S0RIR |
S0RIE |
S0RINT |
00’00ACH |
2BH |
|
ASC0 Error |
|
S0EIR |
S0EIE |
S0EINT |
00’00B0H |
2CH |
SSC Transmit |
|
SCTIR |
SCTIE |
SCTINT |
00’00B4H |
2DH |
SSC Receive |
|
SCRIR |
SCRIE |
SCRINT |
00’00B8H |
2EH |
SSC Error |
|
SCEIR |
SCEIE |
SCEINT |
00’00BCH |
2FH |
CAPCOM Register 16 |
CC16IR |
CC16IE |
CC16INT |
00’00C0H |
30H |
|
CAPCOM Register 17 |
CC17IR |
CC17IE |
CC17INT |
00’00C4H |
31H |
|
CAPCOM Register 18 |
CC18IR |
CC18IE |
CC18INT |
00’00C8H |
32H |
|
CAPCOM Register 19 |
CC19IR |
CC19IE |
CC19INT |
00’00CCH |
33H |
|
CAPCOM Register 24 |
CC24IR |
CC24IE |
CC24INT |
00’00E0H |
38H |
|
CAPCOM Register 25 |
CC25IR |
CC25IE |
CC25INT |
00’00E4H |
39H |
|
CAPCOM Register 26 |
CC26IR |
CC26IE |
CC26INT |
00’00E8H |
3AH |
|
CAPCOM Register 27 |
CC27IR |
CC27IE |
CC27INT |
00’00ECH |
3BH |
|
CAPCOM Timer 7 |
T7IR |
T7IE |
T7INT |
00’00F4H |
3DH |
|
CAPCOM Timer 8 |
T8IR |
T8IE |
T8INT |
00’00F8H |
3EH |
|
CAPCOM6 Interrupt |
CC6IR |
CC6IE |
CC6INT |
00’00FCH |
3FH |
|
CAN Interface 1 |
XP0IR |
XP0IE |
XP0INT |
00’0100H |
40H |
|
PLL/OWD and RTC |
XP3IR |
XP3IE |
XP3INT |
00’010CH |
43H |
Data Sheet |
17 |
V2.0, 2001-05 |
C164CI/SI
C164CL/SL
Table 3 |
C164CI Interrupt Nodes (cont’d) |
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Source of Interrupt or |
Request |
Enable |
Interrupt |
Vector |
Trap |
|
PEC Service Request |
Flag |
Flag |
Vector |
Location |
Number |
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CAPCOM 6 Timer 12 |
T12IR |
T12IE |
T12INT |
00’0134H |
4DH |
|
CAPCOM 6 Timer 13 |
T13IR |
T13IE |
T13INT |
00’0138H |
4EH |
|
CAPCOM 6 Emergency |
CC6EIR |
CC6EIE |
CC6EINT |
00’013CH |
4FH |
Data Sheet |
18 |
V2.0, 2001-05 |
C164CI/SI
C164CL/SL
The C164CI also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts.
Table 4 shows all of the possible exceptions or error conditions that can arise during runtime:
Table 4 |
Hardware Trap Summary |
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Exception Condition |
Trap |
Trap |
Vector |
Trap |
Trap |
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Flag |
Vector |
Location |
Number |
Priority |
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Reset Functions: |
– |
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– |
Hardware Reset |
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RESET |
00’0000H |
00H |
III |
|
– |
Software Reset |
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RESET |
00’0000H |
00H |
III |
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– |
W-dog Timer Overflow |
|
RESET |
00’0000H |
00H |
III |
|
Class A Hardware Traps: |
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– |
Non-Maskable Interrupt |
NMI |
NMITRAP |
00’0008H |
02H |
II |
|
– |
Stack Overflow |
STKOF |
STOTRAP |
00’0010H |
04H |
II |
|
– |
Stack Underflow |
STKUF |
STUTRAP |
00’0018H |
06H |
II |
|
Class B Hardware Traps: |
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– |
Undefined Opcode |
UNDOPC |
BTRAP |
00’0028H |
0AH |
I |
|
– |
Protected Instruction |
PRTFLT |
BTRAP |
00’0028H |
0AH |
I |
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Fault |
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– |
Illegal Word Operand |
ILLOPA |
BTRAP |
00’0028H |
0AH |
I |
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Access |
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– |
Illegal Instruction |
ILLINA |
BTRAP |
00’0028H |
0AH |
I |
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Access |
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– |
Illegal External Bus |
ILLBUS |
BTRAP |
00’0028H |
0AH |
I |
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Access |
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Reserved |
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– |
– |
[2CH – |
[0BH – |
– |
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3CH] |
0FH] |
|
Software Traps |
– |
– |
Any |
Any |
Current |
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– |
TRAP Instruction |
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[00’0000H – |
[00H – |
CPU |
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00’01FCH] |
7FH] |
Priority |
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in steps |
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of 4H |
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Data Sheet |
19 |
V2.0, 2001-05 |
C164CI/SI
C164CL/SL
The general purpose CAPCOM2 unit supports generation and control of timing sequences on up to 8 channels with a maximum resolution of 16 TCL. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events.
Two 16-bit timers (T7/T8) with reload registers provide two independent time bases for the capture/compare register array.
Each dual purpose capture/compare register, which may be individually allocated to either CAPCOM timer and programmed for capture or compare function, has one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event.
When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (‘capture’d) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode.
Table 5 |
Compare Modes (CAPCOM2) |
|
Compare Modes |
Function |
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Mode 0 |
|
Interrupt-only compare mode; |
|
|
several compare interrupts per timer period are possible |
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Mode 1 |
|
Pin toggles on each compare match; |
|
|
several compare events per timer period are possible |
|
|
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Mode 2 |
|
Interrupt-only compare mode; |
|
|
only one compare interrupt per timer period is generated |
|
|
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Mode 3 |
|
Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow; |
|
|
only one compare event per timer period is generated |
|
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|
Double |
|
Two registers operate on one pin; pin toggles on each compare |
Register Mode |
match; |
|
|
|
several compare events per timer period are possible. |
|
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Registers CC16 & CC24 pin CC16IO |
|
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Registers CC17 & CC25 pin CC17IO |
|
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Registers CC18 & CC26 pin CC18IO |
|
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Registers CC19 & CC27 pin CC19IO |
|
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|
Data Sheet |
20 |
V2.0, 2001-05 |