ICST AV1660N, AV1660M, ICS1660M Datasheet

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Integrated

ICS1660

Circuit

 

Systems, Inc.

 

Incoming Call Line Identification (ICLID) Receiver with Ring Detection

Description

The ICS1660 “ICLID” circuit is a monolithic CMOS VLSI device that decodes and detects the Frequency Shift Keying (FSK) signals used in caller identification telephone service. The ICS1660, when used in conjunction with some external components, amplifies, filters and demodulates the FSK data transmitted from the central office to the telephone subscriber.

The ICS1660 detects the first power ring signal and demodulates the 1200 baud FSK data transmitted during the silent interval between the first and second power ring. The FSK data is transmitted from the central office switch to the subscriber line as part of the CLASS service of Calling Number Delivery (CND). This data is then demodulated, amplified and filtered by the ICS1660 and digitally transmitted to the host controller/processor.

The ICS1660 is designed to be powered by any off-the-shelf 9.0 volt battery. The on-chip 5.0 voltage regulator powers the host microprocessor and any external circuitry supported by the ICS1660. This portion of the circuit can be overridden by connecting the VIN pin (18) to the VDD pin (1) for a common power supply. A low battery detection circuit is also provided on-chip and signals the microprocessor on the FSK/BAT pin (17) when the PWR pin (16) input is pulled low.

Features

Ring Detection

Low Battery Detection

Internal 5V Regulator - can externally source 25mA

FSK Demodulation

Power-down in Standby Mode

Direct Interface to Host Microprocessor or Microcomputer

Applications

Telephones

Facsimile Machines

Modems

Telephone Interface Equipment

Stand-alone ICLID products

ICLID Block Diagram

 

 

 

 

 

TO LINE

 

 

 

 

 

 

 

Surge and

 

2 x 16 LCD

 

 

 

Lightning

 

 

 

 

 

Display

 

 

 

Protection

 

 

 

 

 

 

 

TO PHONE

 

 

8

3

 

 

 

 

Data

Control

 

 

 

ICS1660

 

Micro-

KEYPAD

 

 

Rng Detect

 

Controller

 

 

 

FSK Demodulation

 

 

 

 

 

Signal Conditioning

 

 

 

 

 

Low Battery Detect

 

 

 

 

 

Power-down

 

 

External

 

 

 

 

Memory

 

 

Standby

 

 

 

 

 

 

(RAM/EPROM)

 

 

 

+5VDC

 

AC/DC

DC

Voltage

 

 

 

 

 

Adapter

Jack

Regulation

 

 

 

 

 

9VDC

 

 

 

ICS1660RevA100694

 

 

 

 

 

ICST AV1660N, AV1660M, ICS1660M Datasheet

ICS1660

Block Diagram

 

 

 

 

 

 

.022

F

.033

F

 

 

 

 

 

 

 

 

 

 

 

F1

F2

F3

 

 

 

 

 

 

LINE AF

 

5

 

 

15

10

13

2

RING

 

 

 

 

 

BUFFER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

FOUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.1 F

0.01

 

 

 

 

 

 

 

 

 

 

 

F

 

 

 

 

 

 

 

 

 

 

 

82k

 

 

 

 

 

 

 

 

 

.0033 F

.022

F

TIP

0.1 F

LINE A

 

7

 

 

 

 

 

 

 

 

 

RING

DIFF

 

FILTER

 

 

 

 

 

RING

LINE B

 

8

 

 

 

 

 

 

 

DETECT

AMP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

82k

0.01

 

 

 

 

 

 

 

 

AMPIN

 

 

 

 

F

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LINE BF

 

14

BUFFER

 

 

 

 

POST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AMP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VIN

 

18

REGULATOR

 

 

 

 

 

 

 

 

 

 

VDD

1

 

 

 

 

 

 

 

 

 

 

5 VOLT

 

 

 

 

6

VCOSET

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

LFILTER

 

 

 

 

10 F

 

 

 

 

 

 

PLL

 

 

 

 

 

 

 

 

 

 

 

3

POSTF

 

 

 

 

VSS

9

 

 

LOW

 

 

 

1000pF

.01 F

500k

 

 

 

 

 

 

 

BATTERY

 

 

 

 

 

 

 

 

 

 

 

 

 

DETECT

 

 

 

 

 

 

 

 

PWR

16

POWER

 

 

 

 

17

FSKBAT

 

 

 

 

 

 

 

CONTROL

 

 

 

 

MUX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

ICS1660

Function Description

Power Supply

The ICS1660 is designed to be powered by a standard 9.0 volt battery. The chip contains a voltage regulator that powers external circuitry and provides the supply voltage for all digital I/O on the circuit. This allows easy interface between the ICS1660 and other standard logic working at 5.0V. This regulator has short circuit protection and requires an external filter/compensation capacitor with a minimum value of 10uf.

In the event that an external regulated 5.0V supply is available, the VIN and VDD pins can be shorted to permit the entire system to work from a common supply.

A low battery detection circuit is provided. This circuit is designed for a typical trip point of 6.0V with hysteresis of about 200mV above the trip point. This signal is low active and is multiplexed to the FSKBAT output pin when the PWR input is low.

In an effort to keep power dissipation to a minimum and extend battery life, most of the analog circuits are turned off when the circuit is at rest waiting for a ring detect, (PWR pin low). During this time only the regulator, low battery detect, reference generator, and ring detect circuits are active. When the PWR pin is high, all circuits are active.

Ring Detect

As shown in the attached block diagram, the LINEA and LINEB inputs should be connected to the telephone line through external 82kresistors and 0.1uf capacitors. This provides DC isolation and sets up a voltage divider with internal resistors that will detect 35.0V RMS typically. This voltage is applied across the LINEA and LINEB inputs. The design value of the internal resistors is 8.1KΩ ± 20% with relative accuracy of 2%. The RING output is high active.

Differential Front End

As shown in the attached block diagram, the LINEA and LINEB inputs go into a differential amplifier which in turn drives a filter. All resistors are internal to the chip while capacitors are connected as shown in the block diagram. After filtering, the signal is AC coupled into a high gain amplifier that converts the signal to digital. This digital signal in turn acts as the reference frequency for the phase comparator section of the phase locked loop.

FSK Demodulation

After the signal from the telephone line has been filtered, amplified and converted to digital, it acts as an input to a phase locked loop. This PLL does FSK demodulation. The summing amplifier shown in the block diagram provides a signal to the VCO that should be about 0.5V for MARK frequency (1200 HZ), and 2.0V for SPACE frequency (2200 HZ).

As shown in the block diagram, the LFILTER (loop filter) output has a post filter attached to it. This POSTF signal is sent to a comparator. The other side of the comparator is set to approximately 2.5V. This comparator has a small amount (200mV) of hysteresis and its output is the demodulated FSK data. The FSK output is high for MARK frequency and low for SPACE frequency. FSK data is multiplexed out of the FSKBAT pin when the PWR input is high.

The VCO frequency is set with one external resistor with a value in the range of 300K for a center frequency of 1700 HZ. The lock range will be 660 HZ to 2630 HZ typical. The center frequency reproducibility will be ± 15%. The center frequency can be adjusted in the system by connecting AMPIN to VSS, PWR to VDD, and adjusting the external resistor for 1700 HZ. This frequency can be observed at the LFILTER output or the FSK/BAT output.

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