ICST GSP2572N-SA, GSP2572M-SC, GSP2572M-SB, GSP2572M-SA, GSP2572N-SD, GSP2572N-SB, AV2572N-SD, AV2572N-SC, AV2572N-SB, AV2572N-SA, AV2572M-SD, AV2572M-SC, AV2572M-SB, AV2572M-SA, GSP2572M-SD, ICS2572M-SA, ICS2572M-SB, ICS2572M-SC, ICS2572M-SD, ICS2572N-SA, ICS2572N-SC, ICS2572N-SD Datasheet

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ICST GSP2572N-SA, GSP2572M-SC, GSP2572M-SB, GSP2572M-SA, GSP2572N-SD, GSP2572N-SB, AV2572N-SD, AV2572N-SC, AV2572N-SB, AV2572N-SA, AV2572M-SD, AV2572M-SC, AV2572M-SB, AV2572M-SA, GSP2572M-SD, ICS2572M-SA, ICS2572M-SB, ICS2572M-SC, ICS2572M-SD, ICS2572N-SA, ICS2572N-SC, ICS2572N-SD Datasheet

Integrated

ICS2572

 

Circuit

 

Systems, Inc.

 

User-Programmable Dual High-Performance Clock Generator

Description

The ICS2572 is a dual-PLL (phase-locked loop) clock generator with differential video outputs specifically designed for high-resolution, high-refresh rate, video applications. The video PLL generates any of 16 pre-programmed frequencies through selection of the address lines FS0-FS3. Similarly, the auxiliary PLL can generate any one of four pre-programmed frequencies via the MS0 & MS1 lines.

A unique feature of the ICS2572 is the ability to redefine frequency selections after power-up. This permits complete set-up of the frequency table upon system initialization.

Features

Advanced ICS monolithic phase-locked loop technology

Supports high-resolution graphics - differential CLK output to 185 MHz

Divided dotclock output (LOAD) available

Simplified device programming

Sixteen selectable VCLK frequencies (all user re-programmable)

Four selectable MCLK frequencies (all user re-programmable)

Windows NT compatible

Applications

High end PC/low end workstation graphics designs requiring differential output

X Terminal graphics

Block Diagram

XTAL1

Crystal

Reference

EXTFREQ

/1, 4, 5 or 8

LOAD

Oscillator

Divider

 

 

 

XTAL2

 

Phase-

 

 

/ 2

 

 

Charge

 

 

 

 

Frequency

VCO

 

CLK+

 

Pump

 

 

Comparator

 

 

 

 

 

 

 

 

 

 

 

 

/ 4

CLK-

 

 

 

 

 

 

 

Prescaler

 

 

 

 

 

 

 

/ 8

 

 

/ M

/ A

 

 

 

 

 

MCLK PLL (as above)

 

 

 

 

 

 

 

/ 2

 

Strobe

 

 

 

 

 

FS0

VCLK Set &

 

 

 

MCLK

FS1

Program

 

 

/ 4

 

Mode

 

 

 

 

FS2

 

 

 

 

Interface

 

 

 

 

FS3

 

 

 

 

MCLK Set

 

 

 

 

MS0

 

 

/ 8

 

 

 

 

 

 

MS1

ICS2572RevC090894

E-95

ICS2572

Pin Configuration

XTAL1 1

XTAL2 2

XTFREQ 3

FS0 4

FS1 5

STROBE 6

FS2 7

FS3 8

MS0 9

VSS 10

ICS2572

20 VDD

19 CLK+

18 CLK-

17 VSS

16 LOAD

15 VAA

14 VSS

13 VDD

12 MCLK

11 MS1

20-Pin DIP or SOIC J-4, J-7

Pin Descriptions

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

1

XTAL1

A

Quartz crystal connection 1/Reference Frequency Input.

2

XTAL2

A

Quartz crystal connection 2.

3

EXTFREQ

I

External Frequency Input

4

FS0

I

VCLK PLL Frequency Select LSB.

5

FS1

I

VCLK PLL Frequency Select Bit.

7

FS2

I

VCLK PLL Frequency Select Bit.

8

FS3

I

VCLK PLL Frequency Select MSB.

6

STROBE

I

Control for Latch of VCLK Select Bits (FS0-FS3).

9

MS0

I

MCLK PLL Frequency Select LSB.

11

MS1

I

MCLK PLL Frequency Select MSB.

19

CLK+

O

Pixel Clock Output (not inverted)

18

CLK-

O

Pixel Clock Output (inverted)

16

LOAD

O

Divided Dotclock (/4, 5, or 8)

12

MCLK

O

MCLK Frequency Output

17

RESERVED

-

Must Be Connected to VSS.

10, 14

VSS

P

Device Ground. All pins must be connected.

13, 20

VDD

P

Output Stage Vdd. All pins must be connected.

15

VAA

P

Synthesizer Vdd.

 

 

 

 

E-96

ICS2572

Digital Inputs

The FS0-FS3 pins and the STROBE pin are used to select the desired operating frequency of the VCLK output from the 16 pre-programmed/user-programmed selections in the ICS2572. These pins are also used to load new frequency data into the registers.

Available configurations for the STROBE input include: posi- tive-edge triggered, negative-edge triggered, high-level transparent, and low-level transparent (see Ordering Information).

VCLK Output Frequency Selection

To change the VCLK output frequency, simply write the appropriate data to the ICS2572 FS inputs. Do not perform any further writes to the device for 50 milliseconds (assumes a 14.318 MHz reference). The synthesizer will output the new frequency programmed into that location after a brief delay (see timeout specifications).

MCLK Output Frequency Selection

The MS0-MS1 pins are used to directly select the desired operating frequency of the MCLK output from the four pre- programmed/user-programmed selections in the ICS2572. These inputs are not latched, nor are they involved with memory programming operations.

Programming Mode Selection

A programming sequence is defined as a period of at least 50 milliseconds of no data writes to the ICS2572 (to clear the shift register) followed by a series of data writes (as shown here):

FS0

FS1

 

FS2

FS3

X

X

START bit (must be “0”)

0

X

X

 

1

X

X

R/W* control

0

X

X

 

1

X

X

L0 (location LSB)

0

X

X

 

1

X

X

L1

 

0

X

X

 

1

X

X

L2

 

0

X

X

 

1

X

X

L3

 

0

X

X

 

1

X

X

L4 (location MSB)

0

X

X

 

1

X

X

N0

(feedback LSB)

0

X

X

 

1

X

X

N1

 

0

X

X

 

1

X

X

N2

 

0

X

X

 

1

X

X

N3

 

0

X

X

 

1

X

X

N4

 

0

X

X

 

1

X

X

N5

 

0

X

X

 

1

X

X

N6

 

0

X

X

 

1

X

X

N7

(feedback MSB)

0

X

X

 

1

X

X

EXTFREQ bit (selected if “1”)

0

X

X

 

1

X

X

D0

(post-divider LSB)

0

X

X

 

1

X

X

D1

(post-divider MSB)

0

X

X

 

1

X

X

STOP1 bit (must be “1”

0

X

X

 

1

X

X

STOP2 bit (must be “1”)

0

X

X

 

1

 

 

 

 

 

E-97

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