ICSI IC62LV12816DLL-55TI, IC62LV12816DLL-70B, IC62LV12816DLL-70BI, IC62LV12816DLL-70T, IC62LV12816DLL-70TI Datasheet

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IC62LV12816DL

IC62LV12816DLL

Document Title

128 K x 16 bit Low Voltage and Ultra Low Power CMOS Static RAM

Revision History

Revision No

History

Draft Date

Remark

0A

Initial Draft

June 7,2002

Preliminary

The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.

Integrated Circuit Solution Inc.

1

LPSR025-0A 6/7/2002

IC62LV12816DL

IC62LV12816DLL

128K x 16 LOW VOLTAGE, ULTRA

Preliminary

LOW POWER CMOS STATIC RAM

 

FEATURES

High-speed access times: 55, 70, 100 ns

CMOS low power operation --60mW (typical)* operating --3µW (typical)* CMOS standby

TTL compatible interface levels

Single 2.7V-3.6V Vcc power supply

Fully static operation: no clock or refresh required

Three state outputs

Data control for upper and lower bytes

Industrial temperature available

Available in the 44-pin TSOP-2 and 48-pin 6x8mm TF-BGA

CE2 pin only for 48-pin TF-BGA.

* Typical values are measured at VCC=3.0V, TA=25°C

DESCRIPTION

The ICSI IC62LV12816DL and IC62LV12816DLL are lowpower,2,097,152 bit static RAMs organized as 131,072 words by 16 bits. They are fabricated using ICSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices.

When CE1 is HIGH or when CE2 is low (deselected) or both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels.

Easy memory expansion is provided by using Chip Enable Output and Enable inputs, CE1, CE2 and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access.

The IC62LV12816DL and IC62LV12816DLL are packaged in the JEDEC standare 44-pin TSOP-2 and 48-pin 6*8mm TFBGA.

FUNCTIONAL BLOCK DIAGRAM

A0-A16

 

DECODER

 

 

128K x 16

 

 

 

MEMORY ARRAY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O0-I/O7

 

 

 

 

 

 

 

 

 

I/O

 

 

 

 

 

 

 

 

 

 

 

Lower Byte

 

 

 

COLUMN I/O

 

DATA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O8-I/O15

 

CIRCUIT

 

 

 

 

 

 

 

 

 

 

 

 

Upper Byte

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE1,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OE

 

CONTROL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WE

 

 

 

 

 

 

 

 

 

 

 

 

 

CIRCUIT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

2

Integrated Circuit Solution Inc.

LPSR025-0A 6/7/2002

ICSI IC62LV12816DLL-55TI, IC62LV12816DLL-70B, IC62LV12816DLL-70BI, IC62LV12816DLL-70T, IC62LV12816DLL-70TI Datasheet

IC62LV12816DL

IC62LV12816DLL

PIN CONFIGURATIONS

44-Pin TSOP-2

 

 

48-Pin TF-BGA (TOP View)

 

 

A4

1

44

A5

 

1

2

3

4

5

6

A3

2

43

A6

 

A2

3

42

A7

 

 

 

 

 

 

 

A1

4

41

OE

A

LB

OE

A0

A1

A2

CE2

A0

5

40

UB

 

 

 

 

 

 

 

CE1

6

39

LB

B

I/O8

UB

A3

A4

CE1

I/O0

I/O0

7

38

I/O15

 

 

 

 

 

 

 

I/O1

8

37

I/O14

C

I/O9

I/O10

A5

A6

I/O1

I/O2

I/O2

9

36

I/O13

 

 

 

 

 

 

 

I/O3

10

35

I/O12

D

GND

I/O11

NC

A7

I/O3

Vcc

Vcc

11

34

GND

GND

12

33

Vcc

E

Vcc

I/O12

NC

A16

I/O4

GND

I/O4

13

32

I/O11

I/O5

14

31

I/O10

F

I/O14

I/O13

A14

A15

I/O5

I/O6

I/O6

15

30

I/O9

I/O7

16

29

I/O8

G

I/O15

NC

A12

A13

WE

I/O7

WE

17

28

NC

A16

18

27

A8

H

NC

A8

 

A10

 

 

A15

19

26

A9

A9

A11

NC

A14

20

25

A10

 

 

 

 

 

 

 

A13

21

24

A11

 

 

 

 

 

 

 

A12

22

23

NC

 

 

 

 

 

 

 

PIN DESCRIPTIONS

 

A0-A16

Address Inputs

 

 

 

 

 

I/O0-I/O15

Data Input/Output

 

 

 

 

 

 

 

Chip Enable1 Input

 

CE1

 

 

 

 

 

CE2

Chip Enable2 Input, BGA only

 

 

 

 

 

OE

Output Enable Input

 

 

 

 

 

WE

Write Enable Input

 

 

 

 

LB

Lower-byte Control (l/O0-I/O7)

 

 

UB

Upper-byte Control (l/O8-I/O15)

 

 

NC

No Connection

 

 

Vcc

Power

 

 

GND

Ground

 

 

TRUTH TABLE

 

 

 

 

 

 

 

 

I/O PIN

 

Mode

WE

CE1

CE2

OE

LB

UB

I/O0/-I/O7

I/O8-I/O15

Vcc Current

 

 

 

 

 

 

 

 

 

 

Not Selected

X

H

X

X

X

X

High-Z

High-Z

Standby

 

X

X

L

X

X

X

High-Z

High-Z

Standby

 

X

L

H

X

H

H

High-Z

High-Z

Standby

 

 

 

 

 

 

 

 

 

 

Output Disabled

H

L

H

H

L

X

High-Z

High-Z

Active

 

H

L

H

H

X

L

High-Z

High-Z

Active

 

 

 

 

 

 

 

 

 

 

Read

H

L

H

L

L

H

DOUT

High-Z

Active

 

H

L

H

L

H

L

High-Z

DOUT

Active

 

H

L

H

L

L

L

DOUT

DOUT

Active

 

 

 

 

 

 

 

 

 

 

Write

L

L

H

X

L

H

DIN

High-Z

Active

 

L

L

H

X

H

L

High-Z

DIN

Active

 

L

L

H

X

L

L

DIN

DIN

Active

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Integrated Circuit Solution Inc.

 

 

 

 

 

 

3

LPSR025-0A 6/7/2002

IC62LV12816DL

IC62LV12816DLL

OPERATING RANGE

Range

Ambient Temperature

VCC

Commercial

0°C to +70°C

2.7V- 3.6V

 

 

 

Industrial

–40°C to +85°C

2.7V - 3.6V

 

 

 

ABSOLUTE MAXIMUM RATINGS(1)

Symbol

Parameter

Value

Unit

VTERM

Terminal Voltage with Respect to GND

–0.5 to Vcc + 0.5

V

 

 

 

 

TBIAS

Temperature Under Bias

–40 to +85

°C

 

 

 

 

VCC

Vcc related to GND

–0.3 to +4.0

V

 

 

 

 

TSTG

Storage Temperature

–65 to +150

°C

 

 

 

 

PT

Power Dissipation

1.0

W

Notes:

1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

VOH

Output HIGH Voltage

IOH = –1 mA

2.0

V

 

 

 

 

 

 

VOL

Output LOW Voltage

IOL = 2.1 mA

0.4

V

 

 

 

 

 

 

VIH(1)

Input HIGH Voltage

 

2.2

VCC + 0.2

V

VIL(2)

Input LOW Voltage(1)

 

–0.2

0.4

V

ILI

Input Leakage

GND VIN VCC

–1

1

µA

 

 

 

 

 

 

ILO

Output Leakage

GND VOUT VCC, OUTPUTS DISABLED

–1

1

µA

Notes:

1.VIH(max.) = Vcc + 0.2V for pulse width less than 10ns.

2.VIL(min.) = –2.0V for pulse width less than 10 ns.

CAPACITANCE(1)

Symbol

Parameter

Conditions

Max.

Unit

CIN

Input Capacitance

VIN = 0V

6

pF

 

 

 

 

 

COUT

Output Capacitance

VOUT = 0V

8

pF

 

 

 

 

 

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

4

Integrated Circuit Solution Inc.

LPSR025-0A 6/7/2002

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