IC62LV1024AL
IC62LV1024ALL
Document Title
128K x 8 Ultra Low Power and Low VCC SRAM
Revision History
Revision No |
History |
Draft Date |
Remark |
0A |
Initial Draft |
September 13,2001 |
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc. |
1 |
LPSR017-0A 09/13/2001
IC62LV1024AL
IC62LV1024ALL
128K x 8 LOW POWER and LOW Vcc CMOS STATIC RAM
FEATURES
•Access times of 45, 55, and 70 ns
•Low active power: 60 mW (typical)
•Low standby power: 15 µW (typical) CMOS standby
•Low data retention voltage: 2V (min.)
•Available in Low Power (-L) and Ultra Low Power (-LL)
•Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications
•TTL compatible inputs and outputs
•Single 2.7V to 3.3V power supply
DESCRIPTION
The ICSI IC62LV1024AL and IC62LV1024ALL are low power and low Vcc,131,072-word by 8-bit CMOS static RAMs. They arefabricatedusingICSI'shigh-performanceCMOStechnology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices.
When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory.
The IC62LV1024AL and IC62LV1024ALL are available in 32-pin 8*20mm TSOP-1, 8*13.4mm TSOP-1, 450mil SOP and 48-pin 6*8mm TF-BGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A16 |
DECODER |
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512 X 2048 |
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MEMORY ARRAY |
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VCC
GND
I/O
I/O0-I/O7 DATA COLUMN I/O
CIRCUIT
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CE1 |
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CONTROL |
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CE2 |
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CIRCUIT |
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OE |
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WE |
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ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2 |
Integrated Circuit Solution Inc. |
LPSR017-0A 09/13/2001
IC62LV1024AL
IC62LV1024ALL
PIN CONFIGURATION |
PIN CONFIGURATION |
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32-Pin SOP |
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32-Pin 8x20mm TSOP-1 and 8x13.4mm TSOP-1 |
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NC |
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1 |
32 |
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VCC |
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A11 |
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1 |
32 |
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31 |
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A15 |
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OE |
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A16 |
2 |
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A9 |
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2 |
31 |
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A10 |
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30 |
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CE2 |
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A14 |
3 |
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A8 |
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3 |
30 |
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CE1 |
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A12 |
4 |
29 |
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WE |
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A13 |
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4 |
29 |
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I/O7 |
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28 |
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A13 |
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A7 |
5 |
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28 |
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I/O6 |
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WE |
5 |
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27 |
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A8 |
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A6 |
6 |
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27 |
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I/O5 |
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26 |
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A9 |
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CE2 |
6 |
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A5 |
7 |
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26 |
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I/O4 |
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25 |
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A11 |
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A15 |
7 |
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A4 |
8 |
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VCC |
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8 |
25 |
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I/O3 |
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A3 |
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24 |
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OE |
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NC |
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9 |
24 |
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GND |
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A2 |
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10 |
23 |
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A10 |
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A16 |
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23 |
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I/O2 |
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A1 |
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11 |
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CE1 |
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A14 |
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I/O1 |
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A0 |
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I/O7 |
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12 |
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A12 |
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I/O0 |
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I/O0 |
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I/O6 |
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A7 |
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A0 |
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I/O1 |
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I/O5 |
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A6 |
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A1 |
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I/O2 |
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18 |
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I/O4 |
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A5 |
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A2 |
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GND |
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I/O3 |
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A4 |
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A3 |
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48-Pin 6x8mm TF-BGA |
PIN DESCRIPTIONS |
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1 |
2 |
3 |
4 |
5 |
6 |
A |
A0 |
A1 |
CE2 |
A3 |
A6 |
A8 |
B |
I/O5 |
A2 |
WE |
A4 |
A7 |
I/O1 |
C |
I/O6 |
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NC |
A5 |
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I/O2 |
D |
GND |
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Vcc |
E |
Vcc |
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GND |
F |
I/O7 |
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NC |
NC |
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I/O3 |
G |
I/O8 |
OE |
CE1 |
A16 |
A15 |
I/O4 |
H |
A9 |
A10 |
A11 |
A12 |
A13 |
A14 |
A0-A16 |
Address Inputs |
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CE1 |
Chip Enable 1 Input |
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CE2 |
Chip Enable 2 Input |
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OE |
Output Enable Input |
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WE |
Write Enable Input |
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I/O0-I/O7 |
Input/Output |
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NC |
No Connection |
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Vcc |
Power |
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GND |
Ground |
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OPERATING RANGE
Range |
Ambient Temperature |
VCC |
Commercial |
0°C to +70°C |
2.7V to 3.3V |
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Industrial |
–40°C to +85°C |
2.7V to 3.3V |
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Integrated Circuit Solution Inc. |
3 |
LPSR017-0A 09/13/2001
IC62LV1024AL
IC62LV1024ALL
TRUTH TABLE
Mode |
WE |
CE1 |
CE2 |
OE |
I/O Operation |
Vcc Current |
Not Selected |
X |
H |
X |
X |
High-Z |
ISB1, ISB2 |
(Power-down) |
X |
X |
L |
X |
High-Z |
ISB1, ISB2 |
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Output Disabled |
H |
L |
H |
H |
High-Z |
ICC |
Read |
H |
L |
H |
L |
DOUT |
ICC |
Write |
L |
L |
H |
X |
DIN |
ICC |
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ABSOLUTE MAXIMUM RATINGS(1)
Symbol |
Parameter |
Value |
Unit |
VTERM |
Terminal Voltage with Respect to GND |
–0.5 to +3.6 |
V |
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VCC |
Vcc related to GND |
–0.3 to +3.6 |
V |
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TBIAS |
Temperature Under Bias |
–40 to +85 |
°C |
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TSTG |
Storage Temperature |
–65 to +150 |
°C |
PT |
Power Dissipation |
0.7 |
W |
Notes:
1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol |
Parameter |
Conditions |
Max. |
Unit |
CIN |
Input Capacitance |
VIN = 0V |
6 |
pF |
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COUT |
Output Capacitance |
VOUT = 0V |
8 |
pF |
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Notes:
1.Tested initially and after any design or process changes that may affect these parameters.
2.Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.0V.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol |
Parameter |
Test Conditions |
Min. |
Max. |
Unit |
VOH |
Output HIGH Voltage |
VCC = Min., IOH = –1.0 mA |
2.2 |
— |
V |
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VOL |
Output LOW Voltage |
VCC = Min., IOL = 2.1 mA |
— |
0.4 |
V |
VIH |
Input HIGH Voltage |
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2.2 |
VCC + 0.3 |
V |
VIL |
Input LOW Voltage(1) |
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–0.3 |
0.4 |
V |
ILI |
Input Leakage |
GND ≤ VIN ≤ VCC |
–1 |
1 |
µA |
ILO |
Output Leakage |
GND ≤ VOUT ≤ VCC |
–1 |
1 |
µA |
Notes:
1. VIL = –3.0V for pulse width less than 10 ns.
4 |
Integrated Circuit Solution Inc. |
LPSR017-0A 09/13/2001