IC62C1024AL
Document Title
128K x 8 Low Power CMOS SRAM
Revision History
Revision No |
History |
Draft Date |
Remark |
0A |
Initial Draft |
May 7,2002 |
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The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc. |
1 |
ALSR009-0A 5/7/2002
IC62C1024AL
128K x 8 LOW POWER CMOS STATIC RAM
FEATURES
•High-speed access time: 35, 45, 55, 70 ns
•Low active power: 450 mW (typical)
•Low standby power: 150 µW (typical) CMOS standby
•Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications
•Fully static operation: no clock or refresh required
DESCRIPTION
The ICSI IC62C1024AL is a low power,131,072-word by 8-bit CMOS static RAM. It is fabricated using ICSI's highperformance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices.
When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels.
•TTL compatible inputs and outputs
•Single 5V (±10%) power supply
Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory.
The IC62C1024L is available in 32-pin 600mil DIP, 450mil SOP and 8*20mm TSOP-1 packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A16 |
DECODER |
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512 x 2048 |
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MEMORY ARRAY |
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VCC
GND
I/O
I/O0-I/O7 DATA COLUMN I/O
CIRCUIT
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CE1 |
CONTROL |
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CE2 |
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CIRCUIT |
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OE |
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WE |
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ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
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Integrated Circuit Solution Inc. |
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ALSR009-0A 5/7/2002 |
IC62C1024AL
PIN CONFIGURATION |
PIN CONFIGURATION |
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32-Pin SOP and DIP |
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32-Pin 8x20mm TSOP-1 |
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NC |
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1 |
32 |
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VCC |
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A16 |
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2 |
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A15 |
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A11 |
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1 |
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OE |
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A9 |
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A10 |
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A14 |
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CE2 |
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A8 |
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CE1 |
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A12 |
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WE |
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I/O7 |
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A13 |
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A7 |
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A13 |
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I/O6 |
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A6 |
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A8 |
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WE |
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I/O5 |
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A5 |
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A9 |
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CE2 |
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I/O4 |
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A4 |
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A11 |
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A15 |
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VCC |
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I/O3 |
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A3 |
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OE |
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NC |
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GND |
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A10 |
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A2 |
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10 |
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A16 |
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I/O2 |
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A1 |
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CE1 |
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A14 |
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I/O1 |
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I/O7 |
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A0 |
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A12 |
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I/O0 |
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I/O0 |
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I/O6 |
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A7 |
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A0 |
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I/O1 |
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I/O5 |
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A6 |
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A1 |
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I/O2 |
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I/O4 |
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A5 |
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A2 |
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GND |
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I/O3 |
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A4 |
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A3 |
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PIN DESCRIPTIONS |
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A0-A16 |
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Address Inputs |
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CE1 |
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Chip Enable 1 Input |
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CE2 |
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Chip Enable 2 Input |
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OE |
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Output Enable Input |
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WE |
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Write Enable Input |
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I/O0-I/O7 |
Input/Output |
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Vcc |
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Power |
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GND |
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Ground |
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OPERATING RANGE
Range |
Ambient Temperature |
VCC |
Commercial |
0°C to + 70°C |
5V ± 10% |
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Industrial |
–40°C to + 85°C |
5V ± 10% |
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TRUTH TABLE
Mode |
WE |
CE1 |
CE2 |
OE |
I/O Operation |
Vcc Current |
Not Selected |
X |
H |
X |
X |
High-Z |
ISB1, ISB2 |
(Power-down) |
X |
X |
L |
X |
High-Z |
ISB1, ISB2 |
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Output Disabled |
H |
L |
H |
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High-Z |
ICC |
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Read |
H |
L |
H |
L |
DOUT |
ICC |
Write |
L |
L |
H |
X |
DIN |
ICC |
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Integrated Circuit Solution Inc. |
3 |
ALSR009-0A 5/7/2002