IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
Document Title
8Mb SyncBurst Flow through SRAM
Revision History |
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Revision No |
History |
Draft Date |
Remark |
0A |
Initial Draft |
September 3,2002 |
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The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc. |
1 |
SSR020-0A 9/03/2002
IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
256K x 32, 256K x 36, 512K x 18
8Mb SYNCBURST Flow throughSRAMs
FEATURES
•Flowthrough Mode operation.
•User-selectable Output Drive Strength with XQ Mode.
•Internal self-timed write cycle
•Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and control
•Pentium™ or linear burst sequence control using MODE input
•Common data inputs and data outputs
•JEDEC 100-Pin TQFP and 119-pin PBGA package
•Single +3.3V, +10%, –5% core power supply
•Power-down snooze mode
•2.5V or 3.3V I/O Supply
•Snooze MODE for reduced-power standby
•T version (three chip selects)
•D version (two chip selects)
FAST ACCESS TIME
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Symbol |
-6.5 |
-7.5 |
-8.5 |
-9.5 |
Units |
Flow |
tKQ |
6.5 |
7.5 |
8.5 |
9.5 |
ns |
Through |
tKC |
7.5 |
8.5 |
10 |
11 |
ns |
2-1-1-1 |
ICC1 |
270 |
260 |
240 |
230 |
mA |
DESCRIPTION
ICSI's 8Mb SyncBurst Flowthrough SRAMs integrate a 512k x 18, 256k x 32, or 256k x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter.
Applications
The ICSI SyncBurst Flowthrough SRAM family employs high- speed ,low-power CMOS designs that are fabricated using an advanced CMOS process to provide Level 2 Cache applications supporting Pentium and PowerPC microprocessors originally, the device now finds application ranging from DSP
main store to networking chip set support.
Controls
All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied
HIGH or left floating.
Byte Write and Global Write
Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs.Separate byte enables allow individual bytes to be written. Byte write operation is performed by using byte write enable (BWE).input combined with one or more individualbyte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time,
regardless of the byte write controls.
IOL/IOH Drive strength Options
The XQ pin allows selection between high drive strength (XQ low) for multi-drop bus applications and normal drive strength (XQ floating or high) point-to-point applications. See the Output
Driver Characteristics chart for details.
Snooze Mode
Low power (Snooze mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Snooze mode.
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2 |
Integrated Circuit Solution Inc. |
SSR020-0A 9/03/2002
IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
BLOCK DIAGRAM
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MODE |
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Q0 |
A0' |
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CLK |
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CLK |
A0 |
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BINARY |
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COUNTER |
A1' |
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ADV |
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Q1 |
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A1 |
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ADSC |
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256Kx32; 256Kx36; |
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512Kx18 |
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ADSP |
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MEMORY ARRAY |
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18/19 |
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18/19 |
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An-A0 |
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ADDRESS |
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REGISTER |
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CLK |
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32, 36, |
32, 36, |
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or 18 |
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GW |
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DQd |
Q |
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BWE |
BYTE WRITE |
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BWd |
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REGISTERS |
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CLK |
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DQc |
Q |
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BWb |
BYTE WRITE |
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REGISTERS |
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CLK |
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D |
DQb |
Q |
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BWa |
BYTE WRITE |
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REGISTERS |
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CLK |
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D |
DQa |
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BWa |
BYTE WRITE |
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REGISTERS |
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CLK |
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(T, D)CE |
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32, 36, |
(T, D) CE2 |
D |
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Q |
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INPUT |
OUTPUT |
or 18 |
(T) CE2 |
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ENABLE |
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REGISTERS |
REGISTERS |
DQa - DQd |
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OE |
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CLK |
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CLK |
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Q |
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ENABLE |
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DELAY |
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REGISTER |
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Integrated Circuit Solution Inc. |
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3 |
SSR020-0A 9/03/2002 |
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IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
PIN CONFIGURATION
119-pin PBGA (Top View) |
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100-Pin TQFP (D Version) |
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1 |
2 |
3 |
4 |
5 |
6 |
7 |
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SA |
SA CE |
CE2 |
BWd BWc BWb |
BWa |
SA VCC |
GND CLK GW |
BWE |
OE |
ADSC ADSP ADV SA SA |
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A |
SA |
SA |
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SA |
SA |
VCCQ |
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100 |
99 98 97 |
96 95 94 93 |
92 91 90 89 88 87 86 |
85 84 83 82 81 |
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VCCQ |
ADSP |
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NC |
1 |
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80 |
NC |
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B |
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CE2 |
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SA |
NC |
DQc1 |
2 |
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79 |
DQb8 |
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ADSC |
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DQc2 |
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DQb7 |
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C |
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SA |
SA |
VCC |
SA |
SA |
NC |
VCCQ |
4 |
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77 |
VCCQ |
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GND |
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GND |
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D |
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NC |
GND |
XQ |
GND |
NC |
DQb8 |
DQc3 |
6 |
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75 |
DQb6 |
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DQc1 |
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DQc4 |
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DQb5 |
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E |
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DQc3 |
GND |
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GND |
DQb6 |
DQb7 |
DQc5 |
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DQb4 |
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DQc2 |
CE |
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DQc6 |
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DQb3 |
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DQc4 |
GND |
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GND |
DQb5 |
VCCQ |
GND |
10 |
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71 |
GND |
VCCQ |
OE |
VCCQ |
11 |
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VCCQ |
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G |
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DQc6 |
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DQb4 |
DQb3 |
DQc7 |
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DQb2 |
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DQc5 |
BWc |
ADV |
BWb |
DQc8 |
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DQb1 |
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DQc8 |
GND |
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GND |
DQb2 |
DQb1 |
GND/NC |
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GND |
DQc7 |
GW |
VCC |
15 |
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NC |
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VCC |
NC |
VCC |
NC |
VCC |
VCCQ |
XQ |
16 |
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65 |
VCC |
VCCQ |
GND |
17 |
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ZZ |
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K |
DQd2 |
GND |
CLK |
GND |
DQa7 |
DQa8 |
DQd1 |
18 |
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DQa8 |
DQd1 |
DQd2 |
19 |
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DQa7 |
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L |
DQd3 |
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DQa5 |
DQa6 |
VCCQ |
20 |
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VCCQ |
DQd4 |
BWd |
NC |
BWa |
GND |
21 |
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GND |
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M |
DQd5 |
GND |
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GND |
DQa4 |
VCCQ |
DQd3 |
22 |
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DQa6 |
VCCQ |
BWE |
DQd4 |
23 |
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DQa5 |
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N |
DQd7 |
GND |
A1 |
GND |
DQa3 |
DQa2 |
DQd5 |
24 |
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57 |
DQa4 |
DQd6 |
DQd6 |
25 |
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56 |
DQa3 |
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P |
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GND |
26 |
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55 |
GND |
DQd8 |
NC |
GND |
A0 |
GND |
NC |
DQa1 |
VCCQ |
27 |
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54 |
VCCQ |
R |
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DQd7 |
28 |
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53 |
DQa2 |
NC |
SA |
MODE |
VCC |
GND/NC |
SA |
NC |
DQd8 |
29 |
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52 |
DQa1 |
T |
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NC |
30 |
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34 35 36 37 38 39 40 |
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51 |
NC |
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NC |
SA |
SA |
SA |
NC |
ZZ |
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31 32 33 |
41 42 43 44 45 46 47 48 49 50 |
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U |
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MODE |
SA SA SA SA A1 A0 |
NC NC GND VCC NC NC |
A10 |
SA SA SA SA SA SA |
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VCCQ |
NC |
NC |
NC |
NC |
NC |
VCCQ |
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Note:Ball R5 no connection is acceptable |
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256K x 32 |
Note:Pin 14 no connection is acceptable |
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PIN DESCRIPTIONS
A0, A1 |
Synchronous Address Inputs. These |
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pins must tied to the two LSBs of the |
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address bus. |
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A2-A17 |
Synchronous Address Inputs |
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CLK |
Synchronous Clock |
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ADSP |
Synchronous Processor Address |
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Status |
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ADSC |
Synchronous Controller Address |
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Status |
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ADV |
Synchronous Burst Address Advance |
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BWa -BWd |
Synchronous Byte Write Enable |
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BWE |
Synchronous Byte Write Enable |
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GW |
Synchronous Global Write Enable |
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CE , CE2 |
Synchronous Chip Enable |
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OE |
Output Enable |
DQa-DQd |
Synchronous Data Input/Output |
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MODE |
Burst Sequence Mode Selection |
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XQ |
Output Drive Control |
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VCC |
+3.3V Power Supply |
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GND |
Ground |
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VCCQ |
Isolated Output Buffer Supply : +3.3V |
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or 2.5V |
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ZZ |
Snooze Enable |
4 |
Integrated Circuit Solution Inc. |
SSR020-0A 9/03/2002
IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
PIN CONFIGURATION
100-Pin TQFP (T Version)
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SA |
SA |
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CE |
CE2 |
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BWd |
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BWc |
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BWb |
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BWa |
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CE2 VCC |
GND CLK |
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GW |
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BWE |
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OE |
ADSC |
ADSP |
ADV SA SA |
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100 99 98 97 |
96 95 94 93 |
92 91 90 89 88 87 86 |
85 84 83 82 81 |
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NC |
1 |
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80 |
NC |
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DQc1 |
2 |
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79 |
DQb8 |
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DQc2 |
3 |
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78 |
DQb7 |
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VCCQ |
4 |
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77 |
VCCQ |
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GND |
5 |
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76 |
GND |
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DQc3 |
6 |
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DQb6 |
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DQc4 |
7 |
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74 |
DQb5 |
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DQc5 |
8 |
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73 |
DQb4 |
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DQc6 |
9 |
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72 |
DQb3 |
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GND |
10 |
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71 |
GND |
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VCCQ |
11 |
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70 |
VCCQ |
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DQc7 |
12 |
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69 |
DQb2 |
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DQc8 |
13 |
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68 |
DQb1 |
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GND/NC |
14 |
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67 |
GND |
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VCC |
15 |
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66 |
NC |
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XQ |
16 |
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65 |
VCC |
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GND |
17 |
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64 |
ZZ |
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DQd1 |
18 |
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63 |
DQa8 |
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DQd2 |
19 |
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62 |
DQa7 |
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VCCQ |
20 |
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61 |
VCCQ |
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GND |
21 |
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60 |
GND |
||
DQd3 |
22 |
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59 |
DQa6 |
||
DQd4 |
23 |
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58 |
DQa5 |
||
DQd5 |
24 |
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57 |
DQa4 |
||
DQd6 |
25 |
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56 |
DQa3 |
||
GND |
26 |
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55 |
GND |
||
VCCQ |
27 |
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54 |
VCCQ |
||
DQd7 |
28 |
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53 |
DQa2 |
||
DQd8 |
29 |
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52 |
DQa1 |
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NC |
30 |
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51 |
NC |
||
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31 32 33 |
34 35 36 37 38 39 40 |
41 42 43 44 45 46 47 48 49 50 |
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||||||||||||||||||||||
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MODE |
SA SA SA SA A1 A0 NC NC GND VCC NC SA SA SA SA SA SA SA SA |
|
|||||||||||||||||||||||
Note:Pin 14 no connection is acceptable |
|
|
256K x 32 |
|
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|
|
PIN DESCRIPTIONS
A0, A1 |
Synchronous Address Inputs. These |
|
pins must tied to the two LSBs of the |
|
address bus. |
|
|
A2-A17 |
Synchronous Address Inputs |
|
|
CLK |
Synchronous Clock |
|
|
ADSP |
Synchronous Processor Address |
|
Status |
|
|
ADSC |
Synchronous Controller Address |
|
Status |
|
|
ADV |
Synchronous Burst Address Advance |
|
|
BWa -BWd |
Synchronous Byte Write Enable |
|
|
BWE |
Synchronous Byte Write Enable |
|
|
GW |
Synchronous Global Write Enable |
|
|
CE,CE2,CE2 |
Synchronous Chip Enable |
|
|
OE |
Output Enable |
DQa-DQd |
Synchronous Data Input/Output |
|
|
MODE |
Burst Sequence Mode Selection |
|
|
XQ |
Output Drive Control |
|
|
VCC |
+3.3V Power Supply |
|
|
GND |
Ground |
|
|
VCCQ |
Isolated Output Buffer Supply : +3.3V |
|
or 2.5V |
|
|
ZZ |
Snooze Enable |
Integrated Circuit Solution Inc. |
5 |
SSR020-0A 9/03/2002
IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
PIN CONFIGURATION
119-pin PBGA (Top View) |
|
|
100-Pin TQFP (D Version) |
|
||||||||||||
1 |
2 |
3 |
4 |
5 |
6 |
7 |
|
SA |
SA CE |
CE2 |
BWd BWc BWb BWa |
A17 VCC |
GND |
CLK GW BWE OE |
ADSC ADSP ADV SA SA |
|
A |
SA |
SA |
ADSP |
SA |
SA |
VCCQ |
|
100 99 98 97 |
96 95 94 93 |
92 91 90 89 88 87 86 |
85 84 83 82 81 |
|
||||
VCCQ |
DQPc |
1 |
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|
80 |
DQPb |
||||||
B |
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|
||||
CE2 |
SA |
ADSC |
SA |
SA |
NC |
DQc1 |
2 |
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|
79 |
DQb8 |
|
NC |
DQc2 |
3 |
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78 |
DQb7 |
||||||
C |
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||||
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|
VCC |
SA |
SA |
NC |
VCCQ |
4 |
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|
77 |
VCCQ |
|
NC |
SA |
SA |
|
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|
||||||||
GND |
5 |
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|
76 |
GND |
|||||||
D |
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||||
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DQc3 |
6 |
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|
75 |
DQb6 |
|
DQc1 |
DQPc |
GND |
XQ |
GND |
DQPb |
DQb8 |
|
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|
||||
DQc4 |
7 |
|
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|
74 |
DQb5 |
|||||||
E |
|
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||||
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GND |
DQb6 |
DQb7 |
DQc5 |
8 |
|
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|
73 |
DQb4 |
|
DQc2 |
DQc3 |
GND |
CE |
|
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|
|||||||
DQc6 |
9 |
|
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|
72 |
DQb3 |
|||||||
F |
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||||
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GND |
10 |
|
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|
71 |
GND |
|
VCCQ |
DQc4 |
GND |
OE |
GND |
DQb5 |
VCCQ |
|
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|
||||
VCCQ |
11 |
|
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|
70 |
VCCQ |
|||||||
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|||||
G |
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||||
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DQb4 |
DQb3 |
DQc7 |
12 |
|
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|
69 |
DQb2 |
|
DQc5 |
DQc6 |
BWc |
ADV |
BWb |
|
|
|
|
|
|
||||||
DQc8 |
13 |
|
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|
68 |
DQb1 |
|||||||
H |
|
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|
||||
|
|
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|
|
GND/NC |
14 |
|
|
|
|
|
|
67 |
GND |
|
DQc7 |
DQc8 |
GND |
GW |
GND |
DQb2 |
DQb1 |
|
|
|
|
|
|
||||
VCC |
15 |
|
|
|
|
|
|
66 |
NC |
|||||||
J |
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
VCC |
NC |
VCC |
VCCQ |
XQ |
16 |
|
|
|
|
|
|
65 |
VCC |
|
VCCQ |
VCC |
NC |
|
|
|
|
|
|
||||||||
K |
|
|
|
|
|
|
GND |
17 |
|
|
|
|
|
|
64 |
ZZ |
|
|
|
|
|
|
DQd1 |
18 |
|
|
|
|
|
|
63 |
DQa8 |
|
DQd1 |
DQd2 |
GND |
CLK |
GND |
DQa7 |
DQa8 |
|
|
|
|
|
|
||||
L |
|
|
|
|
|
|
DQd2 |
19 |
|
|
|
|
|
|
62 |
DQa7 |
|
|
NC |
BWa |
DQa5 |
DQa6 |
VCCQ |
20 |
|
|
|
|
|
|
61 |
VCCQ |
|
DQd4 |
DQd3 |
BWd |
|
|
|
|
|
|
||||||||
M |
|
|
|
|
|
|
GND |
21 |
|
|
|
|
|
|
60 |
GND |
|
|
|
|
|
|
DQd3 |
22 |
|
|
|
|
|
|
59 |
DQa6 |
|
VCCQ |
DQd5 |
GND |
BWE |
GND |
DQa4 |
VCCQ |
|
|
|
|
|
|
||||
N |
|
|
|
|
|
|
DQd4 |
23 |
|
|
|
|
|
|
58 |
DQa5 |
DQd6 |
DQd7 |
GND |
A1 |
GND |
DQa3 |
DQa2 |
DQd5 |
24 |
|
|
|
|
|
|
57 |
DQa4 |
P |
|
|
|
|
|
|
DQd6 |
25 |
|
|
|
|
|
|
56 |
DQa3 |
DQd8 |
DQPd |
GND |
A0 |
GND |
DQPa |
DQa1 |
GND |
26 |
|
|
|
|
|
|
55 |
GND |
R |
|
|
|
|
|
|
VCCQ |
27 |
|
|
|
|
|
|
54 |
VCCQ |
NC |
SA |
MODE |
VCC |
GND/NC |
SA |
NC |
DQd7 |
28 |
|
|
|
|
|
|
53 |
DQa2 |
T |
|
|
|
|
|
|
DQd8 |
29 |
|
|
|
|
|
|
52 |
DQa1 |
NC |
NC |
SA |
SA |
SA |
NC |
ZZ |
DQPd |
30 |
|
|
|
|
|
|
51 |
DQPa |
U |
|
|
|
|
|
|
|
31 32 33 |
34 35 36 37 38 39 40 |
41 42 43 44 45 46 47 48 49 50 |
|
|||||
VCCQ |
NC |
NC |
NC |
NC |
NC |
VCCQ |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
MODE |
SA SA SA SA A1 A0 NC NC GND VCC |
NC NC SA SA SA SA SA SA SA |
|
|||||
Note:Ball R5 no connection is acceptable |
256K x 36 |
Note:Pin 14 no connection is acceptable |
|
PIN DESCRIPTIONS
A0, A1 |
Synchronous Address Inputs. These |
|
pins must tied to the two LSBs of the |
|
address bus. |
|
|
A2-A17 |
Synchronous Address Inputs |
|
|
CLK |
Synchronous Clock |
|
|
ADSP |
Synchronous Processor Address |
|
Status |
|
|
ADSC |
Synchronous Controller Address |
|
Status |
|
|
ADV |
Synchronous Burst Address Advance |
|
|
BWa -BWd |
Synchronous Byte Write Enable |
|
|
BWE |
Synchronous Byte Write Enable |
|
|
GW |
Synchronous Global Write Enable |
|
|
CE , CE2 |
Synchronous Chip Enable |
|
|
OE |
Output Enable |
DQa-DQd |
Synchronous Data Input/Output |
|
|
MODE |
Burst Sequence Mode Selection |
|
|
XQ |
Output Drive Control |
|
|
VCC |
+3.3V Power Supply |
|
|
GND |
Ground |
|
|
VCCQ |
Isolated Output Buffer Supply : +3.3V |
|
or 2.5V |
|
|
ZZ |
Snooze Enable |
|
|
DQPa-DQPd |
Parity Data I/O |
6 |
Integrated Circuit Solution Inc. |
SSR020-0A 9/03/2002