IC61SF12832
IC61SF12836
Document Title
128K x 32 Flow Through SyncBurst SRAM
Revision History
Revision No |
History |
Draft Date |
Remark |
0A |
Initial Draft |
September 17,2001 |
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc. |
1 |
SSR018-0A 09/17/2001
IC61SF12832
IC61SF12836
128K x 32, 128K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM
FEATURES
•Fast access times: 7.5 ns, 8 ns, 8.5 ns, 10 ns, and 12 ns
•Internal self-timed write cycle
•Individual Byte Write Control and Global Write
•Clock controlled, registered address, data inputs and control signals
•PentiumTM or linear burst sequence control using MODE input
•Three chip enables for simple depth expansion and address pipelining
•Common data inputs and data outputs
•100-Pin TQFP (JEDEC LQFP) and
119-pin PBGA package
•Single +3.3V +10%, -5% power supply
•Power-down snooze mode
DESCRIPTION
The ICSI IC61SF12832 and IC61SF12836 are high-speed synchronous static RAM designed to provide a burstable, highperformance for high speed networking and communication applications. It is organized as 131,072 words by 32 bits or 36 bits, fabricated with ICSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written. BW1 controls DQa, BW2 controls DQb, BW3 controls DQc, BW4 controls DQd, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IC61SF12832 and controlled by the ADV (burst address advance) input pin.
The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol |
Parameter |
7.5 |
8 |
8.5 |
10 |
12 |
Units |
tKQ |
Clock Access Time |
7.5 |
8 |
8.5 |
10 |
12 |
ns |
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tKC |
Cycle Time |
8.5 |
10 |
11 |
15 |
15 |
ns |
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Frenquency |
117 |
100 |
90 |
66 |
66 |
MHz |
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ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2 |
Integrated Circuit Solution Inc. |
SSR018-0A 09/17/2001
IC61SF12832
IC61SF12836
BLOCK DIAGRAM
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MODE |
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CLK |
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CLK |
Q0 |
A0 |
A0’ |
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BINARY |
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COUNTER |
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A1’ |
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ADV |
CE |
Q1 |
A1 |
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128K x 32, 128K x 36 |
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ADSC |
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CLR |
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MEMORY ARRAY |
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ADSP |
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A16-A0 |
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Q |
15 |
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D |
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ADDRESS |
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REGISTER |
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CE |
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CLK |
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32 |
32 |
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or |
or |
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36 |
36 |
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GW |
D |
DQd |
Q |
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BWE |
BYTE WRITE |
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BW4 |
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REGISTERS |
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CLK |
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D |
DQc |
Q |
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BW3 |
BYTE WRITE |
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CLK |
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D |
DQb |
Q |
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BW2 |
BYTE WRITE |
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REGISTERS |
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CLK |
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D |
DQa |
Q |
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BW1 |
BYTE WRITE |
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CLK |
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CE |
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4 |
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CE2 |
D |
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Q |
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INPUT |
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32 or 36 |
CE2 |
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ENABLE |
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REGISTERS |
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DQ[31:0] or |
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OE |
DQ[35:0] |
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CE |
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CLK |
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D |
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Q |
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ENABLE |
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DELAY |
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REGISTER |
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OE |
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Integrated Circuit Solution Inc. |
3 |
SSR018-0A 09/17/2001
IC61SF12832
IC61SF12836
PIN CONFIGURATION
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119-pin PBGA (Top View) |
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100-Pin LQFP |
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1 |
2 |
3 |
4 |
5 |
6 |
7 |
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A6 |
A7 CE |
CE2 |
BW4 |
BW3 BW2 BW1 CE2 VCC |
GND CLK GW BWE OE |
ADSC |
ADSP |
ADV |
A8 |
A9 |
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A |
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100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 |
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VCCQ |
A6 |
A4 |
ADSP |
A8 |
A16 |
VCCQ |
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B |
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NC |
1 |
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80 |
NC |
NC |
CE2 |
A3 |
ADSC |
A9 |
CE2 |
NC |
DQc1 |
2 |
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79 |
DQb8 |
C |
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DQc2 |
3 |
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78 |
DQb7 |
NC |
A7 |
A2 |
VCC |
A12 |
A15 |
NC |
VCCQ |
4 |
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77 |
VCCQ |
D |
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GND |
5 |
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76 |
GND |
DQc1 |
NC |
GND |
NC |
GND |
NC |
DQb8 |
DQc3 |
6 |
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75 |
DQb6 |
E |
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DQc4 |
7 |
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74 |
DQb5 |
DQc2 |
DQc3 |
GND |
CE |
GND |
DQb6 |
DQb7 |
DQc5 |
8 |
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73 |
DQb4 |
F |
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DQc6 |
9 |
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72 |
DQb3 |
VCCQ |
DQc4 |
GND |
OE |
GND |
DQb5 |
VCCQ |
GND |
10 |
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71 |
GND |
G |
DQc6 |
BW3 |
ADV |
BW2 |
DQb4 |
DQb3 |
VCCQ |
11 |
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70 |
VCCQ |
DQc5 |
DQc7 |
12 |
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69 |
DQb2 |
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H |
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DQc8 |
GND |
GW |
GND |
DQb2 |
DQb1 |
DQc8 |
13 |
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68 |
DQb1 |
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DQc7 |
GNDQ |
14 |
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67 |
GND |
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J |
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VCC |
NC |
VCC |
NC |
VCC |
VCCQ |
VCC |
15 |
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66 |
NC |
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VCCQ |
NC |
16 |
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65 |
VCC |
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K |
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DQd2 |
GND |
CLK |
GND |
DQa7 |
DQa8 |
GND |
17 |
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64 |
ZZ |
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DQd1 |
DQd1 |
18 |
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63 |
DQa8 |
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L |
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DQd2 |
19 |
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62 |
DQa7 |
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DQd4 |
DQd3 |
BW4 |
NC |
BW1 |
DQa5 |
DQa6 |
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VCCQ |
20 |
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61 |
VCCQ |
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M |
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GND |
21 |
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60 |
GND |
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VCCQ |
DQd5 |
GND |
BWE |
GND |
DQa4 |
VCCQ |
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DQd3 |
22 |
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59 |
DQa6 |
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N |
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DQd4 |
23 |
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58 |
DQa5 |
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DQd6 |
DQd7 |
GND |
A1 |
GND |
DQa3 |
DQa2 |
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DQd5 |
24 |
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57 |
DQa4 |
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P |
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DQd6 |
25 |
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56 |
DQa3 |
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DQd8 |
NC |
GND |
A0 |
GND |
NC |
DQa1 |
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GND |
26 |
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55 |
GND |
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R |
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VCCQ |
27 |
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54 |
VCC |
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NC |
A5 |
MODE |
VCC |
GND |
A13 |
NC |
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DQd7 |
28 |
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53 |
DQa2 |
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T |
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DQd8 |
29 |
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52 |
DQa1 |
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NC |
NC |
A10 |
A11 |
A14 |
NC |
ZZ |
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NC |
30 |
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51 |
NC |
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U |
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31 32 33 |
34 35 36 37 38 39 40 |
41 42 43 44 45 46 47 48 49 50 |
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VCCQ |
NC |
NC |
NC |
NC |
NC |
VCCQ |
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MODE |
A5 A4 |
A3 |
A2 |
A1 A0 NC NC GND |
VCC NC NC A10 A11 |
A12 |
A13 |
A14 |
A15 |
A16 |
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128K x 32 |
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PIN DESCRIPTIONS
A0, A1 |
Synchronous Address Inputs. These |
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pins must tied to the two LSBs of the |
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address bus. |
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A2-A16 |
Synchronous Address Inputs |
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CLK |
Synchronous Clock |
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ADSP |
Synchronous Processor Address |
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Status |
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ADSC |
Synchronous Controller Address |
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Status |
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ADV |
Synchronous Burst Address Advance |
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BW1-BW4 |
Synchronous Byte Write Enable |
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BWE |
Synchronous Byte Write Enable |
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GW |
Synchronous Global Write Enable |
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CE, CE2, CE2 |
Synchronous Chip Enable |
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OE |
Output Enable |
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DQa-DQd |
Synchronous Data Input/Output |
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MODE |
Burst Sequence Mode Selection |
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VCC |
+3.3V Power Supply |
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GND |
Ground |
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VCCQ |
Isolated Output Buffer Supply: |
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+3.3V |
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ZZ |
Snooze Enable |
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4 |
Integrated Circuit Solution Inc. |
SSR018-0A 09/17/2001
IC61SF12832
IC61SF12836
PIN CONFIGURATION
|
119-pin PBGA (Top View) |
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100-Pin LQFP |
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1 |
2 |
3 |
4 |
5 |
6 |
7 |
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A6 |
A7 CE |
CE2 BW4 |
BW3 BW2 BW1 CE2 VCC |
GND CLK GW BWE OE |
ADSC ADSP ADV |
A8 |
A9 |
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A |
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100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 |
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VCCQ |
A6 |
A4 |
ADSP |
A8 |
A16 |
VCCQ |
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B |
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DQPc |
1 |
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80 |
DQPb |
NC |
CE2 |
A3 |
ADSC |
A9 |
CE2 |
NC |
DQc1 |
2 |
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79 |
DQb8 |
C |
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DQc2 |
3 |
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78 |
DQb7 |
NC |
A7 |
A2 |
VCC |
A12 |
A15 |
NC |
VCCQ |
4 |
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77 |
VCCQ |
D |
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GND |
5 |
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76 |
GND |
DQc1 |
DQPc |
GND |
NC |
GND |
DQPb |
DQb8 |
DQc3 |
6 |
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75 |
DQb6 |
E |
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DQc4 |
7 |
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74 |
DQb5 |
DQc2 |
DQc3 |
GND |
CE |
GND |
DQb6 |
DQb7 |
DQc5 |
8 |
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73 |
DQb4 |
F |
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DQc6 |
9 |
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72 |
DQb3 |
VCCQ |
DQc4 |
GND |
OE |
GND |
DQb5 |
VCCQ |
GND |
10 |
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71 |
GND |
G |
DQc6 |
BW3 |
ADV |
BW2 |
DQb4 |
DQb3 |
VCCQ |
11 |
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70 |
VCCQ |
DQc5 |
DQc7 |
12 |
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69 |
DQb2 |
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H |
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DQc8 |
GND |
GW |
GND |
DQb2 |
DQb1 |
DQc8 |
13 |
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68 |
DQb1 |
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DQc7 |
GNDQ |
14 |
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67 |
GND |
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J |
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VCC |
NC |
VCC |
NC |
VCC |
VCCQ |
VCC |
15 |
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66 |
NC |
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VCCQ |
NC |
16 |
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65 |
VCC |
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K |
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DQd2 |
GND |
CLK |
GND |
DQa7 |
DQa8 |
GND |
17 |
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64 |
ZZ |
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DQd1 |
DQd1 |
18 |
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63 |
DQa8 |
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L |
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DQd2 |
19 |
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62 |
DQa7 |
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DQd4 |
DQd3 |
BW4 |
NC |
BW1 |
DQa5 |
DQa6 |
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VCCQ |
20 |
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61 |
VCCQ |
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M |
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GND |
21 |
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60 |
GND |
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VCCQ |
DQd5 |
GND |
BWE |
GND |
DQa4 |
VCCQ |
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DQd3 |
22 |
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59 |
DQa6 |
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N |
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DQd4 |
23 |
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58 |
DQa5 |
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DQd6 |
DQd7 |
GND |
A1 |
GND |
DQa3 |
DQa2 |
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DQd5 |
24 |
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57 |
DQa4 |
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P |
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DQd6 |
25 |
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56 |
DQa3 |
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DQd8 |
DQPd |
GND |
A0 |
GND |
DQPa |
DQa1 |
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GND |
26 |
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55 |
GND |
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R |
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VCCQ |
27 |
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54 |
VCC |
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NC |
A5 |
MODE |
VCC |
GND |
A13 |
NC |
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DQd7 |
28 |
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53 |
DQa2 |
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T |
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DQd8 |
29 |
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52 |
DQa1 |
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NC |
NC |
A10 |
A11 |
A14 |
NC |
ZZ |
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DQPd |
30 |
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51 |
DQPa |
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U |
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31 32 33 |
34 35 36 37 38 39 40 |
41 42 43 44 45 46 47 48 49 50 |
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VCCQ |
NC |
NC |
NC |
NC |
NC |
VCCQ |
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MODE |
A5 A4 |
A3 A2 |
A1 A0 NC NC GND |
VCC NC NC A10 A11 |
A12 A13 A14 |
A15 |
A16 |
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128K x 36 |
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PIN DESCRIPTIONS
A0, A1 |
Synchronous Address Inputs. These |
|
pins must tied to the two LSBs of the |
|
address bus. |
|
|
A2-A16 |
Synchronous Address Inputs |
|
|
CLK |
Synchronous Clock |
|
|
ADSP |
Synchronous Processor Address |
|
Status |
|
|
ADSC |
Synchronous Controller Address |
|
Status |
|
|
ADV |
Synchronous Burst Address Advance |
|
|
BW1-BW4 |
Synchronous Byte Write Enable |
|
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BWE |
Synchronous Byte Write Enable |
|
|
GW |
Synchronous Global Write Enable |
|
|
CE, CE2, CE2 |
Synchronous Chip Enable |
|
|
OE |
Output Enable |
|
|
DQa-DQd |
Synchronous Data Input/Output |
|
|
MODE |
Burst Sequence Mode Selection |
|
|
VCC |
+3.3V Power Supply |
|
|
GND |
Ground |
|
|
VCCQ |
Isolated Output Buffer Supply: |
|
+3.3V |
|
|
ZZ |
Snooze Enable |
|
|
DQPa-DQPd |
Parity Data I/O |
|
|
Integrated Circuit Solution Inc. |
5 |
SSR018-0A 09/17/2001
IC61SF12832
IC61SF12836
TRUTH TABLE
|
Address |
|
|
|
|
|
|
|
|
|
Operation |
Used |
CE |
CE2 |
CE2 |
ADSP |
ADSC |
ADV |
WRITE |
OE |
DQ |
Deselected, Power-down |
None |
H |
X |
X |
X |
L |
X |
X |
X |
High-Z |
|
|
|
|
|
|
|
|
|
|
|
Deselected, Power-down |
None |
L |
X |
H |
L |
X |
X |
X |
X |
High-Z |
|
|
|
|
|
|
|
|
|
|
|
Deselected, Power-down |
None |
L |
L |
X |
L |
X |
X |
X |
X |
High-Z |
|
|
|
|
|
|
|
|
|
|
|
Deselected, Power-down |
None |
X |
X |
H |
H |
L |
X |
X |
X |
High-Z |
|
|
|
|
|
|
|
|
|
|
|
Deselected, Power-down |
None |
X |
L |
X |
H |
L |
X |
X |
X |
High-Z |
|
|
|
|
|
|
|
|
|
|
|
Read Cycle, Begin Burst |
External |
L |
H |
L |
L |
X |
X |
X |
X |
High-Z |
Read Cycle, Begin Burst |
External |
L |
H |
L |
H |
L |
X |
Read |
X |
High-Z |
|
|
|
|
|
|
|
|
|
|
|
Write Cycle, Begin Burst |
External |
L |
H |
L |
H |
L |
X |
Write |
X |
High-Z |
|
|
|
|
|
|
|
|
|
|
|
Read Cycle, Continue Burst |
Next |
X |
X |
X |
H |
H |
L |
Read |
L |
Q |
|
|
|
|
|
|
|
|
|
|
|
Read Cycle, Continue Burst |
Next |
X |
X |
X |
H |
H |
L |
Read |
H |
High-Z |
|
|
|
|
|
|
|
|
|
|
|
Read Cycle, Continue Burst |
Next |
H |
X |
X |
X |
H |
L |
Read |
L |
Q |
|
|
|
|
|
|
|
|
|
|
|
Read Cycle, Continue Burst |
Next |
H |
X |
X |
X |
H |
L |
Read |
H |
High-Z |
Write Cycle, Continue Burst |
Next |
X |
X |
X |
H |
H |
L |
Write |
X |
High-Z |
|
|
|
|
|
|
|
|
|
|
|
Write Cycle, Continue Burst |
Next |
H |
X |
X |
X |
H |
L |
Write |
X |
High-Z |
|
|
|
|
|
|
|
|
|
|
|
Read Cycle, Suspend Burst |
Current |
X |
X |
X |
H |
H |
H |
Read |
L |
Q |
|
|
|
|
|
|
|
|
|
|
|
Read Cycle, Suspend Burst |
Current |
X |
X |
X |
H |
H |
H |
Read |
H |
High-Z |
|
|
|
|
|
|
|
|
|
|
|
Read Cycle, Suspend Burst |
Current |
H |
X |
X |
X |
H |
H |
Read |
L |
Q |
|
|
|
|
|
|
|
|
|
|
|
Read Cycle, Suspend Burst |
Current |
H |
X |
X |
X |
H |
H |
Read |
H |
High-Z |
Write Cycle, Suspend Burst |
Current |
X |
X |
X |
H |
H |
H |
Write |
X |
High-Z |
|
|
|
|
|
|
|
|
|
|
|
Write Cycle, Suspend Burst |
Current |
H |
X |
X |
X |
H |
H |
Write |
X |
High-Z |
|
|
|
|
|
|
|
|
|
|
|
PARTIAL TRUTH TABLE
Function |
GW |
BWE |
BW1 |
BW2 |
BW3 |
BW4 |
Read |
H |
H |
X |
X |
X |
X |
|
|
|
|
|
|
|
Read |
H |
L |
H |
H |
H |
H |
Write Byte 1 |
H |
L |
L |
H |
H |
H |
Write All Bytes |
H |
L |
L |
L |
L |
L |
|
|
|
|
|
|
|
Write All Bytes |
L |
X |
X |
X |
X |
X |
|
|
|
|
|
|
|
6 |
Integrated Circuit Solution Inc. |
SSR018-0A 09/17/2001