IC61LV256
Document Title
32K x 8 Hight Speed SRAM with 3.3V
Revision History
Revision No |
History |
Draft Date |
Remark |
0A |
Initial Draft |
April 19,2002 |
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The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc. |
1 |
AHSR027-0A 04/19/2002
IC61LV256
32K x 8 HIGH SPEED CMOS STATIC RAM
FEATURES
•High-speed access times:
--8, 10, 12, 15 ns
•Automatic power-down when chip is deselected
•CMOS low power operation
--345 mW (max.) operating
--7 mW (max.) CMOS standby
•TTL compatible interface levels
•Single 3.3V power supply
•Fully static operation: no clock or refresh required
•Three-state outputs
DESCRIPTION
The ICSI IC61LV256 is a very high-speed, low power, 32,768-word by 8-bit static RAM. It is fabricated using ICSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 8 ns maximum.
When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation is reduced to 600 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active LOW Chip Enable (CE). The active LOW Write Enable (WE) controls both writing and reading of the memory.
The IC61LV256 is available in the JEDEC standard 28-pin, 300mil SOJ and the 8*13.4mm TSOP-1 package.
FUNCTIONAL BLOCK DIAGRAM
A0-A14 |
DECODER |
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256 X 1024 |
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MEMORY ARRAY |
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VCC
GND
I/O
I/O0-I/O7 DATA COLUMN I/O
CIRCUIT
CE
CONTROL
OE CIRCUIT
WE
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
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Integrated Circuit Solution Inc. |
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AHSR027-0A 04/19/2002 |
IC61LV256
PIN CONFIGURATION |
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PIN CONFIGURATION |
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28-Pin SOJ |
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8x13.4mm TSOP-1 |
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A14 |
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28 |
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VCC |
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22 |
21 |
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A10 |
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A12 |
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27 |
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WE |
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OE |
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A11 |
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23 |
20 |
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A7 |
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3 |
26 |
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A13 |
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CE |
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A6 |
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4 |
25 |
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A8 |
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A9 |
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24 |
19 |
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I/O7 |
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A8 |
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25 |
18 |
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I/O6 |
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A5 |
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5 |
24 |
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A9 |
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17 |
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I/O5 |
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A4 |
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23 |
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A11 |
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A13 |
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16 |
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I/O4 |
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WE |
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22 |
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A3 |
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7 |
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OE |
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15 |
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I/O3 |
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VCC |
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A10 |
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A2 |
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8 |
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A14 |
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1 |
14 |
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GND |
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20 |
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A12 |
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I/O2 |
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A1 |
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9 |
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CE |
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A0 |
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10 |
19 |
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I/O7 |
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A7 |
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3 |
12 |
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I/O1 |
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A6 |
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4 |
11 |
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I/O0 |
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I/O0 |
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18 |
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I/O6 |
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A5 |
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10 |
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A0 |
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I/O1 |
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12 |
17 |
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I/O5 |
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A4 |
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A1 |
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I/O2 |
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16 |
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I/O4 |
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A3 |
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7 |
8 |
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A2 |
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GND |
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14 |
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I/O3 |
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PIN DESCRIPTIONS
A0-A14 |
Address Inputs |
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CE |
Chip Enable Input |
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OE |
Output Enable Input |
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WE |
Write Enable Input |
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I/O0-I/O7 |
Input/Output |
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Vcc |
Power |
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GND |
Ground |
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TRUTH TABLE
Mode |
WE |
CE |
OE |
I/O Operation |
Vcc Current |
Not Selected |
X |
H |
X |
High-Z |
ISB1, ISB2 |
(Power-down) |
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Output Disabled |
H |
L |
H |
High-Z |
ICC |
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Read |
H |
L |
L |
DOUT |
ICC |
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Write |
L |
L |
X |
DIN |
ICC |
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ABSOLUTE MAXIMUM RATINGS(1)
Symbol |
Parameter |
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Value |
Unit |
VCC |
Power Supply Voltage Relative to GND |
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–0.5 to +4.6 |
V |
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VTERM |
Terminal Voltage with Respect to GND |
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–0.5 to +4.6 |
V |
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TBIAS |
Temperature Under Bias |
Com. |
–10 to +85 |
°C |
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Ind. |
–45 to +90 |
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TSTG |
Storage Temperature |
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–65 to +150 |
°C |
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PD |
Power Dissipation |
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1 |
W |
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IOUT |
DC Output Current |
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±20 |
mA |
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Integrated Circuit Solution Inc. |
3 |
AHSR027-0A 04/19/2002