SERVICE
MANUAL
VHF TRANSCEIVER
INTRODUCTION
DANGER
ORDERING PARTS
REPAIR NOTES
This service manual describes the latest service information
for the
IC-F50/IC-F51 VHF TRANSCEIVER
at the time of
publication.
NEVER connect the transceiver to an AC outlet or to a DC
power supply that uses more than 8 V. Such a connection
could cause a fire or electric hazard.
DO NOT expose the transceiver to rain, snow or any liquids.
DO NOT reverse the polarities of the power supply when con-
necting the transceiver.
DO NOT apply an RF signal of more than 20 dBm (100mW)
to the antenna connector. This could damage the transceiver's front end.
Be sure to include the following four points when ordering
replacement parts:
1. 10-digit order numbers
2. Component part number and name
3. Equipment model name and unit name
4. Quantity required
<SAMPLE ORDER>
5030002630 LCD L3-0048TAY-2 IC-F50 Front unit 5 pieces
8810010120 Screw BO 2x8 SUS ZK IC-F50 Chassis 10 pieces
Addresses are provided on the inside back cover for your
convenience.
1. Make sure a problem is internal before disassembling the transceiver.
2. DO NOT open the transceiver until the transceiver is disconnected from its power source.
3. DO NOT force any of the variable components. Turn them slowly and smoothly.
4. DO NOT short any circuits or electronic parts. An insulated turning tool MUST be used for all adjustments.
5. DO NOT keep power ON for a long time when the transceiver is defective.
6. DO NOT transmit power into a signal generator or a sweep generator.
7. ALWAYS connect a 30 dB to 40 dB attenuator between the transceiver and a deviation meter or spectrum analyzer when
using such test equipment.
8. READ the instructions of test equipment thoroughly before connecting equipment to the transceiver.
To upgrade quality, all electrical or mechanical parts and
internal circuits are subject to change without notice or obligation.
MODEL VERSION SYMBOL
IC-F50
IC-F51
U.S.A
Europe
USA
GENGeneral
EUR
TABLE OF CONTENTS
SECTION 1 SPECIFICATIONS
SECTION 2 INSIDE VIEWS
SECTION 3 DISASSEMBLY INSTRUCTIONS
SECTION 4 CIRCUIT DESCRIPITON
4-1 RECEIVER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4-2 TRANSMITER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4-3 PLL CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4-4 POWER SUPPLY CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4-5 OTHER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4-6 PORT ALLOCATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
SECTION 5 ADJUSTMENT PROCEDURES
5-1 PREPARATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5-2 SOFTWARE ADJUSTMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
SECTION 6 PARTS LIST
SECTION 7 MECHANICAL PARTS AND DISASSEMBLY
SECTION 8 SEMI-CONDUCTOR INFORMATION
SECTION 9 BOARD LAYOUTS
9-1 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9-2 FRONT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9-3 VR BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9-4 CONNECTOR BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
SECTION 10 BLOCK DIAGRAM
SECTION 11 VOLTAGE DIAGRAM
11-1 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11-2 RF UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11-3 VR / CONNECTOR BOARDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
Icom, Icom Inc. and are registered trademarks of Icom Incorporated (Japan) in the United States, the United Kingdom,
Germany, France, Spain, ussia and/or other countries.
1 - 1
SECTION 1 SPECIFICATIONS
‘‘
GENERAL
• Frequency coverage : 136.000–174.000 MHz
• Mode : FM
• Type of emission :
• Number of conventional channels : 128 ch, 8banks
• Antenna connector : SMA type (50 Ω)
• Operating temperature range : –30 ˚C to +60˚C (–22 ˚F to +140˚F) [USA], [GEN]
–25 ˚C to +55˚C [EUR]
• Power supply requirement : 7.2 V DC nominal (negative ground)
• Current drain (at 7.2 V DC) :
• Dimensions (projections not included) : 56.0(W)
×97.0(H)×36.4(D) mm
2
7
⁄32(W) ✕ 313⁄16(H) ✕ 17⁄16(D) in
• Weight (Including BP-223) : Approximately 280 g (9.88 oz)
‘‘
TRANSMITTER
• Output power (at 7.2 V DC) : High: 5 W, Low: 1 W
• Modulation : Variable reactance frequency modulation
• Maximum permissible deviation : ±5.0 kHz (Wide), ±4.0 kHz (Middle), ±2.5 kHz (Narrow)
• Frequency error : ±2.5 ppm
• Spurious emissions : 70 dB (typical) [USA], [GEN]
0.25 µW (≤ 1 GHz), 1.0 µW (≥ 1 GHz) [EUR]
• Adjacent channel power : 70 dB min. (Wide, Middle), 60 dB min. (Narrow)
• Audio harmonic distortion : 3 % typical (AF 1kHz, 40 % deviation)
• *
1
Hum and Noise ([USA], [GEN] only) : 40 dB min (46 dB typical) for Wide
(without CCITT filter) 34 dB min (40 dB typical) for Narrow
• *
1
Residual modulation ([EUR] only) : 45 dB min (55 dB typical) for Wide
(with CCITT filter) 43 dB min (53 dB typical) for Middle
40 dB min (50 dB typical) for Narrow
• Limiting charact of modulator : 60–100 % of maximum deviation
• Microphone impedance : 2.2 kΩ
‘‘
RECEIVER
• Receive system : Double conversion superheterodyne system
• Intermediate frequencies : 1st IF: 46.35 MHz, 2nd IF: 450 kHz
• Sensitivity : 0.25 µV (–119 dBm) typical at 12 dB SINAD [USA], [GEN]
0.63 µV (–111 dBm) emf typical at 20 dB SINAD [EUR]
• Adjacent channel selectivity : 70 dB min (75 dB typical) for Wide and Middle
60 dB min (65 dB typical) for Narrow
• Spurious response : 70 dB
• Intermodulation rejection ratio : 70 dB min (74 dB typical) [USA], [GEN]
65 dB min (67 dB typical) [EUR]
• *
1
Hum and Noise ([USA], [GEN] only) : 40 dB min (45 dB typical) for Wide
(without CCITT filter) 34 dB min (40 dB typical) for Narrow
• *
1
Hum and Noise ([EUR] only) : 45 dB min (55 dB typical) for Wide
(with CCITT filter) 43 dB min (53 dB typical) for Middle
40 dB min (50 dB typical) for Narrow
• Audio output power : 0.5 W typical at 5% distortion with an 8 Ω load
• Squelch sensitivity (at threshold) : 0.25 µV typical [USA], [GEN]
0.63 µV (–111 dBm) emf typical [EUR]
• Output impedance (Audio) : 8 Ω
Specifications are measured in accordance with EIA-152-C/204D, TIA-603 or EN 300 086.
All stated specifications are subject to change without notice or obligation.
VERSION
[USA], [GEN]
[EUR]
WIDE
16K0F3E (25.0 kHz)
MIDDLE
14K0F3E (20.0 kHz)
NARROW
11K0F3E (12.5 kHz)
8K0F3E (12.5 kHz)
RECEIVING TRANSMITTING
Stand-by
85 mA
Max. audio
300 mA
High (5 W)
1.8 A
Low (1 W)
0.7 A
SECTION 2 INSIDE VIEWS
•
MAIN UNIT
2 - 1
•
FRONT UNIT
APC amplifier
(IC2: TA75S01F)
+5 Regurator
(IC9: NJM2870)
IF amplifier
(Q4: 2SC4215)
IF IC
(IC1: TA31136FN)
Antenna
switching circuit
(D2,D5: 1SV307)
Analog switch
(IC13: BU4066BCFV)
Baseband IC
(IC10: AK2346)
Expander IC
(IC12: BU4094BCFV)
D/A converter
(IC6: M62363FP)
Power amplifier
(Q7: RD07MVS1)
T5 Regulator
(Q21: 2SA1577)
S5 Regulator
Q23: 2SB1132
Q24: XP6501
Q25: DTA144EU
R5 Regulator
(Q22: 2SA1577)
*Scrambler IC
(IC14: FX214LG)
*Depended on versions
VCO circuit
TOP VIEW BOTTOM VIEW
TX/RX
switch
(D14,D15: MA2S077)
EEPROM
(IC409: 24LC64T)
Reset IC
(IC408: BD5242G)
Expander IC
(IC410: BU4094BCFV)
CPU
(IC401:
HD6432264F01TF)
TOP VIEW BOTTOM VIEW
Microphone
mute switch
(IC406: TC7W66FK)
AF amplifier
(IC405: TA7368F)
SECTION 3 DISASSEMBLY INSTRUCTIONS
3 - 1
Chassis unit
B
C
D
F
G
E
H
A
E
F
Shield cover
L
L
K
I
I
K
J
J
Main unit
Chassis unit
N
N
Front unit
M
O
•
REMOVING THE CHASSIS UNIT
1 Unscrew 1 nut A, and remove 1 knob B.
2 Remove 1 washer c, and unscrew 1 screw D.
3 Unscrew 2 screws E, and remove 2 washers F.
4 Unscrew 2 screws G.
5 Ta ke off the chassis unit in the direction of the arrow.
6 Remove the cable H from the chassis unit.
•
REMOVING THE FRONT UNIT
1 Unscrew 4 screws M.
2 Unsolder 11 points N.
3 Unplug the connector O from J402 on the Front unit.
4 Ta ke off the front unit in the direction of the arrow.
•
REMOVING THE MAIN UNIT
1 Unscrew 2 screws I.
2 Unsolder 5 points J, and remove the shield cover.
3 Unscrew 5 screws K.
4 Unsolder 5 points L, and take off the main unit in the
direction of the arrow.
4 - 1
SECTION 4 CIRCUIT DESCRIPTION
4-1 RECEIVER CIRCUITS
4-1-1 ANTENNA SWITCHING CIRCUIT
(MAIN UNIT)
The antenna switching circuit functions as a low-pass filter
while receiving and a resonator circuit while transmitting.
This circuit does not allow transmit signals to enter the
receiver circuits.
Received signals enter the antenna connector (CHASSIS;
J1) and pass through the low-pass filter (L1, L2, C1–C5).
The filtered signals are passed through the
λ
⁄4 type antenna
switching circuit (D5, D6, L5, L6) and then applied to the RF
circuit.
4-1-2 RF CIRCUIT (MAIN UNIT)
The RF circuit amplifies signals within the range of frequency coverage and filters out-of-band signals.
The signals from the antenna switching circuit pass through
the two-stage tunable bandpass filters (D4, D8, L7, L8). The
filtered signals are amplified at the RF amplifier (Q2) and
then passed through the another two-stage tunable bandpass filters (D9, D10, L9, L11) to suppress unwanted signals. The filtered signals are applied to the 1st mixer circuit.
D4, D8–D10 employ varactor diodes, that are controlled by
the CPU via the D/A converter (IC6), to track the bandpass
filter. These varactor diodes tune the center frequency of an
RF pass band for wide bandwidth receiving and good image
response rejection.
4-1-3 1ST MIXER AND 1ST IF CIRCUITS
(MAIN UNIT)
The 1st mixer circuit converts the received signal into fixed
frequency of the 1st IF signal with the PLL output frequency.
By changing the PLL frequency, only the desired frequency
passes through a crystal filter at the next stage of the 1st
mixer.
The RF signals from the bandpass filter are mixed with the
1st LO signals, where come from the RX VCO circuit via the
attenuator (R26–R28), at the 1st mixer circuit (Q3) to produce a 46.35 MHz 1st IF signal. The 1st IF signal is passed
through a monolithic filter (FI1) in order to obtain selection
capability and to pass only the desired signals. The filtered
signal is applied to the 2nd IF circuit after being amplified at
the 1st IF amplifier (Q4).
4-1-4 2ND IF AND DEMODULATOR CIRCUITS
(MAIN UNIT)
The 2nd mixer circuit converts the 1st IF signal into a 2nd IF
signal. The double-conversion superheterodyne system
(which convert receive signals twice) improves the image
rejection ratio and obtains stable receiver gain.
The 1st IF signal from the IF amplifier (Q4) is applied to the
2nd mixer section of the FM IF IC (IC1, pin 16), and is mixed
with the 2nd LO signal to be converted into a 450 kHz 2nd
IF signal.
The FM IF IC (IC1) contains the 2nd mixer, 2nd local oscillator, limiter amplifier, quadrature detector, active filter and
noise amplifier circuits. A 2nd LO signal (45.9 MHz) is produced at the PLL circuit by tripling it’s reference frequency
(15.3 MHz).
The 2nd IF signal from the 2nd mixer (IC1, pin 3) passes
through the ceramic filter (FI2) to remove unwanted heterodyned frequencies. It is then amplified at the limiter amplifier section (IC1, pin 5) and applied to the quadrature detector section (IC1, pins 10, 11) to demodulate the 2nd IF signal into AF signals.
The demodulated AF signals are output from pin 9 (IC1) and
applied to the AF circuit via the receiver mute circuit.
Mixer
16
Limiter
amp.
2nd IF filter
450 kHz
X2
15.3 MHz
45.9 MHz
IC1 TA31136FN
12
1st IF from the IF amplifier (Q4)
"RSSI" signal to the CPU (FRONT unit; IC401, pin 50)
11109
87
5
AF signal "DET"
"SQIN" signal from the
D/A converter IC
(IC6, pin 2)
R5V
X2
2
Active
filter
Noise
detector
FM
detector
13
"NOIS" signal to the CPU (FRONT unit; IC401, pin 41)
RSSI
Noise
comp.
×3
PLL IC
IC4
Q19
12
FI2
3
• 2ND IF AND DEMODULATOR CIRCUITS
4 - 2
4-1-5 AF AMPLIFIER CIRCUIT
(MAIN AND FRONT UNITS)
The AF amplifier circuit amplifies the demodulated AF signals to drive a speaker. This transceiver employs the base
band IC which is composed of pre-amplifier, expander,
scrambler, MSK de-modulator, etc. at the AF amplifier section.
The AF signals from the FM IF IC (IC1, pin 9) are amplified
at the AF amplifier section of the base band IC (IC10, pin 5)
and are then applied to the low-pass filter section of it.
The filtered signals passes through the high-pass filter to
suppress unwanted harmonic components. The signals
pass through (or bypass) scrambler and expander sections,
and are then applied to (or bypass) the scrambler IC (IC14)
via the analog switch (IC13). The signals are amplified at the
amplifier section of the base band IC (IC10), and pass
through the AF mute switch (IC406) and low-pass filter
(IC403). The filtered signals pass through the AF volume,
and are then applied to the AF power amplifier (IC405) to
drive the speaker.
4-1-6 RECEIVE MUTE CIRCUITS
(MAIN AND FRONT UNITS)
• NOISE SQUELCH
A squelch circuit cuts out AF signals when no RF signals are
received. By detecting noise components in the AF signals,
the squelch circuit switches the AF mute switch.
Some noise components in the AF signals from the FM IF IC
(IC1, pin 9) are passed through the D/A converter (IC6, pin
1). The signals are applied to the active filter section in the
FM IF IC (IC1, pin 8). Noise components about 10 kHz are
amplified and output from pin 7.
The filtered signals are converted into the pulse-type signals
at the noise detector section and output from pin 13 (NOIS).
The “NOIS” signal from the FM IF IC is applied to the CPU
(FRONT unit; IC401, pin 41). Then the CPU analyzes the
noise condition and controls the AF mute signal via “AFON”
line from expander IC (FRONT unit; IC410, pin 7) to the AF
power controller (FRONT unit; Q401, Q402).
• CTCSS AND DTCS
The tone squelch circuit detects AF signals and opens the
squelch only when receiving a signal containing a matching
subaudible tone (CTCSS or DTCS). When tone squelch is in
use, and a signal with a mismatched or no subaudible tone
is received, the tone squelch circuit mutes the AF signals
even when noise squelch is open.
A portion of the “DET” AF signals from the FM IF IC (IC1, pin
9) passes through the low-pass filter (IC5, pin 5) to remove
AF (voice) signals, and are then applied to the amplifier
(MAIN unit; IC5, pin 10). The amplified signals are applied to
the CTCSS or DTCS decoder inside of the CPU (FRONT;
IC401, pin 44) via the “CDEC” line. The CPU outputs AF
mute control signal, and is then applied to the I/O expander
IC (IC410). The IC outputs AF mute circuit (IC406) and AF
power supply circuits (Q401, Q402) control signals via the
“AFON” line.
4-2 TRANSMITTER CIRCUITS
4-2-1 MICROPHONE AMPLIFIER CIRCUIT
(FRONT AND MAIN UNITS)
The microphone amplifier circuit amplifies audio signals
within +6 dB/octave pre-emphasis characteristics from the
microphone to a level needed for the modulation circuit.
This transceiver employs the base band IC which is composed of microphone amplifier, compressor, scrambler, limiter, splatter filter, MSK modulator, etc. at the microphone
amplifier section.
The AF signals (MIC) from the microphone (MC401) are
passed through the microphone mute switch (IC406, pins 2,
1), and are then applied to the amplifier (IC407, pins 2, 6).
The amplified signals pass through (or bypass) the scrambler IC (IC14) via the analog switch (IC13), and are then
applied to the microphone amplifier section of the base band
IC (MAIN unit; IC10, pins 3, 4). The amplified signals are
passed through or bypass the compressor, scrambler sections of IC10 (MAIN unit), and are then passed through the
high-pass, limiter amplifier, splatter filter sections of IC10
(MAIN unit).
The filtered AF signals are applied to the FM/PM switch
(MAIN unit; IC11, pin 6), and pass through the low-pass filter (MAIN unit; IC5, pin 1). The amplified signals are applied
to the D/A converter (MAIN unit; IC6, pin 4)
The output signals from the D/A converter (MAIN unit; IC6,
pin 3) are applied to the modulation circuit (MAIN unit; D18).
AF mute
(IC406)
Base band IC
(IC10)
"DET" AF signal
from FM IF IC (IC1, pin 9)
5
20
Scrambler IC
(IC14)
LPF
AF
volume
AF
IC405
Speaker
(SP1)
IC403
18 18
Analog switch
(IC13)
8
11
10
9
19
15
• AF AMPLIFIER CIRCUIT
4 - 3
4-2-2 MODULATION CIRCUIT (MAIN UNIT)
The modulation circuit modulates the VCO oscillating signal
(RF signal) using the microphone audio signals.
The AF signals from the D/A converter (IC6, pin 3) change
the reactance of varactor diode (D18) to modulate the oscillated signal at the TX VCO circuit (Q13, D16, D17). The
modulated VCO signal is amplified at the buffer amplifiers
(Q10, Q12) and is then applied to the drive amplifier circuit
via the T/R switch (D14).
The CTCSS/DTCS signals (“CENC0”, “CENC1”, ”CENC2”
from the CPU (FRONT unit; IC401, pins 79–81) pass
through the low-pass filter (IC403, pins 1, 3), and are then
applied to the D/A converter via the “CDCS” line (IC6, pin 9).
The output signal from the D/A converter (IC6, pin 10) passes through the low-pass filter (IC5, pins 1, 2). The
CTCSS/DTCS signals are mixed with “MOD” signal at the
low-pass filter (IC5), and are then applied to the D/A converter again (IC6, pin 4).
4-2-3 DRIVE/POWER AMPLIFIER CIRCUITS
The drive/power amplifier circuits amplify the VCO oscillating signal to an output power level.
The signal from the VCO circuit passes through the T/R
switch (D14), and is amplified at the pre-drive (Q9), drive
(Q8), power (Q7) amplifiers to obtain 5 W of RF power (at
7.2 V DC).
The amplified signal is passed through the power detector
(D1), antenna switching circuit (D2) and low-pass filter (L1,
L2, C1–C5), and is then applied to the antenna connector
(CHASSIS unit; J1).
The bias current of the pre-drive (Q9), drive (Q8) and power
(Q7) amplifiers are controlled by the APC circuit.
4-2-4 APC CIRCUIT (MAIN UNIT)
The APC circuit (IC2, D1) protects the drive and power
amplifiers from excessive current drive, and selects output
power of HIGH, LOW2 or LOW1.
The power detector circuit (D1) detects the transmit power
output level and converts it into DC voltage. The output voltage is at a minimum level when the antenna impedance is
matched at 50 Ω and is increased when it is mismatched.
The detected voltage is applied to the differential amplifier
(IC2, pin 3), and the “T2” signal from the D/A converter (IC6,
pin 14), controlled by the CPU (FRONT unit; IC401), is
applied to the other input for reference. When antenna
impedance is mismatched, the detected voltage exceeds
the power setting voltage. Then the output voltage of the differential amplifier (IC2, pin 4) controls the input current of
the pre-drive (Q9), drive (Q8) and power (Q7) amplifiers to
reduce the output power.
4-3 PLL CIRCUITS
4-3-1 PLL CIRCUIT (MAIN UNIT)
A PLL circuit provides stable oscillation of the transmit frequency and receive 1st LO frequency. The PLL output compares the phase of the divided VCO frequency to the reference frequency. The PLL output frequency is controlled by
the divided ratio (N-data) of a programmable divider.
The PLL circuit contains the TX/RX VCO circuits (Q13, Q14,
D16, D17, D19, D20). The oscillated signal is amplified at
the buffer amplifiers (Q11, Q12) and then applied to the PLL
IC (IC4, pin 8) after being passed through the low-pass filter
(L32, C206–C208).
The PLL IC contains a prescaler, programmable counter,
programmable divider and phase detector, etc. The entered
signal is divided at the prescaler and programmable counter
section by the N-data ratio from the CPU. The divided signal
is detected on phase at the phase detector using the reference frequency.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.
Q7
Power
amp.
IC2
APC
amp.
Q8
Driver
amp.
+
—
Q9
Pre
drive
VCC
to antenna
T2
TMUT
D25
RF signal
from PLL circuit
T5V
APC control circuit
Power detector
circuit (D1)
D1
L4 L3
• APC CIRCUIT
4 - 4
4-3-2 VCO CIRCUIT (MAIN UNIT)
The VCO circuit contains a separate RX VCO (Q14, D19,
D20) and TX VCO (Q13, D16, D17). The oscillated signal is
amplified at the buffer amplifiers (Q10, Q12) and is then
applied to the T/R switch (D14, D15). Then the receive 1st
LO (Rx) signal is applied to the 1st mixer (Q3) and the transmit (Tx) signal to the pre-drive amplifier circuit (Q9).
A portion of the signal from the buffer amplifier (Q12) is fed
back to the PLL IC (IC4, pin 8) via the buffer amplifier (Q11)
as the comparison signal.
LINE
VCC
+5V
S5V
R5V
T5V
DESCRIPTION
The voltage from the connected battery pack.
Common 5 V converted from the VCC line at the
+5 regulator circuit (IC9). The output voltage is
supplied to the fast switch (IC17), buffer amplifiers (IC16, IC18) and so on.
Common 5 V converted from the VCC line at the
S5 regulator circuit (Q23–Q25). The output voltage is supplied to the ripple filter (Q17), PLL IC
(IC4), FRONT unit, etc.
Receive 5 V converted from the S5V line at the
R5 regulator circuit (Q22). The output voltage is
supplied to the tripler (Q19), FM IF IC (IC1), IF
amplifier (Q4), VCO switch (Q15, Q16), 1st
mixer (Q3), etc.
Transmit 5 V converted from the S5V line at the
T5 regulator circuit (Q21). The output voltage is
supplied to the pre-drive (Q9), APC amplifier
(IC2).
LINE
VCC
CPU5
S5V
DESCRIPTION
Same voltage as VCC line on the MAIN unit is
applied to the FRONT unit via the J401, pins 1,
2 (FRONT unit). The voltage is supplied to the
[PWR] switch controller (Q401, Q402).
Same voltage as +5V line on the MAIN unit is
applied to the FRONT unit via the J401, pin 4
(FRONT unit). The voltage is supplied to the
CPU (IC401), reset IC (IC408), etc.
Same voltage as S5V line on the MAIN unit is
applied to the FRONT unit via the J401, pin 5
(FRONT unit). The voltage is supplied to the mic
mute circuit (IC406), etc.
Shift register
Prescaler
Phase
detector
Loop
filter
Programmable
counter
Programmable
divider
X2
15.3 MHz
1
Buffer
Q12
Buffer
Q8
Buffer
Q10
Buffer
Q11
9
10
11
SCK
SO
PLST
to transmitter circuit
to 1st mixer circuit
D14
D15
5
8
Q13, D16, D17
TX VCO
Q14, D19, D20
RX VCO
IC4 MB15A02
3
45.9 MHz 2nd LO
signal to the FM IF IC
(IC1, pin 2)
Tripler
Q19
2
"LVIN" signal to the CPU
(FRONT unit; IC401, pin 49)
LPF
• PLL CIRCUIT
4-4 POWER SUPPLY CIRCUIT
4-4-1 MAIN UNIT VOLTAGE LINE
4-4-2 FRONT UNIT VOLTAGE LINE
4 - 5
4-5 OTHER CIRCUITS
4-5-1 COMPOUNDER CIRCUIT (MAIN UNIT)
IC-F50/F51 have compounder circuit which can improve S/N
ratio and become wide dynamic range to suppress the
transmitting signal and to extend receiving signal. The circuit
is composed of the base band IC (MAIN unit; IC10).
(1) IN CASE OF TRANSMITTING
The audio signals from the microphone are applied to the
base band IC (IC10, pin 3) via microphone mute circuit
(FRONT unit; IC406), microphone amplifier (IC407), etc.
The signals are amplified at the amplifier section, and are
then applied to the compressor circuit to compress the audio
signals. The signals pass through (or bypass) scrambler
section, and are then amplified at limiter amplifier section
after being passed through the high-pass filter. The amplified signals pass through the low-pass filter section, and are
then applied to the modulation circuit (Q13, D16–D18) via
the FM/PM switch (IC11), low-pass filter (IC5) and D/A converter (IC6).
(2) IN CASE OF RECEIVING
The demodulated AF signals from the IF IC are applied to
the amplifier section of base band IC (IC10, pin 23), and
then pass through the low-pass and high-pass filter section
to suppress unwanted signals. The filtered signals pass
through (or bypass) scrambler section, and are then applied
to the expander circuit to expand AF signals. The signals
pass through (or bypass) scrambler IC (IC14), and are then
applied to the analog switch (IC13, pins 8, 11). The signals
are applied to the base band IC’s amplifier section (IC10,
pins 19, 20), and are then applied to the AF amplifier circuit.
4
5
6
7
11
12
13
14
LEDR
LEDT
LIGT
AFON
DUSE
MCON
CSFT
SPON
Outputs RX LED control signal.
Low: Lights ON.
Outputs TX LED control signal.
Low: Lights ON.
Outputs back light LED control signal.
Low: Back light is ON.
Outputs audio control signal.
Low: Outputs audio signals from
speaker.
• Outputs CTCSS/DTCS switching signal when transmitting.
High: Selected DTCS.
• Outputs Min. VR switching signal
when receiving.
Low: Select Min VR.
NOTE: Audio signals are prior to
transmitting.
Outputs microphone select signal.
High: While the internal microphone
is used.
Outputs shift signal for reference oscillator’s frequency.
Outputs the internal speaker control
signal.
High: The internal speaker is select-
ed.
Pin Port
Description
number name
Scrambler/
De-scrambler
TX/RX
HPF
Pre-
emphasis
Limiter Splatter VR2
Expander VR4
RXA2
SMF
De-
emphasis
Com-
pressor
VR1
(HPF)
RX
LPF
VR3
(HPF)
4
TXINO
7 MOD
18
19
20 SIGNAL
3TXIN
22RXINO
23RXIN
21SDEC
10
14MDIR
9
MTDT
MTCK
13MSCK
11MDIO
12MRDF
MSK
Modulator
MSK
Demodulator
MSK
BPF
Control
Register
TXA1
RXA1
• BASE BAND IC BLOCK DIAGRAM
4-6 PORT ALLOCATIONS
4-6-1 EXPANDER IC (FRONT UNIT; IC410)
4 - 6
4-6-2 MAIN CPU (FRONT unit; IC401)
Input port for the PTT switch detection
signal.
Low: While the PTT switch is
pushed.
Input ports for the key return A/D signals.
Input port for the detect signal for connecting battery pack’s voltage.
Input port for the PLL lock voltage
.
Input port for the S-meter signal from
the FM IF IC (MAIN unit; IC1, pin 12).
Input port for the transceiver’s internal
temperature detecting signal.
Input port for the optional microphone
determine signal.
Input port for the PLL unlock signal.
Low: The PLL circuit is unlocked.
Outputs serial data control signal to
the base band IC (MAIN unit; IC10, pin
14)
Output single tone encoder signal.
Outputs the cloning data signal.
Input port for the cloning data signal.
Input port for the receiving MSK detection signal from the base band IC
(MAIN unit; IC10, pin 12)
Output the CTCSS/DTCS signals.
• Outputs strobe signals to the D/A
convertor (IC6, pin 6).
• Input port for the connecting battery
type detect signal.
Output common signal to the LCD display.
PTT
KR1
KR0
BATV
LVIN
RSSI
TEMP
OPTV
ULCK
MDIR
SENC3–
SENC0
CLO
CLI
MRDF
CENC2–
CENC0
DAST
COM4–
COM1
45
46
47
48
49
50
51
52
55
71
72–75
76
77
78
79–81
82
88–91
1–11,
13,
15–25,
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
43
44
SEG23–
SEG13,
SEG12,
SEG11–
SEG1
SO
SCK
MDIO
MSCK
SCST
PLST
ESDA
ESCL
SCAT
EXSF
EXSM
EXOE
BEEP
MTDT
MTCK
NOIS
SDEC
CDEC
Output segment data to the LCD display.
Outputs serial data to the PLL IC
(MAIN unit; IC6, pin 8) and D/A convertor (MAIN unit; IC6, pin 8).
Outputs serial clock signal to the PLL
IC (MAIN unit; IC4, pin 9), D/A convertor (MAIN unit; IC6, pin 7), etc.
I/O port for the serial data signals
from/to the base band IC (MAIN unit;
IC10, pin 11).
Outputs clock signal to the base band
IC (MAIN unit; IC10, pin 13).
Outputs strobe signals to the scrambler IC (MAIN unit; IC14, pin 11).
Outputs strobe signals to the PLL IC
(MAIN unit; IC4, pin 11).
I/O port for data signals from/to the
EEPROM (IC409, pin 5).
Outputs clock signal to the EEPROM
(IC409, pin 6).
• Outputs power down control signal to
the scrambler IC (MAIN unit; IC14,
pin 12).
• Input port for the detection signal
whether the scrambler unit is
installed or not.
Outputs strobe signals to the expander
IC (IC410, pin 2).
Outputs strobe signals to the expander
IC (MAIN unit; IC12, pin 1).
Outputs the enable signal to the
expander ICs (IC410, pin 15 and MAIN
unit; IC12, pin 15).
Outputs beep audio signals.
Outputs MSK data for transmitting to
the base band IC (MAIN unit; IC10, pin
10).
Input port for the transmitting MSK
clock signal from the base band IC
(MAIN unit; IC10, pin 9).
Input port for the noise signal from the
FM IF IC (MAIN unit; IC1, pin 13).
Input port for single tone decode signal
from the base band IC (MAIN unit;
IC10, pin 21).
Input port for CTCSS/DTCS signal
from the amplifier (MAIN unit; IC5, pin
8).
Pin Port
Description
number name
Pin Port
Description
number name
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