SERVICE
MANUAL
VHF/UHF ALL MODE TRANSCEIVER
i910H
INTRODUCTION |
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DANGER |
This service manual describes the latest service information for the IC-910H VHF/UHF ALL MODE TRANSCEIVER at the time of publication.
VERSION No. |
VERSION |
SYMBOL |
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#02 |
Europe |
EUR |
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#04 |
Australia |
AUS |
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#06 |
U.S.A. |
USA-1 |
#07 |
Korea |
KOR |
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To upgrade quality, any electrical or mechanical parts and internal circuits are subject to change without notice or obligation.
NEVER connect the transceiver to an AC outlet or to a DC power supply that uses more than 16 V. This will ruin the transceiver.
DO NOT expose the transceiver to rain, snow or any liquids.
DO NOT reverse the polarities of the power supply when connecting the transceiver.
DO NOT apply an RF signal of more than 20 dBm (100 mW) to the antenna connector. This could damage the transceiver’s front end.
ORDERING PARTS
Be sure to include the following four points when ordering replacement parts:
1.10-digit order numbers
2.Component part number and name
3.Equipment model name and unit name
4.Quantity required
<SAMPLE ORDER>
1110003140 |
IC |
LA1150N |
IC-910H |
MAIN UNIT |
5 pieces |
8810005770 |
Screw |
BiH M3×8 ZK |
IC-910H |
Cover |
10 pieces |
Addresses are provided on the inside back cover for your convenience.
REPAIR NOTES
1.Make sure a problem is internal before disassembling the transceiver.
2.DO NOT open the transceiver until the transceiver is disconnected from its power source.
3.DO NOT force any of the variable components. Turn them slowly and smoothly.
4.DO NOT short any circuits or electronic parts. An insulated tuning tool MUST be used for all adjustments.
5.DO NOT keep power ON for a long time when the transceiver is defective.
6.DO NOT transmit power into a signal generator or a sweep generator.
7.ALWAYS connect a 50 dB to 60 dB attenuator between the transceiver and a deviation meter or spectrum analyzer when using such test equipment.
8.READ the instructions of test equipment thoroughly before connecting equipment to the transceiver.
SECTION 1 |
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SPECIFICATIONS |
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SECTION 2 |
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INSIDE VIEWS |
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2 |
- 1 |
IC-910H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 2 - 1 |
2 |
- 2 |
UX-910 (OPTIONAL UNIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 2 - 3 |
SECTION 3 |
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DISASSEMBLY AND OPTION INSTRUCTIONS |
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SECTION 4 |
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CIRCUIT DESCRIPTION |
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SECTION 5 |
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ADJUSTMENT PROCEDURES |
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SECTION 6 |
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PARTS LIST |
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SECTION 7 |
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MECHANICAL PARTS |
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SECTION 8 |
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SEMI-CONDUCTOR INFORMATION |
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SECTION 9 |
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BOARD LAYOUTS |
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9 |
- 1 |
VR-A BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
9 - 1 |
9 |
- 2 |
VR-B BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
9 - 1 |
9 |
- 3 |
RIT BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
9 - 1 |
9 |
- 4 |
FUNC BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
9 - 3 |
9 |
- 5 |
MIC BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
9 - 3 |
9 |
- 6 |
JACK BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
9 - 3 |
9 |
- 7 |
DRV BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
9 - 3 |
9 |
- 8 |
VARISTOR-A BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
9 - 3 |
9 |
- 9 |
VARISTOR-B BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
9 - 3 |
9 |
- 10 |
VARISTOR-C BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
9 - 3 |
9 |
- 11 |
DISPLAY BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
9 - 5 |
9 |
- 12 |
PA UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
9 - 7 |
9 |
- 13 |
PLL UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
9 - 9 |
9 |
- 14 |
MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
9 - 11 |
9 |
- 15 |
UX-910 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
9 - 13 |
SECTION 10 BLOCK DIAGRAMS
10 - 1 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 1 10 - 2 PA AND PLL UNITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 2 10 - 3 FRONT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 3 10 - 4 UX-910 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 3
SECTION 11 WIRING DIAGRAM
SECTION 12 VOLTAGE DIAGRAMS
12 - 1 FRONT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 1 12 - 2 PLL UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 2 12 - 3 PA UNIT (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 3 12 - 4 PA UNIT (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 4 12 - 5 MAIN UNIT (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 5 12 - 6 MAIN UNIT (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 6 12 - 7 MAIN UNIT (3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 6 12 - 8 UX-910 MAIN UNIT (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 7 12 - 9 UX-910 MAIN UNIT (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 8
SECTION 1 SPECIFICATIONS
■ GENERAL
• Frequency coverage |
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(Unit: MHz) |
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Version |
144 MHz |
430 (440) MHz |
1200 MHz*1 |
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U.S.A. |
Tx: 144.0–148.0 |
Tx: 430.0–450.0 |
Tx: 1240.0–1300.0 |
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Rx: 136.0–174.0*2 |
Rx: 420.0–480.0*3 |
Rx: 1240.0–1320.0*4 |
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Europe |
144.0–146.0 |
430.0–440.0 |
1240.0–1300.0 |
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Australia |
144.0–148.0 |
430.0–450.0 |
1240.0–1300.0 |
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Korea |
144.0–146.0 |
430.0–440.0 |
1260.0–1300.0 |
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•Mode
•No. of memory Ch.
•Antenna connector
•Usable temp. range
•Frequency stability
•Frequency resolution
•Power supply
•Current drain (at 13.8 V DC)
•Dimensions
(projections not included)
•Weight (approx.)
•ACC 1 connector
•CI-V connector
•DATA connectors
■ TRANSMITTER
•Output power
•Modulation system
•Spurious emission
•Carrier suppression
•Unwanted sideband suppression
•Microphone connector
•KEY connector
*1 Optional UX-910 is installed.
*2 Guaranteed range is 144.0–148.0 MHz. *3 Guaranteed range is 430.0–450.0 MHz. *4 Guaranteed range is 1240.0–1300.0 MHz.
:USB, LSB, CW, FM, FM-N*
*Not available in 1200 MHz band
:212 (99 regular, 6 scan edges, 1 calls for each band) plus 10 satellite memories)
:SO-239 (50 Ω; VHF) Type-N (50 Ω; UHF)
:–10˚C to +60˚C; +14˚F to +140˚F
:Less than ±3 ppm (–10 to 60˚C; +14 to +140˚F)
:1 Hz minimum
:13.8 V DC ±15% (negative ground)
:
Transmit |
Max. power |
23.0 A |
Receive |
Standby |
2.0 A (3.0 A with UX-910) |
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Max. audio |
2.5 A (3.5 A with UX-910) |
:241(W) × 94(H) × 239(D) mm 91⁄2(W) × 311⁄16(H) × 913⁄32(D) in
:4.5 kg; 10 lb (with UX-910: 5.35 kg; 11 lb 13 oz)
:8-pin DIN connector
:2-conductor 3.5 (d) mm (1⁄8″)
:6-pin mini DIN × 2 (for MAIN and SUB)
: (continuously adjustable)
144 MHz |
5–100 W |
430 (440) MHz |
5–75 W |
1200 MHz |
1–10 W (with UX-910) |
: SSB |
Balanced modulation |
FM |
Variable reactance modulation |
: 144/430 (440) MHz More than 60 dB |
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1200 MHz |
More than 50 dB |
:More than 40 dB
:More than 40 dB
:8-pin connector (600 Ω)
:3-conductor 3.5(d) mm (1⁄4″)
All stated specifications are subject to change without notice or obligation.
1 - 1
■ RECEIVER
• Receive system |
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VHF |
SSB, CW |
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Single conversion superheterodyne |
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FM |
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Double conversion superheterodyne |
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UHF |
SSB, CW |
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Double conversion superheterodyne |
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FM |
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Triple conversion superheterodyne |
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• Intermediate frequencies |
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(Unit: MHz) |
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MAIN BAND |
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SUB BAND |
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1st |
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2nd |
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3rd |
1st |
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2nd |
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3rd |
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SSB |
10.8500 |
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— |
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— |
10.9500 |
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— |
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— |
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144 MHz |
CW |
10.8491 |
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10.9491 |
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— |
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FM |
10.8500 |
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0.455 |
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— |
10.9500 |
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0.455 |
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— |
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SSB |
71.2500 |
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10.8500 |
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— |
71.3500 |
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10.9500 |
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— |
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430 (440) MHz |
CW |
71.2491 |
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10.8491 |
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— |
71.3491 |
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10.9491 |
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— |
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FM |
71.2500 |
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10.8500 |
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0.455 |
71.3500 |
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10.9500 |
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0.455 |
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SSB |
243.9500 |
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10.8500 |
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— |
243.9500 |
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10.9500 |
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— |
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1200 MHz |
CW |
243.9491 |
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10.8491 |
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— |
243.9491 |
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10.9491 |
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— |
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FM |
243.9500 |
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10.8500 |
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0.455 |
243.9500 |
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10.9500 |
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0.455 |
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• Sensitivity |
: SSB, CW (10 dB S/N) |
Less than 0.11 µV |
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FM (12 dB SINAD) |
Less than 0.18 µV |
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• Squelch sensitivity |
: SSB, CW |
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Less than 1.0 µV |
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(threshold) |
FM |
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Less than 0.18 µV |
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• Selectivity |
: SSB, CW |
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More than 2.3 kHz/–6 dB |
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Less than 4.2 kHz/–60 dB* |
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FM |
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More than 15.0 kHz/–6 dB |
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Less than 30.0 kHz/–60 dB* |
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FM-N |
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More than 6.0 kHz/–6 dB |
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Less than 18.0 kHz/–36 dB |
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CW-N |
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More than 0.5 kHz/–6 dB |
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(w/FL-132 or FL-133) |
Less than 1.34 kHz/–60 dB* |
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*Except 1200 MHz band |
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• Spurious and image rejection ratio: |
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144/430 (440) MHz |
More than 60 dB |
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1200 MHz |
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More than 50 dB |
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• AF output power (at 13.8 V DC): |
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More than 2.0 W at 10% distortion with an 8 Ω load |
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• RIT variable range |
: 144/430 (440) MHz |
±1.0 kHz (SSB, CW) |
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±5.0 kHz (FM) |
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1200 MHz |
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±2.0 kHz (SSB, CW) |
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±10.0 kHz (FM) |
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• IF SHIFT variable range |
: More than ±1.2 kHz |
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• PHONES connector |
: 3-conductor 6.35(d) mm (1⁄4″) |
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• Ext. SP connectors |
: 2-conductor 3.5 (d) mm (1⁄8″) /8 Ω × 2 (for MAIN and SUB) |
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1 - 2
1 - 2
* Located under side of the point
MAIN unit
Crystal band pass filter (FI151: FL-128)
TX IF amplifier* (Q1: 3SK131)
Crystal band pass filter (FI751: FL-129)
FM IF IC
(IC951: TA31136FN)
D/A converter (IC1521: M62352GP)
AF power amplifier (IC1852: LA4445)
Analog master IC* (IC1701: PC5023-077)
FM IF IC
(IC401: TA31136FN)
PLL unit
DDS gate array (IC331: SC-1246A)
430 MHz band VCO circuit |
DDS IC
(IC601: SC-1287)
Driver IC
(IC1: BU4094BCF)
Reference oscillator (X512: CR-452 30.2 MHz)
DDS gate array (IC131: SC-1246A)
144 MHz band VCO circuit |
DDS IC
(IC701: SC-1287)
UNITS PLL AND MAIN • |
910H-IC 1-2 |
2 SECTION |
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VIEWS INSIDE |
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2 - 2
TX/RX switching relay (RL700: AE5349)
Pre-amplifier (Q507: 3SK177)
RX balanced mixer (Q511, Q512: 2SK1740)
145 MHz power amplifier (Q651, Q652: 2SC5152)
TX balanced mixer Q501, Q502: 2SK302 D502: 1SV286
Varistor-A board
DRV board
UNIT PA •
Pre-amplifier (Q260: 3SK177)
RX balanced mixer (Q220, Q221: 2SC3356)
Varistor-C board
Varistor-B board
440 MHz power amplifier (Q151, Q152: 2SC3102)
TX balanced mixer* (Q1, Q2: 2SK302)
TX double balanced mixer |
D190: HSB88WS |
L190, L191: 617DB-1010 |
Drive amplifier (Q131: SRFJ7044)
* Located under side of the point
2-2 UX-910 (OPTIONAL UNIT)
• TOP VIEW
Power module IC (IC21: M57762-02)
YGR amplifier (IC141: PC1878G)
PLL IC
(IC501: TB31242)
1st LO VCO circuit
DDS IC
(IC661: SC-1246A)
• BOTTOM VIEW
Power supply circuit for AG-1200 (Q71: 2SD1801)
Pre-drive amplifier (Q36: 2SK2354)
2nd IF amplifier (Q81: 2SC2712)
Power supply circuit for AG-1200
Q72: DTC144EU Q73, Q74: 2SC2712
RF pre-amplifier (Q281: NE34018)
RF amplifier (Q271: 2SC5454)
TX 1st mixer (IC131: PC8163TB)
RX 1st mixer (IC241: PC2721)
TX 1st IF amplifier (IC111: PC2709)
RX 2nd mixer (Q221: 3SK166)
TX 2nd mixer (D82: HSB88WS)
2nd LO VCO circuit
Drive amplifier (Q38: 2SK2855)
Divider
(IC610: TC7W74FU)
Reference amplifier (IC601: TC7SU04F)
2 - 3
SECTION 3 DISASSEMBLY AND OPTION INSTRUCTIONS
• Opening the transceiver’s case
Follow the case and cover opening procedures shown here when you want to install an optional unit or adjust the internal units, etc.
qRemove the 5 screws from the top of the transceiver and 4 screws from the sides, then lift up the top cover.
w Turn the transceiver upside down.
eRemove 5 screws from the bottom of the transceiver, then lift up the bottom cover.
CAUTION: DISCONNECT the DC power cable from the transceiver before performing any work on the transceiver. Otherwise, there is a danger of electric shock and/or equipment damage.
Disconnect the speaker cable.
• UX-910 1200MHz BAND UNIT
q Remove the bottom cover as shown above.
wRemove the antenna plate from the chassis using a standard screw driver.
WARNING!
NEVER attempt to remove the antenna plate using your finger, this may result in injury.
e Connect the FFC (Flexible Flat Cable) of the UX-910 to J2 on the MAIN unit, DC power cable to the power connector (W305) from the PA unit and the coaxial cable to J541 on the PLL unit.
CAUTION
NEVER catch the cables from the optional DSP unit(s) between chassis and the UX-910, this may damage the DSP unit(s) and/or transceiver.
Coaxial cable
PLL unit
J541
UX-910
DC power cable
J2
Flexible flat cable
Power connector
r Place the UX-910 using the supplied 4 screws.
BE CAREFUL not to drop the supplied screws inside the transceiver.
Antenna plate
UX-910
UX-910
J2
MAIN unit
Turn the flexible flat cable up under the UX-910.
t Return the bottom cover to its original position.
3 - 1
• Opening the PA unit cover
qRemove the top cover as shown in the diagram on p. 3- 1.
wRemove 8 screws and grounding plate from the PA unit cover.
e Remove fastening tape from the inside power cable.
grounding plate
r Slide the PA unit cover as shown below.
• FL-132/FL-133 CW NARROW FILTER
qRemove the bottom cover as shown in the diagram on p. 3-1.
• Remove the UX-910 if you have installed it. (p. 3-1)
wDisconnect the connection cable connectors from J501 and J1051 on the MAIN unit.
e Remove 2 clips.
WARNING!
BE CAREFUL not to pinch your finger with the clip.
rRemove 6 screws from the MAIN unit, then lift up the MAIN unit.
PLL unit
J501
J1051
MAIN unit
Clips
tInstall FL-132 or FL-133 to the specified position on the MAIN unit.
FL-132 (MAIN)
FL-133 (SUB)
ySolder then cut the leads, keeping 2–3 mm (1/8’’) of the leads from the bottom of the MAIN unit.
u Return the MAIN unit and clips to their original positions.
iRe-connect the connection cable connector to J501 and J1051 on the MAIN unit.
o Return the bottom cover to the original position.
(MAIN)
(SUB)
3 - 2
• UT-102 VOICE SYNTHESIZER UNIT
qRemove the bottom cover as shown in the diagram on p. 3-1.
• Remove the UX-910 if you have installed it. (p. 3-1)
wRemove the protective paper attached to the bottom of the UT-102 to expose the adhesive strip.
ePlug UT-102 into J1801 on the MAIN unit as shown in the diagram at right.
r Return the bottom cover to its original position.
UT-102
J1801
MAIN unit
• UT-106 DSP UNIT
RECOMMENDATION:
When installing only 1 DSP unit, you can install into either front or rear panel side. However, installing a DSP unit into the front panel side may be easier and also safer.
Installing 1st DSP unit (front panel side)
qRemove the bottom cover as shown in the diagram on p. 3-1.
• Remove the UX-910 if you have installed it. (p. 3-1)
w Remove the shielding plate.
eRemove the connection cable from J1751 on the MAIN unit. Connect the cable into J1 on the UT-106.
rPlug the connection cable (P1) from the UT-106 to J1751 on the MAIN unit.
tPlug the flat cable into J3 on the UT-106 and to J1771 on the MAIN unit.
•Take care of the conductor direction.
•Attach the Velcro tape to the UT-106 and PLL unit shielding plate.
yReturn the shielding plate, top cover and bottom cover to their original positions.
Shielding plate |
PLL unit |
UT-106 J3 |
J1 |
P1 |
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J1751 |
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J1771 |
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MAIN unit |
conductor direction. |
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Installing 2nd DSP unit (rear panel side)
qRemove the top and bottom cover as shown in the diagram on p. 3-1.
• Remove the UX-910 if you have installed it. (p. 3-1)
w Remove the shielding plate.
eRemove the connection cable from J1761 on the MAIN unit. Connect the cable into J1 on the UT-106.
The cable between J1221 on the MAIN and J1 on the DSP unit, must be set in the groove of the chassis (see diagram below).
Otherwise, the cable may be damaged when returning the shield plate to its original position.
rPlug the connection cable (P1) from the UT-106 to J1761 on the MAIN unit.
tPlug the flat cable into J3 on the UT-106 and to J1781 on the MAIN unit.
•Take care of the conductor direction.
•Attach the Velcro tape to the UT-106 and PLL unit shielding plate.
yReturn the shielding plate, top cover and bottom cover to their original positions.
Set cable into the groove.
J1
Shielding plate
PLL unit
J3
UT-106
P1
J1761
Take care of the conductor direction.
MAIN unit
3 - 3
• CR-293 HIGH STABILITY CRYSTAL UNIT
qRemove the bottom cover as shown in the diagram on p. 3-1.
• Remove the UX-910 if you have installed it. (p. 3-1)
wRemove 6 screws from the PLL shield cover, then lift up the PLL shield cover.
PLL shield cover
eDisconnect the FFC (Flexible Flat Cable) from the DISPLAY unit and the connection cable connectors from J501 and J1051 on the MAIN unit.
rRemove 5 screws from the PLL unit, then lift up the PLL unit.
tUnsolder the original reference crystal, then remove it.
•The original reference crystal unit is soldered at both top and bottom sides of the PCB (Printed Circuit Board).
Unsolder the |
CR-293 |
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original |
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crystal. |
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Original crystal
J501
J1051
Flexible flat cable
y Install the CR-293 and solder the leads.
uReturn the PLL unit, PLL shield cover and bottom cover to their original positions.
Original crystal soldering point
CR-293 soldering points
3 - 4
SECTION 4 CIRCUIT DESCRIPTION
Note: [Main]=Main band, [Sub]=Sub band
4-1-1 VHF TRANSMIT/RECEIVE SWITCHING CIRCUIT (PA UNIT)
Received signals from the antenna connector (CHASSIS; J1) are passed through the low-pass filter (L723–L721, C728–C726, C728) then applied to the transmit/receive switching circuit (RL700, D710).
The transmit/receive switching circuit leads receive signal to the RF circuit from a low-pass filter while receiving. However, the circuit leads the transmit signal from the RF power amplifier to the antenna connector while transmitting.
The passed signals are then applied to the RF amplifier circuit.
4-1-2 VHF RF CIRCUIT (PA UNIT)
Received signals from transmit/receive switching circuit are applied to the RF amplifier circuit (Q507) via the RF attenuator (D515), limiter (D514) and tunable band pass filter (D513, L560) circuits.
The amplified signals are then passed through the another three-stage tunable bandpass filters (D512–D510, L13–L15) to suppress unwanted signals. The filtered signals are then applied to the 1st mixer circuit (Q511, Q512).
D510–D513 employ varactor diodes, which are controlled by the CPU (DISPLAY board; IC1) via the D/A converter (MAIN unit; IC1521) and buffer amplifier (MAIN unit; IC1522d), to track the bandpass filter. These varactor diodes tune the center frequency of an RF pass band for wide bandwidth receiving and good image response rejection.
4-1-3 VHF 1ST MIXER CIRCUIT (PA UNIT)
The 1st mixer circuit converts the received signals into a fixed frequency of the 10 MHz IF signal with a PLL output frequency. By changing the PLL frequency, only the desired frequency will pass through a pair of crystal filters at the next stage of the VHF 1st mixer.
The filtered signals from the bandpass filter are mixed with 1st LO signals at the mixer circuit (Q511, Q512) to produce a 1st IF signal (10.85 MHz [Main] or 10.95 MHz [Sub]). The 1st LO signals (125.15 MHz–163.15 MHz) are PLL output frequency, which comes from the VHF VCO circuit (PLL unit; Q191, D191–D194).
The 1st IF signal is then applied to either the Main or Sub band 10 MHz IF circuit in the MAIN unit via P501 [Main] or P510 [Sub].
4-1-4 UHF RF CIRCUIT (PA UNIT)
The received signals from the UHF antenna connector (CHASSIS; J2) are passed through the low-pass filter (L181, L180, C188–C184) and then transmit/receive switching circuit (D182–D185, D265, D266, D227). The signals from the transmit/receive switching circuit are applied to the RF amplifier circuit (Q260) via the RF attenuator circuit (D264) and tunable bandpass filter (D263, L288). The amplified signals are passed through the three-stage tunable bandpass filters (D262–D260, L262–L260), and are then applied to the 1st mixer circuit (Q220, Q221).
4-1-5 UHF 1ST AND 2ND MIXER CIRCUIT (PA UNIT)
The filtered RF signals from the bandpass filter are mixed with a 1st LO signal at the 1st mixer circuit (Q220, Q221) to produce a 1st IF signal (71.25 MHz [Main] or 71.35 MHz [Sub]). The 1st IF signal is passed through a crystal filter (Fl280 [Main], Fl281 [Sub]) to suppress out-of-band signals. The filtered IF signal is applied to the 2nd mixer circuit (Q11) to produce a 10 MHz IF signal (10.85 MHz [Main] or 10.95 MHz [Sub]) with a 2nd LO signal. The IF signal is then applied to the MAIN unit via P1 [Main] or P30 [Sub].
The 1st LO signal (348.75 MHz–408.75 MHz) is generated at the UHF VCO circuit (PLL unit; Q391, D391–D394), and a 2nd LO signal (60.2 MHz) is produced at the PLL circuit by doubling it’s reference frequency (30.2 MHz).
• RECEIVER CONSTRUCTION |
PA unit |
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430 MHz |
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1st mixer |
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2nd mixer |
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Q220, Q221 |
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Q11 |
LPF |
BPF |
BPF |
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1st LO |
BPF |
2nd LO |
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B1LO |
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B2LO |
144 MHz |
1st mixer |
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Q511, Q512 |
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LPF |
BPF |
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1st LO A1LO
MAIN unit |
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FI51 |
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FI151 |
IC351 |
for MAIN band |
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BPF |
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10.85 MHz |
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AF selector circuit |
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BFOM |
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for SUB band |
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FI651 |
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FI751 |
IC851 |
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BPF |
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AF signals to |
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10.95 MHz |
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AF selector circuit |
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BFOM |
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4 - 1
4-1-6 10 MHz IF CIRCUIT (MAIN UNIT)
The 10 MHz IF signal from the mixer circuit is passed through a monolithic filter (Fl51 [Main], Fl651 [Sub]) to suppress out-of-band signals. The filtered signal is amplified at the IF amplifier (Q51 [Main], Q651 [Sub]). The IF amplifier provides 20 dB gain.
The amplified signal is then applied to the different circuits depending on the selected mode.
(1) FM mode
The signal is applied to an FM IF IC pin 16 (IC401 [Main] or IC951 [Sub]).
(2) SSB and CW mode
The signal is passed through a 10 MHz IF filter (FI151/10.85 MHz [Main] or Fl751/10.95 MHz [Sub]) or optional CW narrow filters. The filtered signal is amplified at the IF amplifiers (Q350–Q352 [Main] or Q850–Q852 [Sub]) and then applied to a demodulator circuit.
4-1-7 DEMODULATOR CIRCUIT (MAIN UNIT)
(1) FM mode
The 10 MHz IF signal from an IF amplifier (Q51 [Main] or Q651 [Sub]) is applied to the mixer section of the FM IF IC (IC401 [Main], IC951 [Sub], pin 16), and is mixed with a LO signal (10.395 MHz [Main], 10.495 MHz [Sub]) to produce a 455 kHz IF signal. The LO signal is generated by the BFO circuit (PLL unit; IC601 [Main], IC701 [Sub]).
The FM detector circuit employs the quadrature detection method, which uses a ceramic discriminator (X401 [Main], X951 [Sub]) for phase delay to obtain a non-adjusting circuit.
The detected signals are output from pin 9, and applied to the squelch control and center indication detector circuits, etc.
(2) SSB and CW modes
The amplified signal from the IF amplifier circuit (Q51 [Main], Q651 [Sub]) is applied to the balanced mixer circuit (IC351 [Main], IC851 [Sub]) to demodulate into AF signals. Demodulated audio signals are output from pin 1, and applied to the squelch control gate (IC452 [Main], IC1002 [Sub]).
BFO circuit (PLL unit; IC601 [Main] and IC701 [Sub]) generates BFO signals for using in the balanced mixers.
• BFO frequencies
Mode |
for MAIN band |
for SUB band |
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USB |
10.8485 MHz |
10.9485 MHz |
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LSB |
10.8515 MHz |
10.9515 MHz |
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CW |
10.8483 MHz |
10.9483 MHz |
4-1-8 SQUELCH CONTROL CIRCUIT (MAIN UNIT)
The demodulated AF signals from the balanced mixer circuit or FM IF IC are applied to the squelch control gate (IC452 [Main], IC1002 [Sub]). This consists of 4 analog switches which are selected with a mode signal and squelch control signal from the CPU (DISPLAY board; IC1) via the expander IC (IC1491). The switched AF signals are applied to the AF circuit.
4-1-9 SQUELCH CIRCUIT (MAIN UNIT)
(1) FM mode
A squelch circuit cuts out AF signals when no RF signal is received or the S-meter signal is lower than the [SQL] control setting level. By detecting noise components in the AF signals, the CPU switches the squelch control gate.
A portion of the AF signals from the FM IF IC pin 9 (IC401 [Main], IC951 [Sub]) passes through the active filter section of FM IFIC (pin 8). The active filter section amplifies and filters noise components. The filtered signals are applied to the noise detector section for conversion into DC voltage and output from pin 14 (IC401 [Main], IC951 [Sub]) as the “NSQM [Main]/NSQS [Sub]” signal. The “NSQM [Main]/ NSQS [Sub]” signal is applied to the DISPLAY board.
The DC voltages are passed through the analog multiplexer (DISPLAY board; IC5, pins 15 and 2) and then applied to the CPU (DISPLAY board; IC1, pins 93, 94) via the MP1Y and MP1X signal lines. The [SQL] level signal is also applied to the CPU via the analog multiplexer (DISPLAY board; IC3, pins 14, 5) as a reference voltage for comparison with the noise signals. Also, an S-meter signal is applied to the CPU from FM IF IC pin 12 (IC401 [Main], IC951 [Sub]) via the meter amplifier (IC1804c [Main], IC1804a [Sub]) and analog multiplexer (DISPLAY board; IC4, pins 12 and 1). The CPU compares these signals, then outputs a control signals to the squelch control gate.
(2) SSB and CW modes
The squelch circuit mutes audio output when the S-meter signal is lower than the [SQL] control setting level.
A portion of the 10 MHz IF signal from the IF amplifier (Q352 [Main], Q852 [Sub]) is converted into DC voltage at the AGC detector (D303, Q305 [Main], D902 Q901 [Sub]) and amplified at the meter amplifier (IC1804d [Main] or IC1804b [Sub]). The amplified signal is passed through the analog multiplexer (DISPLAY board; IC4, pins 12 and 1) via the SMLM [Main]/ SMLS [Sub] signals and then applied to the CPU (DISPLAY board; IC1). The CPU outputs control signals to the squelch control gate when the S-meter signal is low level.
4-1-10 AF AMPLIFIER CIRCUIT (MAIN UNIT)
The AF amplifier circuit amplifiers the demodulated signals to drive a speaker. For the separate speaker function, a stereo power amplifier is used.
AF signals from the squelch control gate are passed through the AF filter (IC451a [Main], IC1001a [Sub]) and AF preamplifier (IC451b [Main], IC1001b [Sub]) and then amplified at the voltage controlled amplifier (VCA: IC1808 [Main], IC1809 [Sub]) which functions as a volume control using the [AF] control signal. The amplified AF signals are applied to the AF power amplifier circuit (IC1852, pin 2 [Main], pin 5 [Sub]).
The amplified audio signals of SUB band are output from pin 7, and are applied to the external speaker jack for the SUB band (J1852) via the [PHONE] jack (JACK board; J1). When no plug is connected to the jack, the signals are fed back to the MAIN band audio. The mixed audio is applied to the internal speaker via the [PHONE] jack and external speaker jack for the MAIN band (J1851).
4 - 2
4-1-11 NOISE BLANKER CIRCUIT (MAIN UNIT)
The noise blanker circuit detects pulse-type noises, and stops IF amplifier operation during detection.
A portion of the 10 MHz IF signal from the bandpass filter (FI51 [Main], FI651 [Sub]) is amplified at the noise amplifier circuit (Q102, IC101, Q101 [Main], Q702, IC701, Q701 [Sub]). The amplified signal is rectified at the noise detector (D371 [Main], D701 [Sub]) for conversion into DC voltage. The DC voltage is amplified at the DC amplifier circuit (Q105 [Main], Q705 [Sub]) and then applied to the noise blanker control circuit (Q52, Q107 [Main], Q652, Q707 [Sub]) to stop amplification of the IF amplifier circuit (Q51 [Main], Q651 [Sub]).
4-1-12 AGC CIRCUIT (MAIN UNIT)
The AGC (Auto Gain Control) circuit reduces IF amplifier gain to keep the audio output at a constant level.
A portion of the 10 MHz IF signal from the IF amplifier (Q352 [Main], Q852 [Sub]) is applied to the AGC detector circuit D303 [Main], D902 [Sub]). The detected signal is then amplified at the DC amplifier circuit (Q305 [Main], Q901 [Sub]) and then applied to the IF amplifiers (Q51, Q351, Q352 [Main], Q651, Q851, Q852 [Sub]).
When strong signals are received, the detected voltage increases and the output level of the DC amplifier, as AGC voltage, decreases. The AGC voltage is used for the bias voltage for the IF amplifiers, therefore, the IF amplifier gain is decreased.
AGC response time is controlled by changing the time constant at the AGC control line with a resistor and capacitor. While AGC is set to slow, the resistor (R312 [Main], R914 [Sub]) and capacitor (C306 [Main], C911 [Sub]) are connected to the AGC control line. While AGC is set to fast, R311 [Main], R913 [Sub] are connected to the AGC control line. Due to Q304 and Q303 [Main]/Q905 and Q904 [Sub] being switched ON that controlled by the “AGSM”, “AGFM” [Main], “AGSS”, “AGFS” [Sub]. Also, R310 [Main]/R912 [Sub] is connected to the AGC control line due to Q302 [Main]/Q903 being switched ON while scanning for faster response than AGC fast mode that controlled by the “AGRM” [Main], “AGRS” [Sub].
4-1-13 S-METER CIRCUIT (MAIN UNIT)
The S-meter circuit indicates the relative received signal strength while receiving and changes depending on the received signal strength.
(1) FM mode
Some of the amplified IF signal is applied to the S-meter detector section in the FM IF IC (IC401 [Main], IC951 [Sub]) to be converted into DC voltage. The converted signal is output from pin 12 and applied to the meter amplifier circuit (IC1804c [Main], IC1804a [Sub]). The amplified signal is then applied to the CPU (DISPLAY board; IC1) passing through the analog multiplexer (DISPLAY board; IC4, pins 12 and 1) via the “SMLM [Main]/SMLS [Sub]” line. The CPU then outputs S-meter control signal.
(2) SSB and CW modes
A portion of the AGC control signal is applied to the meter amplifier (IC1804d [Main], IC1804b [Sub]). The amplified signal is then applied to the CPU via the analog multiplexer to control the S-meter.
4-2-1 MICROPHONE AMPLIFIER CIRCUIT (MAIN UNIT)
The microphone amplifier circuit amplifies audio signals from the microphone or ACC connector and then applies them to the FM modulation or balanced modulator circuit. One microphone amplifier circuit is commonly used for both FM/SSB and VHF/UHF.
Audio signals from the [MIC] connector enter the microphone amplifier IC (IC1701, pin 22) and are then amplified at the microphone amplifier or speech compressor section. Compression level is adjusted by the setting mode.
The amplified or compressed signals are applied to the VCA section of IC1701. The microphone gain setting from the D/A converter (IC1521, pin 8) is applied to the VCA control terminal (IC1701, pin 10). The resulting signals from pin 9 are then applied to the buffer-amplifier (Q1651) via the analog switch (IC1653a). External modulation input from the [ACC] socket (pin 4) is also applied to Q1651.
• AGC CIRCUIT FOR MAIN BAND
D302
RFGM (RF/SQL control)
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AGC det. |
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D303 |
2nd IF |
C309 |
signal |
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C310 |
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–5 V |
R316 |
R317 |
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Q306 |
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R315 |
C311 |
C312 |
R314 |
9 V
SCAN |
FAST |
SLOW |
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AGC line |
R310 |
R311 |
R312 |
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C306 |
R313 |
C308 |
R302 13 |
IC1804d |
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Meter |
14 |
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12 |
amp. |
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“SMLM” |
Q302 |
Q303 |
Q304 |
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R303 |
R304 |
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S-meter signal |
C307 |
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4 - 3
While in SSB mode, the amplified signals from the buffer amplifier (Q1651) are then applied to the balanced modulator (IC201).
While in AM/FM mode, the amplified signals from the buffer amplifier (Q1651) are applied to the limiter amplifier (IC1651b) and splatter filter (IC1651a). The signals are passed through the buffer amplifier ((IC1652a) and are then applied to the AM detector (IC1807d, D1652) in AM mode or to the varactor diode (D253) in FM mode.
4-2-2 MODULATION CIRCUIT (MAIN UNIT)
(1) FM mode
The amplified audio signals from IC1701 are pre-empha- sized and limited at IC1651b and then passed through the splatter filter (IC1651a). The filtered signals are then applied to the FM modulation circuit (D253) via the FM deviation level controller (IC1803 pins 21, 22) and buffer amplifier (IC1652a). Also, subaudible tone signals from the CPU (DISPLAY board; IC1 pin 4) are applied to the FM modulation circuit (D253) via the splatter filter (IC1651a).
The FM modulation circuit changes the generating frequency of the FM local oscillator (Q254, X251) to generate an FM signal. The modulated IF signal is passed through the RF limiter (Q253) and then applied to the transmit IF amplifier circuit.
When 9600 bps mode is selected, audio signals from the ACC connector bypass the amplifiers and are applied to IC1654a directly via the external modulation switch (IC1531, pins 12, 1). In such cases, the deviation detector (IC1807d) cuts off the audio line when over modulation is detected.
(2) SSB and CW modes
The amplified audio signals from Q1651 are mixed with BFO signals at the balanced mixer circuit (IC201) to produce a 10 MHz IF signal. The mixed signal is still a DSB signal, therefore, the mixed signal passes through bandpass filter circuit (FI151) to suppress unwanted side band signals. The filtered signal is applied to the transmit IF amplifier circuit
• Transmit IF frequencies
Mode |
Transmit IF signal |
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USB |
10.8485 MHz |
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LSB |
10.8515 MHz |
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CW |
10.8491 MHz |
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4-2-3 CW KEYING CIRCUIT (MAIN UNIT)
When the CW key is closed, control signal is output from CPU (LOGIC unit) and controls break-in operation, the side tone signal.
Keying signals (DOT and DASH) from the [KEY] jack (J1401) are applied to the CPU (DISPLAY board; IC1, pins 49, 48 respectively), and the CPU outputs a CW control signal (KDS1) from pin 21. The CW control signal is applied to the balanced mixer (IC201) via Q201, D201, D207 to unbalance the IC201 input bias voltage and creates a carrier signal. R202 determines the transmit delay timing.
4-2-4 TRANSMIT IF AMPLIFIER CIRCUIT (MAIN UNIT)
The modulated IF signal from a modulation circuit is applied to the IF amplifier circuit (Q1). The amplified IF signal is then applied to the VHF/UHF transmit circuit (PA unit) via the VHF /UHF switching circuit (D52, D53).
The gain of the IF amplifier circuit (Q1) is controlled by the ALC amplifier circuit (IC1601b). Therefore, the IF amplifier is reduced when the output power increases.
4-2-5 RF CIRCUIT (PA UNIT)
The RF circuit consists of mixer and drive amplifiers to obtain the desired frequency and level needed at a PA circuit, respectively.
(1) VHF band
The IF signal from the MAIN unit (P501) is mixed with an LO signal from the VHF VCO circuit (PLL unit; Q191, D191–D194) at the double-balanced mixer circuit (Q501, Q502, D502) to be converted into VHF transmit frequency. The mixed signal is passed through the attenuator (R512–R514) and two-stage tunable bandpass filter (D503, L533 and D504, L504) to suppress spurious components. The filtered signals are then amplified at the YGR amplifier (IC501) and passed through the attenuator (R562–R531) and another two-stage tunable bandpass filter (D641, L641 and D642, L642)
The amplified and filtered RF signal is applied to the drive amplifier circuit that is used VHF and UHF signals commonly.
(2) UHF band
The IF signal from the MAIN unit (P1) is mixed with a 2nd LO signal at the double-balanced mixer circuit (Q1, Q2) to produce a 2nd IF signal (71.25 MHz). The 2nd LO signal (60.4 MHz) is generated at the reference oscillator and doubler circuit (PLL unit; X512, Q551) via LO amplifier (IC40). The 2nd IF signal is amplified at the buffer amplifier (Q3) via the bandpass filter circuit (L3, L4, C12, C13, C15–C17, C24, C26). The amplified 2nd IF signal is applied to the 1st mixer circuit (D190, L190, L191) passing through the attenuator (R12–R14) and low-pass filter (L381, L382, C381–C383).
The 1st mixer circuit (D190, L190, L191) converts the 2nd IF signal into a UHF transmit frequency with a 1st LO signal from the UHF VCO circuit (PLL unit; Q391, D391–D394). The converted RF signal is passed through the bandpass filter (FI200 and FI201) where unwanted LO signal emission is reduced. The filtered signal is attenuated at R204–R206 and amplified at the YGR amplifier (IC200), and is then applied to the drive amplifier circuit via the band pass filter (FI202) and another YGR amplifier (Q200).
4-2-6 DRIVE AMPLIFIER CIRCUIT (PA UNIT)
The drive amplifier circuit amplifies RF signals from the VHF or UHF RF circuit to obtain a level needed at the power amplifier circuit. One drive amplifier circuit is commonly used for both VHF and UHF band signals.
The signals from the VHF or UHF RF circuit are amplified at the drive amplifier circuit (Q101, Q121, Q131, DRV board; Q930). The amplified VHF signals are passed through the
4 - 4
low-pass filter and UHF signal are high-pass filter, and then applied to the VHF and UHF power amplifier circuit separately.
4-2-7 POWER AMPLIFIER CIRCUIT (PA UNIT)
The power amplifier circuit amplifies the RF signals to the specified output power.
(1) VHF power amplifier circuit
The RF signal from the low-pass filter circuit is applied to the VHF power amplifier circuit (Q651, Q652) to obtain a stable 100 W of RF output power. The amplified RF signal is applied to the antenna connector (CHASSIS; J1) via the power detector (D720, D721), transmit/receive switching relay (RL700) and low-pass filter (L723–L721, C728–C726, C728) circuits.
(2) UHF power amplifier circuit
The RF signal from the high-pass filter is applied to the UHF power amplifier circuit (Q151, Q152) to obtain a stable 75 W of RF output power. The amplified RF signal is applied to the antenna connector (CHASSIS; J2) via the transmit/receive switching circuit (D182–D185), low-pass filter (L181, L180, C188–C184) and power detector (D180, D181) circuits.
4-2-8 ALC CIRCUIT (PA AND MAIN UNITS)
The ALC (Automatic Level Control) circuit protects the power amplifiers (PA unit; Q651, Q652 for VHF and Q151, Q152 for UHF) from a mismatched output load. Also, the ALC circuit controls the gain of the transmit IF amplifier in order for the transceiver to output even when the supplied voltage shifts, etc.
The RF power level is detected at the power detector circuit (PA unit; D720–D721 for VHF, D180, D181 for UHF) to be converted into DC voltages. The detected voltage (VFOR for VHF or UFOR for UHF) is passed through the switching diode, and are then applied to the differential amplifier (MAIN unit; IC1601b) via the FOR line. A reference voltage (POCV) for IC1601b is controlled by the [RF PWR] control to output reference voltages. The output voltage is applied to the transmit IF amplifier circuit (MAIN unit; Q1) as an ALC signal to control the amplifier gain.
When the VFOR/UFOR voltage increased, the output from the differential amplifier will be decrease to reduce the IF amplifier gain. This adjusts the RF output power until the VFOR/UFOR and POCV voltage are well balanced.
4-2-9 APC CIRCUIT (MAIN UNIT)
The APC (Automatic Power Control) circuit protects the power amplifiers on the PA unit from excessive current.
Current drain of power amplifiers is detected by voltage drops at a resistor (PA unit; R305) between VCC and PAHV lines. The original voltage (ICH) and dropped voltage (ICL) are applied to the APC differential amplifier (MAIN unit; IC1601d).
The signal output from the differential amplifier reduces IF amplifier gain until these voltages are well-balanced.
IC-910H contains 2 PLL circuits and 1 local oscillator. The VHF and UHF PLL circuits adopt “Icom’s original I-loop PLL” to obtain very fast lock up times.
4-3-1 VHF PLL CIRCUIT (PLL UNIT)
The VHF PLL circuit generates the 1st LO frequency, and the signal is applied to the VHF 1st mixer circuit in the PA unit as the “A1LO” signal. The PLL circuit consists of a VCO, prescaler and DDS circuits.
The signal generated at the VHF VCO circuit (Q191, D191–D194) is amplified at the buffer amplifiers (Q192, Q272), then applied to the prescaler circuit (IC271). The prescaler circuit divides the applied signal, and outputs it to the VHF DDS circuit (IC131) via the buffer amplifier (Q271). The VHF DDS circuit generates digital signals using the applied signals as a clock frequency. The phase detector section in IC131 compares its phase with the reference frequency that is generated at the reference oscillator (X512). IC131 outputs off-phase components as pulse signals via pins 51, 52.
The output pulses are converted into DC voltage at the loop filter circuit (IC161a) and then applied to the VHF VCO circuit.
The D/A converter (R101–R124), low-pass filter (L101–L103, C103–C110) and buffer amplifier (IC101) circuits are connected to the DDS output to convert the digital oscillated signals into smooth analog signals.
4-3-2 UHF PLL CIRCUIT (PLL UNIT)
The UHF PLL circuit generates the 1st LO frequency, and the signal is applied to the UHF 1st mixer circuit in the PA unit as the “B1LO” signal. The PLL circuit consists of a VCO, prescaler and DDS circuits.
The signal generated at the UHF VCO circuit (Q391, D391–D394) is amplified at the buffer amplifiers (Q392, Q472), then applied to the prescaler circuit (IC471). The prescaler circuit divides the applied signal, and outputs it to the UHF DDS circuit (IC331) via the buffer amplifier (Q471).
The D/A converter (R301–R324), low-pass filter (L301–L303, C103–C311) and buffer amplifier (IC301) circuits are connected to the DDS output to convert the digital oscillated signals into smooth analog signals.
4-4 UX-910 (1200 MHz BAND UNIT)
UX-910 is an optional 1200 MHz band unit for IC-910H. This unit covers 1240–1300 MHz frequency range.
4-4-1 ANTENNA SWITCHING CIRCUIT (for RX)
Received signals from the antenna connector (CHASSIS; J501) are applied to the transmit/receive switching circuit (RL51).
The transmit/receive switching circuit leads receive signal to the RF circuit while receiving. However, the circuit leads the transmit signal from the RF power amplifier to the antenna connector while transmitting.
4 - 5
The passed signals are then applied to the RF amplifier circuit.
4-4-2 1200 MHz RF CIRCUIT (for RX)
Received signals from the transmit/receive switching circuit are passed through the high-pass filter (L285–L287, L289, C297–C300) and pre-amplifier (Q281) and are applied to the RF amplifier circuit (Q271) via the band pass filter circuit (FI281).
The amplified signals are then passed through the another bandpass filter (FI271) to suppress unwanted signals. The filtered signals are then applied to the 1st mixer circuit (IC241).
4-4-3 1200 MHz 1ST/2ND MIXER CIRCUITS (for RX)
The 1st/2nd mixer circuits convert the received signals into a fixed frequency of the 10 MHz IF signal with a PLL output frequencies. By changing the PLL frequency, only the desired frequency will pass through a filter at the next stage.
The filtered signals from the bandpass filter are mixed with 1st LO signals at the mixer circuit (IC241) to produce a 1st IF signal (243.95 MHz). The 1st LO signals (996.0 MHz–1076.1 MHz) are PLL output frequency, which comes from the 1st LO VCO circuit (Q451, Q452).
The 1st IF signal is passed through the bandpass filter (FI241) to suppress unwanted signals, and then applied to the 2nd mixer circuit (Q221).
The applied signal is mixed with 2nd LO signal coming from the 2nd LO VCO circuit (Q731) to produce a 10.85 MHz [Main], 10.95 MHz [Sub] 2nd IF signal. The 2nd IF signal is passed through the main/sub switching circuit (Q161, Q164), and then output to the MAIN unit of IC-910H via J311 (pin 25 [Main], pin 1 [Sub]).
4-4-4 IF AMPLIFIER CIRCUIT (for TX)
The modulated 2nd IF signal from IC-910H via J311 is amplified at the 2nd IF amplifier (Q81), and is passed through the low-pass filter (L82, L83, C80, C85–C89) to suppress unwanted signals. The filtered signal is then applied to the 2nd mixer circuit.
The applied signal is mixed at the 2nd mixer circuit (D82, L84, L85) to converted into the 1st LO signal with the 2nd LO signal, which comes from the 2nd LO VCO (Q731).
Then the 1st LO signal is passed through the low-pass filter (L121, L122, C121–C125) and amplified at the 1st IF amplifier (IC111). The amplified signal is passed through the bandpass filter (FI101) between the attenuators (R104–R106) and (R133–R135), and are then applied to the 1st mixer circuit (IC131).
The signal is mixed with the 1st LO signal coming from the 1st LO VCO circuit (Q451, Q452) to converted into RF signals.
4-4-5 DRIVE/POWER AMPLIFIER CIRCUITS (for TX)
The RF signals from the 1st mixer circuit are passed through the bandpass filter (FI141) and low-pass filter (L141, L142, C142–C146), and then amplified at the YGR amplifier circuit (IC141).
The amplified signals are passed through the bandpass filter (FI1) to suppress spurious components, and are amplified at the pre-drive amplifier (Q36, Q38) and power module (IC21) to obtain a stable 10 W of output power.
The output signals from the power module (IC21) are passed through the duplexer circuit (RL51) and detector circuits of forwared voltage and refrected voltage, and are then applied to the antenna connector.
4-4-6 PLL CIRCUITS
UX-910 contains 2 frequency synthesizer circuit. This unit does not have a local oscillator circuit and uses a 30.2 MHz frequency from IC-910H as a reference frequency. The 2nd LO circuit adopt “Icom’s original I-loop PLL” to obtain 1 Hz pitch fine tuning.
The reference frequency from the IC-910H via J312 is amplified at the reference amplifier (IC601, Q601) and applied to the 2LO DDS IC (IC661). A portion of the reference signal is also applied to the divider circuit (IC610). The divided signal is applied to the 1LO PLL circuit (IC501).
4-4-7 1LO PLL CIRCUIT
The 1LO PLL circuit generates the 1st LO frequency, and the signal is applied to the 1st mixer circuit as the “1LO” signal.
An oscillated signal from the 1LO VCO (Q541, Q542) passes through the buffer amplifiers (Q551, Q681) and is applied to the PLL IC (IC501, pin 1) and is prescaled in the PLL IC based on the divided ratio (N-data). The reference signal is also applied to the PLL IC (IC501, pin 6). The PLL IC detects the out-of-step phase using the reference frequency and outputs it from pin 10. The output signal is passed through the active filter (IC502, Q511, Q512) and is then applied to the 1LO VCO circuit as the lock voltage.
4-4-8 2LO PLL CIRCUIT
The 2LO PLL circuit generates the 2nd LO frequency, and the signal is applied to the 2nd mixer circuit as the “2LO” signal.
The signal generated at the 2LO VCO circuit (Q731) is amplified at the buffer amplifiers (Q741, Q761), then applied to the prescaler circuit (IC761). The prescaler circuit divides the applied signal, and outputs it to the DDS circuit (IC661) via the buffer amplifier (Q762). The DDS circuit generates digital signals using the applied signals as a clock frequency. The phase detector section in IC661 compares its phase with the reference frequency from the reference amplifier (IC601). IC661 outputs off-phase components as pulse signals via pins 51, 52.
The output pulses are converted into DC voltage at the loop filter circuit (IC701a) and then applied to the 2LO VCO circuit.
The D/A converter (R621–R645), low-pass filter (L651–L653, C651–C657) and buffer amplifier (IC621) circuits are connected to the DDS output to convert the digital oscillated signals into smooth analog signals.
4 - 6
SECTION 5 ADJUSTMENT PROCEDURES
■ REQUIRED TEST EQUIPMENT
EQUIPMENT |
GREDE AND RANGE |
EQUIPMENT |
GREDE AND RENGE |
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DC power supply |
Output voltage |
: 13.8 V DC |
Audio generator |
Frequency range |
: 300–3000 Hz |
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Current capacity |
: 30 A or more |
Measuring range |
: 1–500 mV |
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Measuring range |
: 1–150 W |
Standard signal |
Frequency range |
: 0.1–1500 MHz |
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RF power meter |
Frequency range |
: 120–1500 MHz |
Output level |
: 0.1 µV–32 mV |
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generator (SSG) |
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(terminated type) |
Impedance |
: 50 Ω |
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(–127 to –17 dBm) |
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SWR |
: Less than 1.2 : 1 |
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AC millivoltmeter |
Measuring range |
: 10 mV–10 V |
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Frequency range |
: 0.1–100 MHz |
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DC voltmeter |
Input impedance |
: 50 kΩ/V DC or better |
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Frequency counter |
Frequency accuracy |
: ±0.5 ppm or better |
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Sensitivity |
: 100 mV or better |
DC ammeter |
Measurement capability: 1 A/30 A |
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Frequency range |
: 0.1–500 MHz |
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RF voltmeter |
Spectram analyzer |
Frequency range |
: At least 150 MHz |
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Measuring range |
: 0.01–10 V |
Spectraum bandwidth |
: 100 kHz or more |
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FM deviation meter |
Frequency range |
: DC–500 MHz |
Attenuator |
Power attenuation |
: 50 or 60 dB |
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Measuring range |
: 0 to ±5 kHz |
Capacity |
: 150 W or more |
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Distortion meter |
Frequency range |
: 1 kHz ±10 % |
External speaker |
Input impedance |
: 8 Ω |
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Measuring range |
: 1–100 % |
Capacity |
: 5 W or more |
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Oscilloscope |
Frequency range |
: DC–20 MHz |
Terminator |
Resistance |
: 50 and 150 Ω |
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Measuring range |
: 0.01–20 V |
Capacity |
: 150 W or more |
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Digital multimeter |
Imput impeadance |
: 10 MΩ/DC or beter |
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‘ CONNECTIONS
CAUTION !
DO NOT transmit while an SSG is connected to the antenna connector.
Standard signal generator
DC power supply |
Ammeter |
to [DC 13.8 V] |
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Distortion meter |
to [EXT SP] |
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Speaker |
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TERMINATOR for software |
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adjustment (page 5-12). |
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2-conductor 3.5 (d) mm (1/8") Shouten inner and outer plugs.
IC-910H
Audio generator
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[MIC]
PTT
CAUTION !
When [P.AMP] switch is turned ON, DC voltage is applied to the antenna connector. This may damege the signal generator.
connector |
FM deviation meter |
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Attenuator |
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antenna |
Spectrum analyzer |
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theto |
RF power meter |
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JIG cable (A) |
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2.2 k |
JIG cable (B)
+9 V
2.2 k
5 - 1
5-2 PLL ADJUSTMENTS
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MEASUREMENT |
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ADJUSTMENT |
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ADJUSTMENT |
ADJUSTMENT CONDITION |
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VALUE |
POINT |
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UNIT |
LOCATION |
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UNIT |
ADJUST |
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30.2 MHz |
1 |
• Display frequency: Any |
PLL |
Connect an RF volt- |
–10 dBm (or more than |
PLL |
R570 |
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LEVEL |
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• Receiving |
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meter or |
spectram |
–11.5 dBm, when R570 |
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analyzer |
to |
check |
is in maximum posi- |
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point J541. |
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tion.) |
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REFERENCE |
1 |
• Display frequency: Any |
PLL |
Connect an RF volt- |
Maximum level |
PLL |
Adjust in |
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FREQUENCY |
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• Receiving |
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meter or |
spectram |
(–13 dBm to –7dBm) |
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sequence |
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analyzer |
to |
check |
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L551, L552 |
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point P551. |
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s e v e r a l |
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times. |
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2 |
This adjustment must be performed |
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Connect a frequency |
60.400000 MHz |
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The trimmer |
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at 5 minutes later after power ON. |
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counter |
to |
check |
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capacitor of |
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point P551. |
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X512. |
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144M LOCK |
1 |
• Display frequency: 173.9800 MHz |
PLL |
Connect |
a |
digital |
2.7 V |
PLL |
L193 |
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VOLTAGE |
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• Mode |
: USB |
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multimeter or oscillo- |
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• Receiving |
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scope to check point |
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CP100. |
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2 |
• Display frequency: 136.0200 MHz |
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0.6 V to 1.6 V |
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Verify |
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• Receiving |
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3 |
• Display frequency: 155.0000 MHz |
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Connect an RF volt- |
–10 dBm to –4 dBm |
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Verify |
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• Receiving |
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meter to check point |
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P251. |
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440M LOCK |
1 |
• Display frequency: 479.9800 MHz |
PLL |
Connect |
a |
digital |
3.4 V |
PLL |
C402 |
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VOLTAGE |
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• Mode |
: USB |
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multimeter or oscillo- |
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• Receiving |
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scope to check point |
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CP300. |
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2 |
• Display frequency: 420.0200 MHz |
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0.5 V to 1.5 V |
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Verify |
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• Receiving |
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3 |
• Display frequency: 450.0000 MHz |
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Connect an RF volt- |
–16 dBm to –10 dBm |
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Verify |
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• Receiving |
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meter to check point |
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P421. |
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MAIN BFO |
1 |
• Display frequency: Any |
PLL |
Connect an RF volt- |
–11 dBm to –5 dBm |
PLL |
Verify |
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LEVEL |
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• Mode |
:USB |
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meter to check point |
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• Receiving |
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P601. |
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SUB BFO |
2 |
• Sub display freq. : Any |
PLL |
Connect an RF volt- |
–11 dBm to –5 dBm |
PLL |
Verify |
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LEVEL |
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• Mode |
:USB |
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meter to check point |
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• Receiving |
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P701. |
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MEASUREMENT |
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ADJUSTMENT |
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ADJUSTMENT |
ADJUSTMENT CONDITION |
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VALUE |
POINT |
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UNIT |
LOCATION |
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UNIT |
ADJUST |
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FM TX-LO |
1 |
• Display frequency: Any |
MAIN |
Connect a frequency |
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10.85000 MHz |
MAIN |
L255 |
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FREQUENCY |
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• Mode |
: FM |
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counter to check |
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• Disconnect P501, P502 (PA unit) |
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point CP51. |
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from J51 and J52 on the MAIN unit. |
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• Apply no audio signals to [MIC] |
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connector. |
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• Transmitting |
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After adjustment, connect P501, P502 (PA unit) to J51, J52 on the MAIN. |
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5 - 2
• PLL AND MAIN UNITS
R570
30.2 MHz level adjustment
L193
144M lock voltage adjustment
P251
144M LO level check point
X512
Reference frequency adjustment
J541
30.2 MHz level check point
C402 |
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430M lock voltage |
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adjustment |
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CP300 |
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430M lock voltage |
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check point |
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P421 |
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430M LO level |
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check point |
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Referemce level |
L551 |
adjustment |
L552 |
P601 |
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Main BFO level check point
P701
Sub BFO level check point
CP100
144M lock voltage check point
P551
Reference frequency check point
L255
FM TX-LO frequency adjustment
J51 |
FM TX-LO |
J52 |
frequency |
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pre-setting
CP51
FM TX-LO frequency check point
5 - 3
Receiver adjustments must be performed after software adjustment (0) and (1). SUB band must be OFF when adjusting MAIN band, or main AF volume (max.counter clockwise) and SQL volume (max. clockwise) must be set when adjusting SUB band.
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MEASUREMENT |
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ADJUSTMENT |
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ADJUSTMENT |
ADJUSTMENT CONDITION |
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VALUE |
POINT |
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UNIT |
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LOCATION |
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UNIT |
ADJUST |
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144 M |
1 |
• Display frequency: Any |
PA |
Connect an RF volt- |
Maximum level |
PA |
L521 |
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RECEIVER |
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• Disconnect P501 (PA unit) from J51 |
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meter to check point |
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PEAK/GAIN |
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on the MAIN unit. |
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P501 via |
the |
JIG |
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• Connect a standard signal generator |
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cable (A). |
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to [VHF ANT] connector and set as: |
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Frequency : 146.0000 MHz |
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Level |
: 7.1 mV* (–30 dBm) |
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Modulation : OFF |
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• Receiving |
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2 |
• Receiving |
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–14 dBm |
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R547 |
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After adjustment, connect P501 (PA unit) to J51 on the MAIN unit. |
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144 M PEAK |
1 |
• Display frequency: 145.9800 MHz |
Rear |
Connect an distortion |
Minimum audio distor- |
MAIN |
Adjust |
in |
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(MAIN BAND) |
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• Mode |
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: FM |
panel |
meter to [EXT |
SP] |
tion level |
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sequence |
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• Connect an SSG to [VHF ANT] con- |
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connector |
with |
an |
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L51, |
L52 |
||||
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nector and set as: |
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8 Ω load. |
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s e v e r a l |
||||
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Frequency : 145.9800 MHz |
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times. |
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Level |
: 3.2 µV* (–97 dBm) |
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Modulation : 1 kHz/±5.0 kHz Dev. |
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• Receiving |
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2 |
• Mode |
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: USB |
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Connect an AC milli- |
Maximum noise output |
|
L53, L352, |
|||||
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• Set an SSG as |
: |
|
volt meter to [EXT |
level |
|
L353, L354 |
||||||
|
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Frequency : 145.9815 MHz |
|
SP] |
connector |
with |
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Level |
: 0.1 µV* (–127 dBm) |
|
an 8 Ω load. |
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Modulation : OFF |
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• Receiving |
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144 M |
1 |
• Display frequency: 145.9800 MHz |
Rear |
Connect an AC milli- |
1.0 V (0 dB) |
Front |
main [AF] |
|||||||
TOTAL GAIN |
|
• Mode |
|
: USB |
panel |
volt |
meter |
to [EXT |
|
panel |
volume |
|||
(MAIN BAND) |
|
• Set an SSG as |
: |
|
SP] |
connector |
with |
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|
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Frequency : 145.9815 MHz |
|
an 8 Ω load. |
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Level |
: 1 mV* (–47 dBm) |
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Modulation : OFF |
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• Receiving |
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2 |
• Set an SSG as |
: |
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100 mV (20 dB of AF |
MAIN |
R360 |
|||
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Level |
: OFF |
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level difference as step |
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• Receiving |
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1.) |
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|||||
144 M PEAK |
1 |
• Sub display freq. : 145.9800 MHz |
Rear |
Connect an distortion |
Minimum audio distor- |
MAIN |
Adjust |
in |
||||||
(SUB BAND) |
|
• Mode |
|
: FM |
panel |
meter to [EXT |
SP] |
tion level |
|
sequence |
||||
|
|
• Connect an SSG to [VHF ANT] con- |
|
connector |
with |
an |
|
|
L651, L652 |
|||||
|
|
nector and set as: |
|
|
8 Ω load. |
|
|
|
|
s e v e r a l |
||||
|
|
Frequency : 145.9800 MHz |
|
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|
times. |
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||
|
|
Level |
: 3.2 µV* (–97 dBm) |
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Modulation : 1 kHz/±5.0 kHz Dev. |
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||
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• Receiving |
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||||
|
2 |
• Mode |
|
: USB |
|
Connect an AC milli- |
Maximum noise output |
|
L653, L851, |
|||||
|
|
• Set an SSG as |
: |
|
volt meter to [EXT |
level |
|
L852, L853 |
||||||
|
|
Frequency : 145.9815 MHz |
|
SP] |
connector |
with |
|
|
|
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|
|||
|
|
Level |
: 0.1 µV* (–127 dBm) |
|
an 8 Ω load. |
|
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||
|
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Modulation : OFF |
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||
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• Receiving |
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||||||
144 M |
1 |
• Display frequency: 145.9800 MHz |
Rear |
Connect an AC milli- |
1.0 V (0 dB) |
Front |
sub [AF] |
|||||||
TOTAL GAIN |
|
• Mode |
|
: USB |
panel |
volt |
meter |
to [EXT |
|
panel |
volume |
|||
(SUB BAND) |
|
• Set an SSG as |
: |
|
SP] |
connector |
with |
|
|
|
|
|
||
|
|
Frequency : 145.9815 MHz |
|
an 8 Ω load. |
|
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|||
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|
Level |
: 1 mV* (–47 dBm) |
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|
Modulation : OFF |
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||
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• Receiving |
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||
|
2 |
• Set an SSG as |
: |
|
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|
|
100 mV (20 dB of AF |
MAIN |
R857 |
|||
|
|
Level |
: OFF |
|
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|
|
level difference as step |
|
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• Receiving |
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|
|
1.) |
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*This output level of a standard signal generator (SSG) is indicated as SSG’s open circuit.
5 - 4
• PA UNIT
144M receiver |
R547 |
|
peak/gain |
||
|
adjustment L521
P501
144M receiver peak/gain check point
• MAIN UNIT
144M peak |
L353 |
|
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|||
adjustment |
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for main band |
L354 |
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R360 |
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144M total gain |
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|
||
adjustment |
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for main band |
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|
144M peak |
L352 |
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|||
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||
adjustment |
L53 |
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||
L52 |
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|
||
for main band |
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L51 |
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R857
144M total gain adjustment
for sub band
L853
L852
L851 144M peak adjustment
L653 for sub band
L652
L651
J51
144M receiver peak/gain pre-setting
5 - 5
RECEIVER ADJUSTMENTS (continued)
|
|
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|
|
|
MEASUREMENT |
|
|
|
ADJUSTMENT |
||||
ADJUSTMENT |
ADJUSTMENT CONDITION |
|
|
|
VALUE |
POINT |
||||||||
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||||||||
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||||||
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|
UNIT |
|
LOCATION |
|
UNIT |
ADJUST |
|||
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|
|||
430 M PEAK |
1 |
• Display frequency: 435.0200 MHz |
|
MAIN |
Connect |
a |
digital |
Maximum voltage |
PA |
L22, |
||||
(MAIN BAND) |
|
• Mode |
|
: FM |
|
|
multimeter or oscillo- |
|
|
L23, |
||||
|
|
• Connect a standard signal generator |
|
|
scope to check point |
|
|
L282, |
||||||
|
|
to [UHF ANT] connector and set as: |
|
|
CP851. |
|
|
|
|
|
L283 |
|||
|
|
Frequency : 435.0200 MHz |
|
|
|
|
|
|
|
|
|
|
||
|
|
Level |
: 1 µV* (–107 dBm) |
|
|
|
|
|
|
|
|
|
|
|
|
|
Modulation : 1 kHz/±5.0 kHz Dev. |
|
|
|
|
|
|
|
|
|
|
||
|
|
• Receiving |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
430 M PEAK |
1 |
• Sub display freq. : 435.0200 MHz |
|
MAIN |
Connect |
a |
digital |
Maximum voltage |
PA |
L280, |
||||
(SUB BAND) |
|
• Mode |
|
: FM |
|
|
multimeter or oscillo- |
|
|
L281 |
||||
|
|
• Set an SSG as |
: |
|
|
scope to check point |
|
|
|
|||||
|
|
Frequency : 435.0200 MHz |
|
|
CP852. |
|
|
|
|
|
|
|||
|
|
Level |
: 1 µV* (–107 dBm) |
|
|
|
|
|
|
|
|
|
|
|
|
|
Modulation : 1 kHz/±5.0 kHz Dev. |
|
|
|
|
|
|
|
|
|
|
||
|
|
• Receiving |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
430 M |
1 |
• Display frequency: 435.0200 MHz |
|
Rear |
Connect an AC milli- |
1.0 V (0 dB) |
Front |
main [AF] |
||||||
TOTAL GAIN |
|
• Mode |
|
: USB |
|
panel |
volt |
meter |
to |
[EXT |
|
panel |
volume |
|
(MAIN BAND) |
|
• Set an SSG as |
: |
|
|
SP] |
connector with |
|
|
|
||||
|
|
Frequency : 435.0215 MHz |
|
|
an 8 Ω load. |
|
|
|
|
|
||||
|
|
Level |
: 1 mV* (–47 dBm) |
|
|
|
|
|
|
|
|
|
|
|
|
|
Modulation : OFF |
|
|
|
|
|
|
|
|
|
|
||
|
|
• Receiving |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2 |
• Set an SSG as |
: |
|
|
|
|
|
|
|
100 mV (20 dB of AF |
PA |
R61 |
|
|
|
Level |
: OFF |
|
|
|
|
|
|
|
level difference as step |
|
|
|
|
|
• Receiving |
|
|
|
|
|
|
|
|
|
1.) |
|
|
|
|
|
|
|
|
|
|
|
||||||
NOISE |
1 |
• Display frequency: 145.9800 MHz |
|
MAIN |
Connect an oscilloMaximum noise wave- |
MAIN |
L102, |
|||||||
BLANKER |
|
• Mode |
|
: USB |
|
|
scope to check point |
form |
|
L103 |
||||
(MAIN BAND) |
|
• [NB] |
|
: OFF |
|
|
CP101. |
|
|
|
|
|
|
|
|
|
• Connect an SSG to [VHF ANT] con- |
|
|
|
|
|
|
|
|
|
|
||
|
|
nector and set as : |
|
|
|
|
|
|
|
|
|
|
||
|
|
Frequency : 145.98150 MHz |
|
|
|
|
|
|
|
|
|
|
||
|
|
Level |
: 5.6 µV* (–92 dBm) |
|
|
|
|
|
|
|
|
|
|
|
|
|
Modulation : OFF |
|
|
|
|
|
|
|
|
|
|
||
|
|
and apply following signal to [VHF |
|
|
|
|
|
|
|
|
|
|
||
|
|
ANT] connector. |
|
|
|
|
|
|
|
|
|
|
|
100msec.
1msec.
•Receiving
2 |
• [NB] |
|
: ON |
|
|
The noise |
must |
be |
|
Verify |
||
|
|
• Set an SSG as |
: |
|
|
|
blanked. |
|
|
|
|
|
|
|
Level |
: 3.2 µV* (–97 dBm) |
|
|
|
|
|
|
|
||
|
|
• Receiving |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
(SUB BAND) 3 |
• Sub display freq. : |
145.9800 MHz |
|
Connect an oscillo- |
Maximum noise wave- |
|
L703, |
|||||
|
|
• Mode |
|
: USB |
|
scope to check point |
form |
|
|
|
L704 |
|
|
|
• [NB] |
|
: OFF |
|
CP701. |
|
|
|
|
|
|
|
|
• Set an SSG as |
: |
|
|
|
|
|
|
|
|
|
|
|
Level |
: 5.6 µV* (–92 dBm) |
|
|
|
|
|
|
|
||
|
|
• Receiving |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
4 |
• [NB] |
|
: ON |
|
|
The noise |
must |
be |
|
Verify |
||
|
|
• Set an SSG as |
: |
|
|
|
blanked. |
|
|
|
|
|
|
|
Level |
: 3.2 µV* (–97 dBm) |
|
|
|
|
|
|
|
||
|
|
• Receiving |
|
|
|
|
|
|
|
|
|
|
*This output level of a standard signal generator (SSG) is indicated as SSG’s open circuit.
5 - 6