Hyundai GMS90X52C, GMS90X54C, GMS90X51C User Manual.pdf

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HYUNDAI MICRO ELECTRONICS 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS90X51C

GMS90X52C

GMS90X54C

User’s Manual (Ver. 1.0)

+ < 8 1 ' $ ,

MicroElectronics

Semiconductor Group of Hyundai Electronics Industrial Co., Ltd.

Version 1.0

Published by

MCU Application Team

©2001 HYUNDAI MicroElectronics All right reserved.

Additional information of this manual may be served by HYUNDAI MicroElectronics offices in Korea or Distributors and Representatives listed at address directory.

HYUNDAI MicroElectronics reserves the right to make changes to any information here in at any time without notice.

The information, diagrams and other data in this manual are correct and reliable; however, HYUNDAI MicroElectronics is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.

GMS90X5XC Series

HYUNDAI MicroElectronics

Device Naming Structure

GMS90X5XC - GCXXX XX XX

MicroElectronics MCU

Mask ROM version

HYUNDAI

 

Frequency

Blank: 12MHz

16:16MHz

24:24MHz

40:40MHz

Package Type

Blank: 40PDIP

PL: 44PLCC

Q:44MQFP

ROM Code serial No.

ROM size

1:4k bytes

2:8k bytes

4:16k bytes

Operating Voltage

C: 4.25~5.5V

L: 2.7~3.6V

GMS90X5XC Series Selection Guide

Operating

ROM size (bytes)

RAM size

Device Name

Operating

 

Voltage (V)

MASK

(bytes)

Frequency (MHz)

 

 

 

 

 

 

 

 

 

 

4.25~5.5

4K

128

GMS90C51C

12/24/40

 

8K

256

GMS90C52C

12/24/40

 

16K

256

GMS90C54C

12/24/40

 

 

 

 

 

2.7~3.6

4K

128

GMS90L51C

12/16

 

8K

256

GMS90L52C

12/16

 

16K

256

GMS90L54C

12/16

 

 

 

 

 

Jan. 2001 Ver 1.0

GMS90X5XC Series

HYUNDAI MicroElectronics

GMS90C51C

GMS90L51C(Low voltage versions)

Fully compatible to standard MCS-51 microcontroller

Wide operating frequency up to 40MHz

(for more detail, see “GMS90X5XC Series Selection Guide”)

X2 Speed Improvement capability (6 clocks/machine cycle) 20MHz @5V (Equivalent to 40MHz @5V)

8MHz @3V (Equivalent to 16MHz @3V)

4K × 8 ROM

128 × 8 RAM

64K external program memory space

64K external data memory space

Four 8-bit ports

Two 16-bit Timers / Counters

USART

Programmable ALE pin enable / disable (Low EMI)

Five interrupt sources, two priority levels

Power saving Idle and power down mode

2.7Volt low voltage version available

P-DIP-40, P-LCC-44, P-MQFP-44 package

Block Diagram

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RAM

 

PORT 0

 

 

 

 

I/O

 

 

 

 

 

 

 

 

128 ×

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T 0

CPU

 

 

8-BIT

PORT 1

 

 

 

 

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

USART

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T 1

 

 

 

 

PORT 2

 

 

 

 

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

ROM / EPROM

 

PORT 3

 

 

 

 

I/O

 

 

 

 

 

 

 

 

4K ×

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Jan. 2001 Ver 1.0

GMS90X5XC Series

HYUNDAI MicroElectronics

GMS90C52C/54C

GMS90L52C/54C(Low voltage versions)

Fully compatible to standard MCS-51 microcontroller

Wide operating frequency up to 40MHz

(for more detail, see “GMS90X5XC Series Selection Guide”)

X2 Speed Improvement capability (6 clocks/machine cycle) 20MHz @5V (Equivalent to 40MHz @5V)

8MHz @3V (Equivalent to 16MHz @3V)

8K/16K bytes ROM

256 × 8 RAM

64K external program memory space

64K external data memory space

Four 8-bit ports

Three 16-bit Timers / Counters (Timer2 with up/down counter feature)

USART

One clock output port

Programmable ALE pin enable / disable (Low EMI)

Six interrupt sources, two priority levels

Power saving Idle and power down mode

2.7Volt low voltage version available

P-DIP-40, P-LCC-44, P-MQFP-44 package

Block Diagram

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RAM

 

 

PORT 0

 

 

 

 

I/O

 

 

 

 

 

 

 

 

 

 

 

 

256 × 8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T 2

T 0

CPU

 

8-BIT

PORT 1

 

 

 

 

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

USART

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T 1

 

 

 

PORT 2

 

 

 

 

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ROM / EPROM

 

 

 

 

 

 

 

 

GMS90X52C: 8K

× 8

PORT 3

 

 

 

 

I/O

 

 

 

 

 

 

 

 

GMS90X54C: 16K × 8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Jan. 2001 Ver 1.0

1

HYUNDAI MicroElectronics

GMS90X5XC Series

PIN CONFIGURATION

44-PLCC Pin Configuration (top view)

INDEX

CORNER

P1.5 7

P1.6 8

P1.7 9

RESET 10

RxD / P3.0 11

N.C.* 12

TxD / P3.1 13

INT0 / P3.2 14

INT1 / P3.3 15 T0 / P3.4 16 T1 / P3.5 17

 

P1.4

 

P1.3

P1.2

T2EX

 

T2

N.C.*

 

 

 

AD0

 

AD1

 

AD2

 

AD3

 

 

 

P1.1/

 

P1.0/

 

V

P0.0/

 

P0.1/

 

P0.2/

 

P0.3/

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

5

4

3

2

1

44

 

43

42

41

40

 

39 P0.4 / AD4

38 P0.5 / AD5

37 P0.6 / AD6

36 P0.7 / AD7

35 EA / VPP

34 N.C.*

33 ALE / PROG

32 PSEN

31 P2.7 / A15

30 P2.6 / A14

29 P2.5 / A13

18

19

20

21

22

 

23

24

25

26

27

28

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

/WRP3.6

/RDP3.7

XTAL2

XTAL1

 

V

N.C.*

 

P2.0/ A8

 

P2.1/ A9

 

P2.2/ A10

 

/P2.3A11

 

P2.4/ A12

 

 

 

 

 

 

 

 

SS

 

 

 

 

 

 

 

 

 

 

 

N.C.: Do not connect.

2

Jan. 2001 Ver 1.0

GMS90X5XC Series

HYUNDAI MicroElectronics

40-PDIP Pin Configuration (top view)

 

 

 

T2

/ P1.0

 

 

 

 

 

VCC

 

 

 

 

 

 

 

1

40

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T2EX / P1.1

 

2

39

 

 

P0.0

/ AD0

 

 

 

 

 

 

P1.2

 

3

38

 

 

P0.1

/ AD1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.3

 

4

37

 

 

P0.2

/ AD2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.4

 

5

36

 

 

P0.3

/ AD3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.5

 

6

35

 

 

P0.4

/ AD4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.6

 

7

34

 

 

P0.5

/ AD5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.7

 

8

33

 

 

P0.6

/ AD6

 

 

 

 

 

 

 

 

 

 

 

 

RESET

 

9

32

 

 

P0.7

/ AD7

 

 

 

 

 

RxD / P3.0

 

 

 

 

 

 

 

 

 

10

31

 

 

EA

/ VPP

 

 

 

 

 

TxD / P3.1

 

11

30

 

 

ALE /

 

 

 

 

 

 

 

 

 

 

 

PROG

 

 

 

 

 

 

 

 

 

 

 

INT0

/ P3.2

 

12

29

 

 

 

 

 

 

 

 

 

 

PSEN

 

 

 

 

 

 

 

 

 

 

 

 

INT1

/ P3.3

 

13

28

 

 

P2.7

/ A15

 

 

 

 

 

 

 

 

T0 / P3.4

 

14

27

 

 

P2.6

/ A14

 

 

 

 

 

 

 

 

T1 / P3.5

 

 

 

 

 

 

 

15

26

 

 

P2.5

/ A13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WR

/ P3.6

 

16

25

 

 

P2.4

/ A12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RD

/ P3.7

 

17

24

 

 

P2.3

/ A11

 

 

 

 

 

 

 

XTAL2

 

18

23

 

 

P2.2

/ A10

 

 

 

 

 

 

 

XTAL1

 

19

22

 

 

P2.1

/ A9

 

 

 

 

 

 

 

 

 

VSS

 

20

21

 

 

P2.0

/ A8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Jan. 2001 Ver 1.0

3

HYUNDAI MicroElectronics

GMS90X5XC Series

44-MQFP Pin Configuration (top view)

P1.5

P1.6

P1.7

RESET

RxD / P3.0

N.C.*

TxD / P3.1

INT0 / P3.2

INT1 / P3.3 T0 / P3.4 T1 / P3.5

 

 

 

T2EX

T2

 

 

AD0

AD1

AD2

AD3

P1.4

P1.3

P1.2

P1.1 /

P1.0 /

N.C.*

CC

P0.0 /

P0.1 /

P0.2 /

P0.3 /

V

44

43

42

41

40

39

38

37

36

35

34

1

 

 

 

 

 

 

 

 

 

33

2

 

 

 

 

 

 

 

 

 

32

3

 

 

 

 

 

 

 

 

 

31

4

 

 

 

 

 

 

 

 

 

30

5

 

 

 

 

 

 

 

 

 

29

6

 

 

 

 

 

 

 

 

 

28

7

 

 

 

 

 

 

 

 

 

27

8

 

 

 

 

 

 

 

 

 

26

9

 

 

 

 

 

 

 

 

 

25

10

 

 

 

 

 

 

 

 

 

24

11

 

 

 

 

 

 

 

 

 

23

12

13

14

15

16

17

18

19

20

21

22

WR / P3.6

RD / P3.7

XTAL2

XTAL1

SS

N.C.*

P2.0 / A8

P2.1 / A9

P2.2 / A10

P2.3 / A11

P2.4 / A12

V

P0.4 / AD4

P0.5 / AD5

P0.6 / AD6

P0.7 / AD7

EA / VPP

N.C.*

ALE / PROG

PSEN P2.7 / A15 P2.6 / A14 P2.5 / A13

N.C.: Do not connect.

4

Jan. 2001 Ver 1.0

GMS90X5XC Series

HYUNDAI MicroElectronics

Logic Symbol

VCC VSS

 

XTAL1

 

 

 

 

 

 

 

 

 

 

 

 

 

Port 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XTAL2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8-bit Digital I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Port 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RESET

 

 

 

 

 

 

 

 

 

 

 

 

8-bit Digital I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Port 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8-bit Digital I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EA/VPP

 

 

 

 

 

 

 

 

 

 

 

 

Port 3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ALE/PROG

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8-bit Digital I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PSEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Jan. 2001 Ver 1.0

5

HYUNDAI MicroElectronics GMS90X5XC Series

PIN DEFINITIONS AND FUNCTIONS

 

 

Pin Number

 

Input/

 

 

 

 

 

 

 

Symbol

 

 

 

 

 

 

 

 

 

 

 

Function

PLCC-

 

PDIP-

 

MQFP-

Output

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

44

 

40

 

44

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.0-P1.7

2-9

 

1-8

 

40-44,

I/O

Port1

 

 

 

 

 

 

1-3

 

Port 1 is an 8-bit bidirectional I/O port with internal

 

 

 

 

 

 

 

pull-ups. Port 1 pins that have 1s written to them are

 

 

 

 

 

 

 

pulled high by the internal pull-up resistors and can be

 

 

 

 

 

 

 

used as inputs. As inputs, port 1 pins that are

 

 

 

 

 

 

 

externally pulled low will source current because of

 

 

 

 

 

 

 

the pulls-ups (IIL, in the DC characteristics). Pins P1.0

 

 

 

 

 

 

 

and P1.1 also. Port1 also receives the low-order

 

 

 

 

 

 

 

address byte during program memory verification.

 

 

 

 

 

 

 

Port1 also serves alternate functions of Timer 2.

 

2

 

1

 

40

 

P1.0 / T2 :Timer/counter 2 external count input

 

3

 

2

 

41

 

P1.1 / T2EX :Timer/counter 2 trigger input

 

 

 

 

 

 

 

In GMS90X52C/54C:

 

2

 

1

 

40

 

P1.0 / T2, Clock Out : Timer/counter 2 external count

 

 

 

 

 

 

 

input, Clock Out

 

 

 

 

 

 

 

 

 

P3.0-P3.7

11,

 

10-17

 

5, 7-13

I/O

Port 3

 

 

13-19

 

 

 

 

 

Port 3 is an 8-bit bidirectional I/O port with internal

 

 

 

 

 

 

 

pull-ups. Port 3 pins that have 1s written to them are

 

 

 

 

 

 

 

pulled high by the internal pull-up resistors and can be

 

 

 

 

 

 

 

used as inputs. As inputs, port 3 pins that are

 

 

 

 

 

 

 

externally pulled low will source current because of

 

 

 

 

 

 

 

the pulls-ups (IIL, in the DC characteristics). Port 3 also

 

 

 

 

 

 

 

serves the special features of the 80C51 family, as

 

 

 

 

 

 

 

listed below.

 

 

11

 

10

 

5

 

P3.0 / RxD

receiver data input (asynchronous) or

 

 

 

 

 

 

 

 

 

 

 

 

 

data input output(synchronous) of serial

 

 

 

 

 

 

 

 

 

 

 

 

 

interface 0

 

13

 

11

 

7

 

P3.1 / TxD

transmitter data output (asynchronous)

 

 

 

 

 

 

 

 

 

 

 

 

 

or clock output (synchronous) of the

 

 

 

 

 

 

 

 

 

 

 

 

 

serial interface 0

 

14

 

12

 

8

 

P3.2 /

INT0

 

interrupt 0 input/timer 0 gate control

 

15

 

13

 

9

 

P3.3 / INT1

interrupt 1 input/timer 1 gate control

 

16

 

14

 

10

 

P3.4 /T0

counter 0 input

 

17

 

15

 

11

 

P3.5 /T1

counter 1 input

 

18

 

16

 

12

 

P3.6 /

WR

 

the write control signal latches the data

 

 

 

 

 

 

 

 

 

 

 

 

 

byte from port 0 into the external data

 

 

 

 

 

 

 

 

 

 

 

 

 

memory

 

19

 

17

 

13

 

P3.7

/RD

 

the read control signal enables the

 

 

 

 

 

 

 

 

 

 

 

 

 

external data memory to port 0

 

 

 

 

 

 

 

 

 

XTAL2

20

 

18

 

14

O

XTAL2

 

 

 

 

 

 

 

 

Output of the inverting oscillator amplifier.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

Jan. 2001 Ver 1.0

GMS90X5XC Series

 

 

 

HYUNDAI MicroElectronics

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Number

 

Input/

 

 

 

Symbol

 

 

 

 

 

 

Function

PLCC-

 

PDIP-

 

MQFP-

Output

 

 

 

 

 

 

 

 

 

 

 

 

44

 

40

 

44

 

 

 

 

 

 

 

 

 

 

 

 

XTAL1

21

 

19

 

15

I

XTAL1

 

 

 

 

 

 

 

 

 

Input to the inverting oscillator amplifier and input to

 

 

 

 

 

 

 

 

 

the internal clock generator circuits.To drive the

 

 

 

 

 

 

 

 

 

device from an external clock source, XTAL1 should

 

 

 

 

 

 

 

 

 

be driven, while XTAL2 is left unconnected. There are

 

 

 

 

 

 

 

 

 

no requirements on the duty cycle of the external

 

 

 

 

 

 

 

 

 

clock signal, since the input to the internal clocking

 

 

 

 

 

 

 

 

 

circuitry is divided down by a divide-by-two flip-flop.

 

 

 

 

 

 

 

 

 

Minimum and maximum high and low times as well as

 

 

 

 

 

 

 

 

 

rise fall times specified in the AC characteristics must

 

 

 

 

 

 

 

 

 

be observed.

 

 

 

 

 

 

 

 

P2.0-P2.7

24-31

 

21-28

 

18-25

I/O

Port 2

 

 

 

 

 

 

 

 

 

Port 2 is an 8-bit bidirectional I/O port with internal

 

 

 

 

 

 

 

 

 

pull-ups. Port 2 pins that have 1s written to them are

 

 

 

 

 

 

 

 

 

pulled high by the internal pull-up resistors and can be

 

 

 

 

 

 

 

 

 

used as inputs. As inputs, port 2 pins that are

 

 

 

 

 

 

 

 

 

externally pulled low will source current because of

 

 

 

 

 

 

 

 

 

the pulls-ups (IIL, in the DC characteristics).Port 2

 

 

 

 

 

 

 

 

 

emits the high-order address byte during fetches from

 

 

 

 

 

 

 

 

 

external program memory and during accesses to

 

 

 

 

 

 

 

 

 

external data memory that use 16-bit addresses

 

 

 

 

 

 

 

 

 

(MOVX @DPTR). In this application it uses strong

 

 

 

 

 

 

 

 

 

internal pull-ups when emitting 1s. During accesses to

 

 

 

 

 

 

 

 

 

external data memory that use 8-bit addresses

 

 

 

 

 

 

 

 

 

(MOVX @Ri), port 2 emits the contents of the P2

 

 

 

 

 

 

 

 

 

special function register.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PSEN

 

32

 

29

 

26

O

The Program Store Enable

 

 

 

 

 

 

 

 

 

The read strobe to external program memory when

 

 

 

 

 

 

 

 

 

the device is executing code from the external

 

 

 

 

 

 

 

 

 

program memory. PSEN is activated twice each

 

 

 

 

 

 

 

 

 

machine cycle, except that two PSEN activations are

 

 

 

 

 

 

 

 

 

skipped during each access to external data memory.

 

 

 

 

 

 

 

 

 

PSEN is not activated during fetches from internal

 

 

 

 

 

 

 

 

 

program memory.

 

 

 

 

 

 

 

 

RESET

10

 

9

 

4

I

RESET

 

 

 

 

 

 

 

 

 

A high level on this pin for two machine cycles while

 

 

 

 

 

 

 

 

 

the oscillator is running resets the device. An internal

 

 

 

 

 

 

 

 

 

diffused resistor to VSS permits power-on reset using

 

 

 

 

 

 

 

 

 

only an external capacitor to VCC.

Jan. 2001 Ver 1.0

7

HYUNDAI MicroElectronics

 

 

 

GMS90X5XC Series

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Number

 

Input/

 

 

 

 

 

Symbol

 

 

 

 

 

 

Function

 

PLCC-

 

PDIP-

 

MQFP-

Output

 

 

 

 

 

 

 

 

 

 

 

 

 

44

 

40

 

44

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The Address Latch Enable /

 

 

 

ALE /

33

 

30

 

27

O

Program pulse

 

 

PROG

 

 

 

 

 

 

Output pulse for latching the low byte of the address

 

 

 

 

 

 

 

 

 

during an access to external memory. In normal

 

 

 

 

 

 

 

 

 

operation, ALE is emitted at a constant rate of 1/6 the

 

 

 

 

 

 

 

 

 

oscillator frequency, and can be used for external

 

 

 

 

 

 

 

 

 

timing or clocking. Note that one ALE pulse is skipped

 

 

 

 

 

 

 

 

 

during each access to external data memory. This pin

 

 

 

 

 

 

 

 

 

is also the program pulse input (PROG) during

 

 

 

 

 

 

 

 

 

EPROM programming.

 

 

 

 

 

 

 

 

 

If desired, ALE operation can be disabled by setting

 

 

 

 

 

 

 

 

 

bit 0 of SFR location 8EH. With this bit set, the pin is

 

 

 

 

 

 

 

 

 

weakly pulled high. The ALE disable feature will be

 

 

 

 

 

 

 

 

 

terminated by reset. Setting the ALE-disable bit has

 

 

 

 

 

 

 

 

 

no affect if the microcontroller is in external execution

 

 

 

 

 

 

 

 

 

mode.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

/ VPP

35

 

31

 

29

I

External Access Enable / Program Supply Voltage

 

EA

 

 

 

 

 

 

 

 

 

 

 

EA must be external held low to enable the device to

 

 

 

 

 

 

 

 

 

fetch code from external program memory locations

 

 

 

 

 

 

 

 

 

0000H to FFFFH. If EA is held high, the device

 

 

 

 

 

 

 

 

 

executes from internal program memory unless the

 

 

 

 

 

 

 

 

 

program counter contains an address greater than its

 

 

 

 

 

 

 

 

 

internal memory size. This pin also receives the

 

 

 

 

 

 

 

 

 

12.75V programming supply voltage (VPP) during

 

 

 

 

 

 

 

 

 

EPROM programming.

 

 

 

 

 

 

 

 

 

Note;

however, that if any of the Lock bits are

 

 

 

 

 

 

 

 

 

 

programmed, EA will be internally

 

 

 

 

 

 

 

 

 

 

latched on reset.

 

 

 

 

 

 

 

 

 

 

 

P0.0-P0.7

36-43

 

32-39

 

30-37

I/O

Port 0

 

 

 

 

 

 

 

 

 

 

 

 

Port 0 is an 8-bit open-drain bidirectional I/O port.

 

 

 

 

 

 

 

 

 

Port 0 pins that have 1s written to them float and can

 

 

 

 

 

 

 

 

 

be used as high-impedance inputs.

 

 

 

 

 

 

 

 

 

Port 0 is also the multiplexed low-order address and

 

 

 

 

 

 

 

 

 

data bus during accesses to external program and

 

 

 

 

 

 

 

 

 

data memory. In this application it uses strong internal

 

 

 

 

 

 

 

 

 

pull-ups when emitting 1s. Port 0 also outputs the

 

 

 

 

 

 

 

 

 

code bytes during program verification in the

 

 

 

 

 

 

 

 

 

GMS97X5X. External pull-up resistors are required

 

 

 

 

 

 

 

 

 

during program verification.

 

 

 

 

 

 

 

 

 

 

VSS

22

 

20

 

16

-

Circuit ground potential

 

 

 

 

 

 

 

 

 

 

VCC

44

 

40

 

38

-

Supply terminal for all operating modes

 

N.C.

1,12

 

-

 

6,17

-

No connection

 

 

 

23,34

 

 

 

28,39

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

Jan. 2001 Ver 1.0

GMS90X5XC Series

HYUNDAI MicroElectronics

FUNCTIONAL DESCRIPTION

The GMS90X5XC series is fully compatible to the standard 8051 microcontroller family.

It is compatible with the general 8051 family. While maintaining all architectural and operational characteristics of the general 8051 family.

Figure 1 shows a block diagram of the GMS90X5XC series

 

XTAL1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RAM

 

 

 

ROM/EPROM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XTAL2

 

 

 

 

 

OSC & TIMING

 

 

 

 

128/256×8

 

 

 

 

 

4K/8K/16K

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RESET

 

 

 

 

 

 

 

 

 

CPU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EA/VPP

 

 

 

 

 

 

 

 

Timer 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Port 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Port 0

 

 

 

 

 

 

 

 

ALE/PROG

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8-bit Digit. I/O

 

 

PSEN

 

 

 

 

 

 

 

 

 

 

 

Timer 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Port 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Port 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8-bit Digit. I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Timer 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Port 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Port 2

 

 

 

 

8-bit Digit. I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

Interrupt Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Port 3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Port 3

 

 

 

 

8-bit Digit. I/O

 

 

 

 

 

 

 

 

 

 

 

 

Serial Channel

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 1. Block Diagram of the GMS90X5XC series

Jan. 2001 Ver 1.0

9

HYUNDAI MicroElectronics

GMS90X5XC Series

CPU

The GMS90X5XC series is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 1.0μs (40MHz: 300ns).

Special Function Register PSW

 

MSB

 

 

 

 

 

 

LSB

 

Bit No.

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

Addr. D0H

CY

AC

F0

RS1

RS0

OV

F1

P

PSW

 

 

 

 

 

 

 

 

 

 

Bit

 

Function

 

 

 

CY

 

Carry Flag

 

 

 

AC

 

Auxiliary Carry Flag (for BCD operations)

 

 

 

F0

 

General Purpose Flag

 

 

 

RS1

RS0

Register Bank select control bits

0

0

Bank 0 selected, data address 00H - 07H

0

1

Bank 1 selected, data address 08H - 0FH

1

0

Bank 2 selected, data address 10H - 17H

1

1

Bank 3 selected, data address 18H - 1FH

OV

 

Overflow Flag

 

 

 

F1

 

General Purpose Flag

 

 

 

P

 

Parity Flag

 

 

Set/cleared by hardware each instruction cycle to indicate an odd/even

 

 

number of "one" bits in the accumulator, i.e. even parity.

 

 

 

Reset value of PSW is 00H.

10

Jan. 2001 Ver 1.0

GMS90X5XC Series

HYUNDAI MicroElectronics

SPECIAL FUNCTION REGISTERS

All registers, except the program counter and the four general purpose register banks, reside in the special function register area.

The 28 special function registers (SFR) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. There are also 128 directly addressable bits within the SFR area.

All SFRs are listed in Table 1, Table 2, and Table 3.

In Table 1 they are organized in numeric order of their addresses. In Table 2 they are organized in groups which refer to the functional blocks of the GMS90X5XC series. Table 3 illustrates the contents of the SFRs

Table 1. Special Function Registers in Numeric Order of their Addresses (cont’d)

Address

Register

Contents after

 

Address

Register

Contents after

Reset

 

Reset

 

 

 

 

 

 

 

 

 

 

 

 

80H

P0 1)

FFH

 

88H

TCON 1)

00H

81H

SP

07H

 

89H

TMOD

00H

82H

DPL

00H

 

8AH

TL0

00H

83H

DPH

00H

 

8BH

TL1

00H

84H

reserved

XXH 2)

 

8CH

TH0

00H

85H

reserved

XXH 2)

 

8DH

TH1

00H

86H

reserved

XXH 2)

 

8EH

AUXR0

XXH 2)

87H

PCON

0XXX0000B 2)

 

8FH

CKCON

XXXXXXX0B 2)

90H

P1 1)

FFH

 

98H

SCON 1)

00H

91H

reserved

00H

 

99H

SBUF

XXH 2)

92H

reserved

XXH 2)

 

9AH

reserved

XXH 2)

93H

reserved

XXH 2)

 

9BH

reserved

XXH 2)

94H

reserved

XXH 2)

 

9CH

reserved

XXH 2)

95H

reserved

XXH 2)

 

9DH

reserved

XXH 2)

96H

reserved

XXH 2)

 

9EH

reserved

XXH 2)

97H

reserved

XXH 2)

 

9FH

reserved

XXH 2)

A0H

P2 3)

FFH

 

A8H

IE 1)

0X000000B 2)

A1H

reserved

XXH 2)

 

A9H

reserved

XXH 2)

A2H

reserved

XXH 2)

 

AAH

reserved

XXH 2)

A3H

reserved

XXH 2)

 

ABH

reserved

XXH 2)

A4H

reserved

XXH 2)

 

ACH

reserved

XXH 2)

A5H

reserved

XXH 2)

 

ADH

reserved

XXH 2)

A6H

reserved

XXH 2)

 

AEH

reserved

XXH 2)

A7H

reserved

XXH 2)

 

AFH

reserved

XXH 2)

B0H

P3 1)

FFH

 

B8H

IP 1)

XX000000B 2)

B1H

reserved

XXH 2)

 

B9H

reserved

XXH 2)

B2H

reserved

XXH 2)

 

BAH

reserved

XXH 2)

B3H

reserved

XXH 2)

 

BBH

reserved

XXH 2)

B4H

reserved

XXH 2)

 

BCH

reserved

XXH 2)

B5H

reserved

XXH 2)

 

BDH

reserved

XXH 2)

B6H

reserved

XXH 2)

 

BEH

reserved

XXH 2)

B7H

reserved

XXH 2)

 

BFH

reserved

XXH 2)

Jan. 2001 Ver 1.0

11

HYUNDAI MicroElectronics

GMS90X5XC Series

Table 1. Special Function Registers in Numeric Order of their Addresses (cont’d)

Address

Register

Contents after

 

Address

Register

Contents after

Reset

 

Reset

 

 

 

 

 

 

 

 

 

 

 

 

C0H

reserved

XX

 

C8H 3)

T2CON 1)

00H

 

H

 

 

 

 

C1H

reserved

XXH 2)

 

C9H 4)

T2MOD

XXXXXX00B 2)

C2H

reserved

XXH 2)

 

CAH 3)

RC2L

00H

C3H

reserved

XXH 2)

 

CBH 3)

RC2H

00H

C4H

reserved

XXH 2)

 

CCH 3)

TL2

00H

C5H

reserved

XXH 2)

 

CDH 3)

TH2

00H

C6H

reserved

XXH 2)

 

CEH

reserved

XXH 2)

C7H

reserved

XXH 2)

 

CFH

reserved

XXH 2)

D0H

PSW 1)

FFH

 

D8H

reserved

XXH 2)

D1H

reserved

XXH 2)

 

D9H

reserved

XXH 2)

D2H

reserved

XXH 2)

 

DAH

reserved

XXH 2)

D3H

reserved

XXH 2)

 

DBH

reserved

XXH 2)

D4H

reserved

XXH 2)

 

DCH

reserved

XXH 2)

D5H

reserved

XXH 2)

 

DDH

reserved

XXH 2)

D6H

reserved

XXH 2)

 

DEH

reserved

XXH 2)

D7H

reserved

XXH 2)

 

DFH

reserved

XXH 2)

E0H

ACC 1)

00H

 

E8H

reserved

XXH 2)

E1H

reserved

XXH 2)

 

E9H

reserved

XXH 2)

E2H

reserved

XXH 2)

 

EAH

reserved

XXH 2)

E3H

reserved

XXH 2)

 

EBH

reserved

XXH 2)

E4H

reserved

XXH 2)

 

ECH

reserved

XXH 2)

E5H

reserved

XXH 2)

 

EDH

reserved

XXH 2)

E6H

reserved

XXH 2)

 

EEH

reserved

XXH 2)

E7H

reserved

XXH 2)

 

EFH

reserved

XXH 2)

F0H

B 1)

00H

 

F8H

reserved

XXH 2)

F1H

reserved

XXH 2)

 

F9H

reserved

XXH 2)

F2H

reserved

XXH 2)

 

FAH

reserved

XXH 2)

F3H

reserved

XXH 2)

 

FBH

reserved

XXH 2)

F4H

reserved

XXH 2)

 

FCH

reserved

XXH 2)

F5H

reserved

XXH 2)

 

FDH

reserved

XXH 2)

F6H

reserved

XXH 2)

 

FEH

reserved

XXH 2)

F7H

reserved

XXH 2)

 

FFH

reserved

XXH 2)

1)Bit-addressable Special Function Register.

2)X means that the value is indeterminate and the location is reserved.

3)Bit-addressable Special Function Register.

4)These Registers are in the GMS90X52C/54C only.

12

Jan. 2001 Ver 1.0

GMS90X5XC Series

HYUNDAI MicroElectronics

Table 2. Special Function Registers - Functional Blocks

Block

Symbol

Name

Address

Contents

after Reset

 

 

 

 

 

 

 

 

 

CPU

ACC

Accumulator

E0H 1)

00H

 

B

B-Register

F0H 1)

00H

 

DPH

Data Pointer, High Byte

83H

00H

 

DPL

Data Pointer, Low Byte

82H

00H

 

PSW

Program Status Word Register

D0H 1)

00H

 

SP

Stack Pointer

81H

07H

 

 

 

 

 

Interrupt System

IE

Interrupt Enable Register

A8H 1)

0X000000B 2)

 

IP

Interrupt Priority Register

B8H 1)

XX000000B 2)

Ports

P0

Port 0

80H 1)

FFH

 

P1

Port 1

90H 1)

FFH

 

P2

Port 2

A0H 1)

FFH

 

P3

Port 3

B0H 1)

FFH

Serial Channels

PCON 3)

Power Control Register

87H

0XXX0000B 2)

 

SBUF

Serial Channel Buffer Reg.

99H

XXH 2)

 

SCON

Serial Channel 0 Control Reg.

98H 1)

00H

Timer 0/ Timer 1

TCON

Timer 0/1 Control Register

88H 1)

00H

 

TH0

Timer 0, High Byte

8CH

00H

 

TH1

Timer 1, High Byte

8DH

00H

 

TL0

Timer 0, Low Byte

8AH

00H

 

TL1

Timer 1, Low Byte

8BH

00H

 

TMOD

Timer Mode Register

89H

00H

 

 

 

 

 

Timer 2

T2CON

Timer 2 Control Register

C8H 1)

00H

 

T2MOD

Timer 2 Mode Register

C9H

00H

 

RC2H

Timer 2 Reload Capture Reg., High Byte

CBH

00H

 

RC2L

Timer 2 Reload Capture Reg., Low Byte

CAH

00H

 

TH2

Timer 2, High Byte

CDH

00H

 

TL2

Timer 2, Low Byte

CCH

00H

 

AUXR0

Aux. Register 0

8EH

XXXXXXX0B 2)

Power Saving

PCON 3)

Power Control Register

87H

0XXX0000B 2)

Modes

 

 

 

 

 

 

 

 

 

1)Bit-addressable Special Function register

2)X means that the value is indeterminate and the location is reserved

3)This special function register is listed repeatedly since some bit of it also belong to other functional blocks

Table 3. Contents of SFRs, SFRs in Numeric Order

Address Register

80H P0

Bit 7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Jan. 2001 Ver 1.0

13

HYUNDAI MicroElectronics

GMS90X5XC Series

Table 3. Contents of SFRs, SFRs in Numeric Order

Address Register

Bit 7

6

5

4

3

2

1

0

81H

SP

 

 

 

 

 

 

 

 

 

 

 

 

82H

DPL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

83H

DPH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

87H

PCON

SM O D

-

 

 

-

-

GF1

GF0

PDE

IDLE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

88H

TCON

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

89H

TMOD

GATE

C/T

 

M1

MT

GATE

C/T

M1

M0

8AH

TL0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8BH

TL1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8CH

TH0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8DH

TH1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8EH

AUXR0

-

-

 

 

-

-

-

-

 

 

-

A0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8FH

CKCON

-

-

 

 

-

-

-

-

 

 

-

X2

90H

P1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

98H

SCON

SM0

SM1

SM2

REN

TB8

RB8

TI

RI

99H

SBUF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A0H

P2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A8H

IE

EA

-

 

 

ET2

ES

ET1

EX1

ET0

EX0

B0H

P3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B8H

IP

-

-

 

 

PT2

PS

PT1

PX1

PT0

PX0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SFR bit and byte addressable

SFR not bit addressable - : this bit location is reserved

14

Jan. 2001 Ver 1.0

GMS90X5XC Series

HYUNDAI MicroElectronics

Table 3. Contents of SFRs, SFRs in Numeric Order (cont’d)

Address Register

Bit 7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C8H

T2CON

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2

CP/RL2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C9H

T2MOD

-

-

-

-

-

-

T2OE

DCEN

CAH

RC2L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CBH

RC2H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CCH

TL2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CDH

TH2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D0H

PSW

CY

AC

F0

RS1

RS0

OV

F1

P

E0H

ACC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

F0H

B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

† indicates resident in the GMS90X52C/54C, not in 90X51C.

8EH

 

 

 

 

 

 

 

A0

 

 

 

 

 

 

 

 

 

A0 : ALE Signal Disable bit

0 : Enable ALE Signal (Generated ALE Signal)

1 : Disable ALE Signal (Not Generated ALE Signal)

8FH

 

 

 

 

 

 

 

X2

 

 

 

 

 

 

 

 

 

X2 : CPU & Peripheral Clock Select bit

0 : Select 12 clock periods per machine cycle

1 : Select 6 clock periods per machine cycle

C9H

T2OE

T2OE : Timer2 Output Enable bit 0 : Disable Timer2 Output

1 : Enable Timer2 Output

SFR bit and byte addressable

SFR not bit addressable

- : this bit location is reserved

Jan. 2001 Ver 1.0

15

HYUNDAI MicroElectronics

GMS90X5XC Series

X2 MODE

The GMS90X5XC core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following advantages:

Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.

Save power consumption while keeping same CPU power (oscillator power saving).

Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes.

Increase CPU power by 2 while keeping same crystal frequency.

In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by software.

X2 Mode Description

The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 2. shows the clock generation block diagram. X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode. Figure 3.shows the mode switching waveforms:

 

 

 

 

 

 

 

 

 

 

 

XTAL1

fOSC

 

 

 

÷ 2

 

0

 

State Machine: 6 clokc cyles

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

CPU control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X2

CKCON Register

Figure 2. Clock Generation Diagram

The X2 bit in the CKCON register allows to switch from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature(X2 mode).

CAUTION

In order to prevent any incorrect operation while operating in X2 mode, user must be aware that all peripherals using clock frequency as time reference (UART, timers) will have their time reference divided by two. For example a free running timer generating an interrupt every 30 ms will then generate an interrupt every 15 ms. UART with 2400 baud rate will have 4800 baud rate.

16

Jan. 2001 Ver 1.0

GMS90X5XC Series

HYUNDAI MicroElectronics

XTAL1

 

 

XTAL1:2

 

 

X2 bit

 

 

CPU Clock

 

 

STD Mode

X2 Mode

STD Mode

Figure 3. Mode Swithcing Waveforms

.

Jan. 2001 Ver 1.0

17

HYUNDAI MicroElectronics

GMS90X5XC Series

TIMER / COUNTER 0 AND 1

Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 4:

Table 4. Timer/Counter 0 and 1 Operating Modes

Mode

Description

 

 

TMOD

 

Input Clock

 

 

 

 

 

 

 

 

 

 

Gate

C/T

 

M1

M0

internal

external (Max.)

 

 

 

 

 

 

 

 

 

0

8-bit timer/counter with a

X

X

 

0

0

fOSC ÷(12×32)

fOSC ÷(24×32)

 

divide-by-32 prescaler

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

16-bit timer/counter

X

X

 

0

1

fOSC ÷12

fOSC ÷24

2

8-bit timer/counter with

X

X

 

1

0

fOSC ÷12

fOSC ÷24

 

8-bit auto-reload

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

Timer/counter 0 used as

X

X

 

1

1

fOSC ÷12

fOSC ÷24

 

one 8-bit timer/counter and

 

 

 

 

 

 

 

 

 

one 8-bit timer Timer 1

 

 

 

 

 

 

 

 

 

stops

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

In the "timer" function (C/T = "0") the register is incremented every machine cycle. Therefore the count rate is fOSC/12.

In the "counter" function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is fOSC/24. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements. Figure 4 illustrates the input clock logic.

 

fOSC

 

 

 

¸ 12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

fOSC ¸ 12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C/T

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TMOD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P3.4/T0

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Timer 0/1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P3.5/T1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input Clock

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Max. fOSC/24

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TR0 / 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCON

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

&

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Gate

 

 

=1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TMOD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

³1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P3.2 /

INT0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P3.3 / INT1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 4. Timer/Counter 0 and 1 Input Clock Logic

18

Jan. 2001 Ver 1.0

GMS90X5XC Series

HYUNDAI MicroElectronics

TIMER 2

Timer 2 is a 16-bit timer/Counter with an up/down count feature. It can operate either as timer or as an event

counter which is selected by bit C/T2 (T2CON.1). It has three operating modes as shown in Table 5.

Table 5. Timer/Counter 2 Operating Modes

Mode

 

 

T2CON

 

 

T2MOD

T2CON

P1.1/

Remarks

Input Clock

 

RCLK or

 

 

 

 

 

 

T2EX

 

external

 

 

 

CP/RL2

 

TR2

DCEN

EXEN2

 

internal

 

 

 

TCLK

 

 

 

 

 

 

 

 

 

(P1.0/T2)

16-bit Auto-

 

0

0

 

1

0

0

X

reload upon over-

fOSC ÷ 12

Max.

Reload

 

0

0

 

1

0

1

flow

 

fOSC ÷24

 

 

 

 

reload trigger (fall-

 

 

 

 

 

 

 

 

 

 

 

 

 

ing edge)

 

 

 

 

 

0

0

 

1

1

X

0

Down counting

 

 

 

 

 

0

0

 

1

1

X

1

Up counting

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16-bit

 

0

1

 

1

X

0

X

16 bit Timer/ Coun-

fOSC ÷ 12

Max.

Capture

 

 

 

 

 

 

 

 

 

ter (only up-count-

 

fOSC ÷ 24

 

 

 

 

 

 

 

 

 

 

ing)

 

 

 

 

 

0

1

 

1

X

1

capture TH2,TL2

 

 

 

 

 

 

 

 

 

 

 

 

 

RC2H,RC2L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Baud Rate

 

1

X

 

1

X

0

X

no overflow

fOSC ÷ 12

Max.

Generator

 

 

 

 

 

 

 

 

 

interrupt request

 

fOSC ÷ 24

 

 

 

 

 

 

 

 

 

 

(TF2)

 

 

 

 

 

1

X

 

1

X

1

extra external inter-

 

 

 

 

 

 

 

 

 

 

 

 

 

rupt ("Timer 2")

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Off

 

X

X

 

0

X

X

X

Timer 2 stops

-

-

 

 

 

 

 

 

 

 

 

 

 

 

 

Note: =

 

falling edge

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Jan. 2001 Ver 1.0

19

HYUNDAI MicroElectronics

GMS90X5XC Series

SERIAL INTERFACE (USART)

The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in Table 6. The possible baud rates can be calculated using the formulas given in Table 7.

Table 6. USART Operating Modes

Mode

SCON

Baudrate

Description

 

 

SM0

SM1

 

 

 

 

0

0

0

fOSC

Serial data enters and exits through RxD.

------------

 

 

 

12

 

TxD outputs the shift clock. 8-bit are transmit-

 

 

 

 

 

 

 

 

 

 

ted/received (LSB first)

 

 

 

 

 

1

0

1

Timer 1/2 overflow rate

8-bit UART

 

 

 

 

 

10 bits are transmitted (through TxD) or

 

 

 

fOSC

fOSC

received (RxD)

2

1

0

9-bit UART

------------ or

------------

 

 

 

32

64

11 bits are transmitted (TxD) or received (RxD)

 

 

 

 

 

 

 

 

 

 

3

1

1

Timer 1/2 overflow rate

9-bit UART

 

 

 

 

 

Like mode 2 except the variable baud rate

 

 

 

 

 

 

Table 7. Formulas for Calculating Baud rates

Baud Rate

Interface Mode

 

 

Baudrate

derived from

 

 

 

 

 

 

 

Oscillator

0

 

 

fOSC

 

 

----12--------

 

 

 

 

 

2

2SMOD

× fOSC

 

2SMOD--

-----

64----------

 

 

 

 

Timer 1 (16-bit timer)

1,3

-----------------

× (Timer 1 overflow)

(8-bit timer with

1,3

2SMOD32

×

 

fOSC

8-bit auto reload)

-------32----------

---------------12 × [-256----------------(--TH1-------------)---]

Timer 2

1,3

 

 

fOSC

-------------------------------------------32 × [65536 (RC2H----------------,---RC2L----------------)---]

 

 

20

Jan. 2001 Ver 1.0

GMS90X5XC Series

HYUNDAI MicroElectronics

INTERRUPT SYSTEM

The GMS90X5XC series provides 5 (4K bytes ROM version) or 6 (above 8K bytes ROM version) interrupt sources with two priority levels. Figure 5 gives a general overview of the interrupt sources and illustrates the request and control flags.

 

 

 

 

 

High

 

 

 

 

 

Priority

Timer 0 Overflow

TF0

 

 

 

 

 

TCON.5

 

 

Low

 

 

 

 

Priority

 

 

ET0

 

PT0

 

 

 

 

 

 

IE.1

 

IP.1

 

Timer 1 Overflow

TF1

 

 

 

 

 

TCON.7

 

 

 

 

 

ET1

 

PT1

 

 

 

IE.3

 

IP.3

 

Timer 2 Overflow

TF2

³1

 

 

 

 

T2CON.7

 

 

 

 

 

 

 

 

P1.1/

EXF2

ET2

 

PT2

 

T2EX

 

 

T2CON.6

 

 

 

 

EXEN2

IE.5

 

IP.5

 

 

 

 

 

 

T2CON.3

RI

³1

 

 

 

 

SCON.0

 

 

 

UART

 

 

 

 

 

TI

ES

 

PS

 

 

 

 

 

 

SCON.1

IE.4

 

IP.4

 

 

 

 

 

P3.2/

 

IE0

 

 

 

INT0

 

 

 

 

 

TCON.1

 

 

 

 

 

 

 

 

IT0

 

EX0

 

PX0

 

TCON.0

 

IE.0

 

IP.0

 

P3.3/

 

IE1

 

 

 

INT1

 

 

 

 

 

TCON.3

 

 

 

 

 

EA

 

 

IT1

 

EX1

PX1

 

TCON.2

 

IE.2

IE.7

IP.2

 

: Low level triggered

 

 

 

 

: Falling edge triggered

 

 

 

 

Figure 5. Interrupt Request Sources

Jan. 2001 Ver 1.0

21

HYUNDAI MicroElectronics

GMS90X5XC Series

Table 8. Interrupt Sources and their Corresponding Interrupt Vectors

Source (Request Flags)

Vectors

Vector Address

 

 

 

RESET

RESET

0000H

IE0

External interrupt 0

0003H

TF0

Timer 0 interrupt

000BH

IE1

External interrupt 1

0013H

TF1

Timer 1 interrupt

001BH

RI + TI

Serial port interrupt

0023H

TF2 + EXF2

Timer 2 interrupt

002BH

 

 

 

A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source.

If two requests of different priority level are received simultaneously, the request of higher priority is serviced. If requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence as shown in Table 9.

Table 9. Interrupt Priority-Within-Level

Interrupt Source

Priority

 

 

 

External Interrupt 0

IE0

High

Timer 0 Interrupt

TF0

External Interrupt 1

IE1

Timer 1 Interrupt

TF1

Serial Channel

RI + TI

Timer 2 Interrupt

TF2 + EXF2

Low

 

 

 

22

Jan. 2001 Ver 1.0

GMS90X5XC Series

HYUNDAI MicroElectronics

Power Saving Modes

Two power down modes are available, the Idle Mode and Power Down Mode.

The bits PDE and IDLE of the register PCON select the Power Down mode or the Idle mode, respectively. If the Power Down mode and the Idle mode are set at the same time, the Power Down mode takes precedence. Table 10 gives a general overview of the power saving modes.

Table 10. Power Saving Modes Overview

 

Entering

 

 

Mode

Instruction

Leaving by

Remarks

 

Example

 

 

 

 

 

 

Idle mode

ORL PCON, #01H

- Enabled interrupt

CPU is gated off

 

 

- Hardware Reset

CPU status registers maintain their

 

 

 

data.

 

 

 

Peripherals are active

 

 

 

 

Power-Down mode

ORL PCON, #02H

Hardware Reset

Oscillator is stopped, contents of on-

 

 

 

chip RAM and SFR’s are maintained

 

 

 

(leaving Power Down Mode means

 

 

 

redefinition of SFR contents).

 

 

 

 

In the Power Down mode of operation, VCC can be reduced to minimize power consumption. It must be ensured, however, that VCC is not reduced before the Power Down mode is invoked, and that VCC is restored to its normal operating level, before the Power Down mode is terminated. The reset signal that terminates the Power Down mode also restarts the oscillator. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize (similar to power-on reset).

Jan. 2001 Ver 1.0

23

HYUNDAI MicroElectronics GMS90X5XC Series

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

Ambient temperature under bias (TA)......................................................................................

-40 to + 85

°C

Storage temperature (TST)......................................................................................................

-65 to + 150

°C

Voltage on VCC pins with respect to ground (VSS) .................................................................

-0.5V to 6.5V

Voltage on any pin with respect to ground (VSS) ..........................................................

-0.5V to VCC + 0.5V

Input current on any pin during overload condition............................................................

-15mA to +15mA

Absolute sum of all input currents during overload condition...........................................................

|100mA|

Power dissipation ....................................................................................................................................

1.5W

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) the Voltage on VCC pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings.

24

Jan. 2001 Ver 1.0

GMS90X5XC Series

HYUNDAI MicroElectronics

DC Characteristics

DC Characteristics for GMS90C51C/52C/54C

VCC= 5V + 10%, -15%; VSS=0V; TA= 0°C to 70°C

Parameter

Symbol

 

Limit Values

Unit

Test Conditions

 

 

 

 

Min.

Max.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input low voltage

 

 

 

 

VIL

-0.5

0.2VCC - 0.1

V

-

(except EA, RESET)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input low voltage

 

 

 

 

 

VIL1

-0.5

0.2VCC - 0.3

V

-

(EA)

 

 

Input low voltage (RESET)

VIL2

-0.5

0.2VCC + 0.1

V

-

Input high voltage (except

VIH

0.2VCC + 0.9

VCC + 0.5

V

-

XTAL1, EA, RESET)

 

 

 

 

 

 

 

 

 

 

 

 

Input high voltage to XTAL1

VIH1

0.7VCC

VCC + 0.5

V

-

Input high voltage to

 

 

 

VIH2

0.6VCC

VCC + 0.5

V

-

EA,

 

RESET

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output low voltage

 

 

 

 

VOL

-

0.45

V

IOL= 1.6mA 1)

(ports 1, 2, 3)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output low voltage

 

 

 

 

VOL1

-

0.45

V

IOL= 3.2mA 1)

(port 0, ALE, PSEN)

 

 

 

 

 

 

 

 

 

 

 

 

Output high voltage

VOH

2.4

-

V

IOH= -80μA

(ports 1, 2, 3)

 

 

 

 

 

 

0.9VCC

 

 

IOH= -10μA

Output high voltage

VOH1

2.4

-

V

IOH= -800μA 2)

(port 0 in external bus

 

 

0.9VCC

 

 

IOH= -80μA 2)

mode, ALE, PSEN)

 

 

 

 

 

 

 

 

 

 

 

 

Logic 0 input current

IIL

-10

-50

μA

VIN= 0.45V

(ports 1, 2, 3)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Logical 1-to-0 transition cur-

ITL

-65

-650

μA

VIN= 2.0V

rent (ports 1, 2, 3)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input leakage current

ILI

-

±1

μA

0.45 < VIN < VCC

(port 0, EA)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin capacitance

 

 

 

 

CIO

-

10

pF

fC= 1MHz

 

 

 

 

 

 

 

 

 

 

 

TA= 25°C

Power supply current:

 

 

 

 

 

VCC= 5V 4)

Active mode, 12MHz 3)

ICC

-

21

mA

Idle mode, 12MHz

3)

 

 

 

ICC

-

4.8

mA

V = 5V 5)

 

 

 

 

CC

Active mode, 24 MHz 3)

ICC

-

36.2

mA

VCC= 5V 4)

Idle mode, 24MHz 3)

ICC

-

8.2

mA

VCC= 5V 5)

Active mode, 40 MHz 3)

ICC

-

58.5

mA

VCC= 5V 4)

Idle mode, 40 MHz 3)

ICC

-

12.5

mA

VCC= 5V 5)

Power Down Mode 3)

IPD

-

50

VCC= 5V 6)

 

 

 

 

 

 

μA

 

1)Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3.

The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading: > 50pF at 3.3V, > 100pF at 5V), the noise pulse on ALE

line may exceed 0.8V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input.

Jan. 2001 Ver 1.0

25

HYUNDAI MicroElectronics

GMS90X5XC Series

2)Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the address lines are stabilizing.

3)ICC Max at other frequencies is given by:

active mode:

ICC = 1.27 × fOSC + 5.73

idle mode:

ICC = 0.28 × fOSC + 1.45 (except OTP devices)

where fOSC is the oscillator frequency in MHz. ICC values are given in mA and measured at VCC = 5V.

4)ICC (active mode) is measured with:

XTAL1 driven with tCLCH, tCHCL = 5ns, VIL = VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 = N.C.;

EA = Port0 = RESET = VCC; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is used (appr. 1mA).

5)ICC (Idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tCLCH, tCHCL = 5ns, VIL = VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 = N.C.; RESET = EA = VSS; Port0 = VCC; all other pins are disconnected;

6)IPD (Power Down Mode) is measured under following conditions:

EA = Port0 = VCC; RESET = VSS; XTAL2 = N.C.; XTAL1 = VSS; all other pins are disconnected.

26

Jan. 2001 Ver 1.0

GMS90X5XC Series

 

 

 

 

HYUNDAI MicroElectronics

DC Characteristics for GMS90L51C/52C/54C

 

 

 

 

VCC= 3.3V + 0.3V, -0.6V; VSS=0V; TA= 0°C to 70°C

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

Symbol

 

Limit Values

 

Unit

Test Conditions

 

 

 

 

 

Min.

Max.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input low voltage

 

VIL

-0.5

0.8

 

V

-

Input high voltage

 

VIH

2.0

VCC + 0.5

 

V

-

Output low voltage

 

VOL

-

0.45

 

V

IOL= 1.6mA 1)

(ports 1, 2, 3)

 

 

 

 

0.30

 

 

IOL= 100μA 1)

Output low voltage

 

VOL1

-

0.45

 

V

IOL= 3.2mA 1)

(port 0, ALE, PSEN)

 

 

 

0.30

 

 

IOL= 200μA 1)

Output high voltage

VOH

2.0

-

 

V

IOH= -20μA

(ports 1, 2, 3)

 

 

 

0.9VCC

 

 

 

IOH= -10μA

Output high voltage

VOH1

2.0

-

 

V

IOH= -800μA 2)

(port 0 in external bus

 

 

0.9VCC

 

 

 

IOH= -80μA 2)

mode, ALE, PSEN)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Logic 0 input current

IIL

-1

-50

 

μA

VIN= 0.45V

(ports 1, 2, 3)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Logical 1-to-0 transition cur-

ITL

-25

-250

 

μA

VIN= 2.0V

rent (ports 1, 2, 3)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input leakage current

ILI

-

±1

 

μA

0.45 < VIN < VCC

(port 0, EA)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin capacitance

 

CIO

-

10

 

pF

fC= 1MHz

 

 

 

 

 

 

 

 

TA= 25°C

Power supply current:

 

 

 

 

 

 

VCC= 3.6V 4)

Active mode, 16 MHz 3)

ICC

-

15

 

mA

Idle mode, 16MHz

3)

ICC

-

5

 

mA

V = 2.6V 5)

 

 

CC

Power Down Mode 3)

IPD

-

10

 

μA

VCC=2~ 5.5V 6)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Jan. 2001 Ver 1.0

27

HYUNDAI MicroElectronics

GMS90X5XC Series

AC Characteristics

Explanation of the AC Symbols

Each timing symbol has 5 characters. The first character is always a ‘t’ (stand for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for.

A: Address

C:Clock

D:Input Data

H:Logic level HIGH

I:Instruction (program memory contents)

L:Logic level LOW, or ALE

P:PSEN

Q:Output Data

R:RD signal

T: Time

V:Valid

W:WR signal

X:No longer a valid logic level

Z:Float

For example,

tAVLL = Time from Address Valid to ALE Low tLLPL = Time from ALE Low to PSEN Low

AC Characteristics for GMS90X5XC series (12MHz version)

VCC= 5V : VCC= 5V + 10%, 15%; VSS= 0V; TA= 0°C to 70°C

(CL for port 0. ALE and PSEN outputs = 100pF; CL for all other outputs = 80pF)

VCC= 3.3V : VCC= 3.3V + 0.3V, 0.6V; VSS= 0V; TA= 0°C to 70°C

(CL for port 0. ALE and PSEN outputs = 50pF; CL for all other outputs = 50pF)

Variable clock : Vcc = 5V : 1/tCLCL = 3.5 MHz to 12 MHz

Vcc = 3.3V : 1/tCLCL = 1 MHz to 12 MHz

External Program Memory Characteristics

 

 

 

 

 

 

 

 

 

 

 

 

 

12 MHz Oscillator

Variable Oscillator

 

 

 

 

Parameter

Symbol

1/tCLCL = 3.5 to 12MHz

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Min.

Max.

Min.

Max.

 

 

 

 

 

 

 

 

 

 

ALE pulse width

tLHLL

127

-

2tCLCL-40

-

ns

 

Address setup to ALE

tAVLL

43

-

tCLCL-40

-

ns

 

Address hold after ALE

tLLAX

30

-

tCLCL-53

-

ns

 

 

 

 

 

 

 

 

 

ALE low to valid instruction in

tLLIV

-

233

-

4tCLCL-100

ns

 

ALE to

 

 

 

 

 

 

 

 

 

tLLPL

58

-

tCLCL-25

-

ns

 

PSEN

 

 

 

 

 

 

 

 

 

 

pulse width

tPLPH

215

-

3tCLCL-35

-

ns

 

PSEN

 

 

to valid instruction in

tPLIV

-

150

-

3tCLCL-100

ns

 

PSEN

 

Input instruction hold after

 

 

tPXIX

0

-

0

-

ns

 

PSEN

 

 

Input instruction float after

 

 

 

tPXIZ

-

63

-

tCLCL-20

ns

 

PSEN

 

 

Address valid after

 

 

 

 

 

 

tPXAV

75

-

tCLCL-8

-

ns

 

PSEN

 

 

Address to valid instruction in

tAVIV

-

302

-

5tCLCL-115

ns

 

Address float to

 

 

 

 

 

 

 

tAZPL

0

-

0

-

ns

 

PSEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

28

Jan. 2001 Ver 1.0

GMS90X5XC Series

HYUNDAI MicroElectronics

Interfacing the GMS90X5XC series to devices with float times up to 75 ns is permissible. This limited bus contention will not

cause

any damage to port 0 Drivers.

Jan. 2001 Ver 1.0

29

HYUNDAI MicroElectronics

 

 

 

 

 

 

 

GMS90X5XC Series

AC Characteristics for GMS90X5XC series (12MHz)

 

 

 

 

 

 

 

External Data Memory Characteristics

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12 MHz Oscillator

 

Variable Oscillator

 

 

 

 

 

 

 

 

 

Parameter

 

Symbol

1/tCLCL = 3.5 to 12MHz

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Min.

Max.

 

Min.

 

Max.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

pulse width

 

tRLRH

400

-

6tCLCL-100

 

-

 

ns

 

RD

 

 

 

 

 

 

 

 

 

pulse width

 

tWLWH

400

-

6tCLCL-100

 

-

 

ns

 

WR

 

 

 

 

 

Address hold after ALE

 

tLLAX2

53

-

tCLCL-30

 

-

 

ns

 

 

 

to valid data in

 

tRLDV

-

252

-

 

5tCLCL-165

ns

 

RD

 

 

 

Data hold after

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tRHDX

0

-

0

 

-

 

ns

 

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data float after

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tRHDZ

-

97

-

 

2tCLCL-70

ns

 

RD

 

 

 

 

 

 

 

 

 

 

 

ALE to valid data in

 

tLLDV

-

517

-

 

8tCLCL-150

ns

 

Address to valid data in

 

tAVDV

-

585

-

 

9tCLCL-165

ns

 

ALE to

 

 

 

or

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tLLWL

200

300

3tCLCL-50

 

3tCLCL+50

ns

 

WR

RD

 

 

 

 

 

 

 

 

 

 

 

 

Address valid to

 

 

 

 

 

 

 

or

 

 

 

tAVWL

203

-

4tCLCL-130

 

-

 

ns

 

WR

RD

 

 

 

 

 

 

 

 

 

or

 

high to ALE high

 

tWHLH

43

123

tCLCL-40

 

tCLCL+40

ns

 

 

WR

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data valid to

 

 

 

 

 

transition

 

tQVWX

33

-

tCLCL-50

 

-

 

ns

 

WR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data setup before

 

 

 

 

 

 

 

 

 

 

tQVWH

433

-

7tCLCL-150

 

-

 

ns

 

WR

 

 

 

 

 

Data hold after

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tWHQX

33

-

tCLCL-50

 

-

 

ns

 

WR

 

 

 

 

 

 

Address float after

 

 

 

 

 

 

 

 

tRLAZ

-

0

-

 

0

 

ns

 

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Advance Information (12MHz)

 

 

 

 

 

 

 

 

 

 

 

External Clock Drive

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Variable Oscillator

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

Symbol

 

 

(Freq. = 3.5 to 12MHz)

 

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Min.

 

Max.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Oscillator period (VCC=5V)

 

tCLCL

 

 

83.3

 

285.7

 

ns

 

Oscillator period (VCC=3.3V)

 

tCLCL

 

 

83.3

 

 

1

 

 

 

High time

 

tCHCX

 

 

20

 

tCLCL - tCLCX

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

Low time

 

tCLCX

 

 

20

 

tCLCL - tCHCX

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

Rise time

 

tCLCH

 

 

-

 

 

20

 

ns

 

Fall time

 

tCHCL

 

 

-

 

 

20

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

30

Jan. 2001 Ver 1.0

GMS90X5XC Series

HYUNDAI MicroElectronics

AC Characteristics for GMS90X5XC series (16MHz version)

VCC= 3.3V + 0.3V, −0.6V; VSS= 0V; TA= 0°C to 70°C

(CL for port 0. ALE and PSEN outputs = 50pF; CL for all other outputs = 50pF)

External Program Memory Characteristics

 

 

 

 

 

 

 

 

 

 

 

 

 

16 MHz Oscillator

Variable Oscillator

 

 

 

 

Parameter

Symbol

1/tCLCL = 3.5 to 16MHz

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Min.

Max.

Min.

Max.

 

 

 

 

 

 

 

 

 

 

ALE pulse width

tLHLL

85

-

2tCLCL-40

-

ns

 

Address setup to ALE

tAVLL

23

-

tCLCL-40

-

ns

 

Address hold after ALE

tLLAX

23

-

tCLCL-40

-

ns

 

 

 

 

 

 

 

 

 

ALE low to valid instruction in

tLLIV

-

150

-

4tCLCL-100

ns

 

ALE to

 

 

 

 

 

 

 

 

 

tLLPL

38

-

tCLCL-25

-

ns

 

PSEN

 

 

 

 

 

 

 

 

 

 

pulse width

tPLPH

153

-

3tCLCL-35

-

ns

 

PSEN

 

 

to valid instruction in

tPLIV

-

88

-

3tCLCL-100

ns

 

PSEN

 

Input instruction hold after

 

 

tPXIX

0

-

0

-

ns

 

PSEN

 

 

Input instruction float after

 

 

 

tPXIZ

-

43

-

tCLCL-20

ns

 

PSEN

 

 

Address valid after

 

 

 

 

 

 

tPXAV

55

-

tCLCL-8

-

ns

 

PSEN

 

 

Address to valid instruction in

tAVIV

-

198

-

5tCLCL-115

ns

 

Address float to

 

 

 

 

 

 

 

tAZPL

0

-

0

-

ns

 

PSEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interfacing the GMS90X5XC series to devices with float times up to 35 ns is permissible. This limited bus contention will not

cause

any damage to port 0 Drivers.

Jan. 2001 Ver 1.0

31

HYUNDAI MicroElectronics

 

 

 

 

 

 

 

GMS90X5XC Series

AC Characteristics for GMS90X5XC series (16MHz)

 

 

 

 

 

 

 

External Data Memory Characteristics

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16 MHz Oscillator

 

Variable Oscillator

 

 

 

 

 

 

 

 

 

Parameter

 

Symbol

1/tCLCL = 3.5 to 16MHz

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Min.

Max.

 

Min.

 

Max.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

pulse width

 

tRLRH

275

-

6tCLCL-100

 

-

 

ns

 

RD

 

 

 

 

 

 

 

 

 

pulse width

 

tWLWH

275

-

6tCLCL-100

 

-

 

ns

 

WR

 

 

 

 

 

Address hold after ALE

 

tLLAX2

23

-

tCLCL-40

 

-

 

ns

 

 

 

to valid data in

 

tRLDV

-

183

-

 

5tCLCL-130

ns

 

RD

 

 

 

Data hold after

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tRHDX

0

-

0

 

-

 

ns

 

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data float after

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tRHDZ

-

75

-

 

2tCLCL-50

ns

 

RD

 

 

 

 

 

 

 

 

 

 

 

ALE to valid data in

 

tLLDV

-

350

-

 

8tCLCL-150

ns

 

Address to valid data in

 

tAVDV

-

398

-

 

9tCLCL-165

ns

 

ALE to

 

 

 

or

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tLLWL

138

238

3tCLCL50

 

3tCLCL+50

ns

 

WR

RD

 

 

 

 

 

 

 

 

 

 

 

 

Address valid to

 

 

 

 

 

 

 

or

 

 

 

tAVWL

120

-

4tCLCL-130

 

-

 

ns

 

WR

RD

 

 

 

 

 

 

 

 

 

or

 

high to ALE high

 

tWHLH

28

97

tCLCL35

 

tCLCL+35

ns

 

 

WR

RD

 

 

 

Data valid to

 

 

 

 

 

transition

 

tQVWX

13

-

tCLCL50

 

-

 

ns

 

WR

 

 

 

 

Data setup before

 

 

 

 

 

 

 

 

 

 

tQVWH

288

-

7tCLCL-150

 

-

 

ns

 

WR

 

 

 

 

 

Data hold after

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tWHQX

23

-

tCLCL40

 

-

 

ns

 

WR

 

 

 

 

 

 

Address float after

 

 

 

 

 

 

 

 

tRLAZ

-

0

-

 

0

 

ns

 

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Advance Information (16MHz)

 

 

 

 

 

 

 

 

 

 

 

External Clock Drive

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Variable Oscillator

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

Symbol

 

 

(Freq. = 3.5 to 16MHz)

 

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Min.

 

Max.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Oscillator period

 

tCLCL

 

 

62.5

 

285.7

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

High time

 

tCHCX

 

 

17

 

tCLCL - tCLCX

 

ns

 

Low time

 

tCLCX

 

 

17

 

tCLCL - tCHCX

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

Rise time

 

tCLCH

 

 

-

 

 

17

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

Fall time

 

tCHCL

 

 

-

 

 

17

 

ns

32

Jan. 2001 Ver 1.0

GMS90X5XC Series

HYUNDAI MicroElectronics

AC Characteristics for GMS90X5XC series (24MHz version)

VCC= 5V + 10%, −15%; VSS= 0V; TA= 0°C to 70°C

(CL for port 0. ALE and PSEN outputs = 100pF; CL for all other outputs = 80pF)

External Program Memory Characteristics

 

 

 

 

 

 

 

 

 

 

 

 

 

24 MHz Oscillator

Variable Oscillator

 

 

 

 

Parameter

Symbol

1/tCLCL = 3.5 to 24MHz

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Min.

Max.

Min.

Max.

 

 

 

 

 

 

 

 

 

 

ALE pulse width

tLHLL

43

-

2tCLCL-40

-

ns

 

Address setup to ALE

tAVLL

17

-

tCLCL-25

-

ns

 

Address hold after ALE

tLLAX

17

-

tCLCL-25

-

ns

 

 

 

 

 

 

 

 

 

ALE low to valid instruction in

tLLIV

-

80

-

4tCLCL-87

ns

 

ALE to

 

 

 

 

 

 

 

 

 

tLLPL

22

-

tCLCL-20

-

ns

 

PSEN

 

 

 

 

 

 

 

 

 

 

pulse width

tPLPH

95

-

3tCLCL-30

-

ns

 

PSEN

 

 

to valid instruction in

tPLIV

-

60

-

3tCLCL-65

ns

 

PSEN

 

Input instruction hold after

 

 

tPXIX

0

-

0

-

ns

 

PSEN

 

 

Input instruction float after

 

 

 

tPXIZ

-

32

-

tCLCL-10

ns

 

PSEN

 

 

Address valid after

 

 

 

 

 

 

tPXAV

37

-

tCLCL-5

-

ns

 

PSEN

 

 

Address to valid instruction in

tAVIV

-

148

-

5tCLCL-60

ns

 

Address float to

 

 

 

 

 

 

 

tAZPL

0

-

0

-

ns

 

PSEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interfacing the GMS90X5XC series to devices with float times up to 35 ns is permissible. This limited bus contention will not

cause

any damage to port 0 Drivers.

Jan. 2001 Ver 1.0

33

HYUNDAI MicroElectronics

 

 

 

 

 

 

 

GMS90X5XC Series

AC Characteristics for GMS90X5XC series (24MHz)

 

 

 

 

 

 

 

External Data Memory Characteristics

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

24 MHz Oscillator

 

Variable Oscillator

 

 

 

 

 

 

 

 

 

Parameter

 

Symbol

1/tCLCL = 3.5 to 24MHz

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Min.

Max.

 

Min.

 

Max.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

pulse width

 

tRLRH

180

-

6tCLCL-70

 

-

 

ns

 

RD

 

 

 

 

 

 

 

 

 

pulse width

 

tWLWH

180

-

6tCLCL-70

 

-

 

ns

 

WR

 

 

 

 

 

Address hold after ALE

 

tLLAX2

15

-

tCLCL-27

 

-

 

ns

 

 

 

to valid data in

 

tRLDV

-

118

-

 

5tCLCL-90

ns

 

RD

 

 

 

Data hold after

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tRHDX

0

-

0

 

-

 

ns

 

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data float after

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tRHDZ

-

63

-

 

2tCLCL-20

ns

 

RD

 

 

 

 

 

 

 

 

 

 

 

ALE to valid data in

 

tLLDV

-

200

-

 

8tCLCL-133

ns

 

Address to valid data in

 

tAVDV

-

220

-

 

9tCLCL-155

ns

 

ALE to

 

 

 

or

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tLLWL

75

175

3tCLCL-50

 

3tCLCL+50

ns

 

WR

RD

 

 

 

 

 

 

 

 

 

 

 

 

Address valid to

 

 

 

 

 

 

 

or

 

 

 

tAVWL

67

-

4tCLCL-97

 

-

 

ns

 

WR

RD

 

 

 

 

 

 

 

 

 

or

 

high to ALE high

 

tWHLH

17

67

tCLCL-25

 

tCLCL+25

ns

 

 

WR

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data valid to

 

 

 

 

 

 

transition

 

tQVWX

5

-

tCLCL-37

 

-

 

ns

 

WR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data setup before

 

 

 

 

 

 

 

 

 

 

tQVWH

170

-

7tCLCL-122

 

-

 

ns

 

WR

 

 

 

 

 

Data hold after

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tWHQX

15

-

tCLCL-27

 

-

 

ns

 

WR

 

 

 

 

 

 

Address float after

 

 

 

 

 

 

 

 

tRLAZ

-

0

-

 

0

 

ns

 

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Advance Information (24MHz)

 

 

 

 

 

 

 

 

 

 

 

External Clock Drive

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Variable Oscillator

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

Symbol

 

 

(Freq. = 3.5 to 24MHz)

 

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Min.

 

Max.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Oscillator period

 

tCLCL

 

 

41.7

 

285.7

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

High time

 

tCHCX

 

 

12

 

tCLCL - tCLCX

 

ns

 

Low time

 

tCLCX

 

 

12

 

tCLCL - tCHCX

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

Rise time

 

tCLCH

 

 

-

 

 

12

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

Fall time

 

tCHCL

 

 

-

 

 

12

 

ns

34

Jan. 2001 Ver 1.0

GMS90X5XC Series

HYUNDAI MicroElectronics

AC Characteristics for GMS90X5XC series (33MHz version)

VCC= 5V + 10%, −15%; VSS= 0V; TA= 0°C to 70°C

(CL for port 0. ALE and PSEN outputs = 100pF; CL for all other outputs = 80pF)

External Program Memory Characteristics

 

 

 

 

 

 

 

 

 

 

 

 

 

33 MHz Oscillator

Variable Oscillator

 

 

 

 

Parameter

Symbol

1/tCLCL = 3.5 to 33MHz

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Min.

Max.

Min.

Max.

 

 

 

 

 

 

 

 

 

 

ALE pulse width

tLHLL

40

-

2tCLCL-20

-

ns

 

Address setup to ALE

tAVLL

10

-

tCLCL-20

-

ns

 

Address hold after ALE

tLLAX

10

-

tCLCL-20

-

ns

 

 

 

 

 

 

 

 

 

ALE low to valid instruction in

tLLIV

-

56

-

4tCLCL-65

ns

 

ALE to

 

 

 

 

 

 

 

 

 

tLLPL

15

-

tCLCL-15

-

ns

 

PSEN

 

 

 

 

 

 

 

 

 

 

pulse width

tPLPH

80

-

3tCLCL-20

-

ns

 

PSEN

 

 

to valid instruction in

tPLIV

-

35

-

3tCLCL-55

ns

 

PSEN

 

Input instruction hold after

 

 

tPXIX

0

-

0

-

ns

 

PSEN

 

 

Input instruction float after

 

 

 

tPXIZ

-

20

-

tCLCL-10

ns

 

PSEN

 

 

Address valid after

 

 

 

 

 

 

tPXAV

25

-

tCLCL-5

-

ns

 

PSEN

 

 

Address to valid instruction in

tAVIV

-

91

-

5tCLCL-60

ns

 

Address float to

 

 

 

 

 

 

 

tAZPL

0

-

0

-

ns

 

PSEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interfacing the GMS90X5XC series to devices with float times up to 35 ns is permissible. This limited bus contention will not

cause

any damage to port 0 Drivers.

Jan. 2001 Ver 1.0

35

HYUNDAI MicroElectronics

 

 

 

 

 

 

 

GMS90X5XC Series

AC Characteristics for GMS90X5XC series (33MHz)

 

 

 

 

 

 

 

External Data Memory Characteristics

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

33 MHz Oscillator

 

Variable Oscillator

 

 

 

 

 

 

 

 

 

Parameter

 

Symbol

1/tCLCL = 3.5 to 33MHz

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Min.

Max.

 

Min.

 

Max.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

pulse width

 

tRLRH

132

-

6tCLCL-50

 

-

 

ns

 

RD

 

 

 

 

 

 

 

 

 

pulse width

 

tWLWH

132

-

6tCLCL-50

 

-

 

ns

 

WR

 

 

 

 

 

Address hold after ALE

 

tLLAX2

10

-

tCLCL-20

 

-

 

ns

 

 

 

to valid data in

 

tRLDV

-

81

-

 

5tCLCL-70

ns

 

RD

 

 

 

Data hold after

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tRHDX

0

-

0

 

-

 

ns

 

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data float after

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tRHDZ

-

46

-

 

2tCLCL-15

ns

 

RD

 

 

 

 

 

 

 

 

 

 

 

ALE to valid data in

 

tLLDV

-

153

-

 

8tCLCL-90

ns

 

Address to valid data in

 

tAVDV

-

183

-

 

9tCLCL-90

ns

 

ALE to

 

 

 

or

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tLLWL

71

111

3tCLCL-20

 

3tCLCL+20

ns

 

WR

RD

 

 

 

 

 

 

 

 

 

 

 

 

Address valid to

 

 

 

 

 

 

 

or

 

 

 

tAVWL

66

-

4tCLCL-55

 

-

 

ns

 

WR

RD

 

 

 

 

 

 

 

 

 

or

 

high to ALE high

 

tWHLH

10

40

tCLCL-20

 

tCLCL+20

ns

 

 

WR

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data valid to

 

 

 

 

 

 

transition

 

tQVWX

5

-

tCLCL-25

 

-

 

ns

 

WR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data setup before

 

 

 

 

 

 

 

 

 

 

tQVWH

142

-

7tCLCL-70

 

-

 

ns

 

WR

 

 

 

 

 

Data hold after

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tWHQX

10

-

tCLCL-20

 

-

 

ns

 

WR

 

 

 

 

 

 

Address float after

 

 

 

 

 

 

 

 

tRLAZ

-

0

-

 

0

 

ns

 

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Advance Information (33MHz)

 

 

 

 

 

 

 

 

 

 

 

External Clock Drive

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Variable Oscillator

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

Symbol

 

 

(Freq. = 3.5 to 24MHz)

 

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Min.

 

 

Max.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Oscillator period

 

tCLCL

 

 

30.3

 

285.7

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

High time

 

tCHCX

 

 

11.5

 

tCLCL - tCLCX

 

ns

 

Low time

 

tCLCX

 

 

11.5

 

tCLCL - tCHCX

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

Rise time

 

tCLCH

 

 

-

 

 

5

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

Fall time

 

tCHCL

 

 

-

 

 

5

 

ns

36

Jan. 2001 Ver 1.0

GMS90X5XC Series

HYUNDAI MicroElectronics

AC Characteristics for GMS90X5XC series (40MHz version)

VCC= 5V + 10%, − 15%; VSS= 0V; TA= 0°C to 70°C

(CL for port 0. ALE and PSEN outputs = 100pF; CL for all other outputs = 80pF)

External Program Memory Characteristics

 

 

 

 

 

 

 

 

 

 

 

 

 

40 MHz Oscillator

Variable Oscillator

 

 

 

 

Parameter

Symbol

1/tCLCL = 3.5 to 40MHz

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Min.

Max.

Min.

Max.

 

 

 

 

 

 

 

 

 

 

ALE pulse width

tLHLL

35

-

2tCLCL15

-

ns

 

Address setup to ALE

tAVLL

10

-

tCLCL15

-

ns

 

Address hold after ALE

tLLAX

10

-

tCLCL15

-

ns

 

ALE low to valid instruction in

tLLIV

-

55

-

4tCLCL45

ns

 

ALE to

 

 

 

 

 

 

 

 

 

tLLPL

10

-

tCLCL15

-

ns

 

PSEN

 

 

 

 

 

 

 

 

 

 

pulse width

tPLPH

60

-

3tCLCL15

-

ns

 

PSEN

 

 

to valid instruction in

tPLIV

-

25

-

3tCLCL50

ns

 

PSEN

 

Input instruction hold after

 

 

tPXIX

0

-

0

-

ns

 

PSEN

 

 

Input instruction float after

 

 

 

tPXIZ

-

15

-

tCLCL10

ns

 

PSEN

 

 

Address valid after

 

 

 

 

 

 

tPXAV

20

-

tCLCL5

-

ns

 

PSEN

 

 

Address to valid instruction in

tAVIV

-

65

-

5tCLCL60

ns

 

Address float to

 

 

 

 

 

 

 

tAZPL

5

-

5

-

ns

 

PSEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interfacing the GMS90X5XC series to devices with float times up to 20 ns is permissible. This limited bus contention will not

cause any damage to port 0 Drivers.

Jan. 2001 Ver 1.0

37

HYUNDAI MicroElectronics

 

 

 

 

 

 

 

GMS90X5XC Series

AC Characteristics for GMS90X5XC series (40MHz)

 

 

 

 

 

 

 

External Data Memory Characteristics

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

at 40 MHz Clock

 

Variable Clock

 

 

 

 

 

 

 

 

 

Parameter

 

Symbol

1/tCLCL = 3.5 to 40MHz

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Min.

Max.

 

Min.

 

Max.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

pulse width

 

tRLRH

120

-

6tCLCL-30

 

-

 

ns

 

RD

 

 

 

 

 

 

 

 

 

pulse width

 

tWLWH

120

-

6tCLCL-30

 

-

 

ns

 

WR

 

 

 

 

 

Address hold after ALE

 

tLLAX2

10

-

tCLCL-15

 

-

 

ns

 

 

 

to valid data in

 

tRLDV

-

75

-

 

5tCLCL-50

ns

 

RD

 

 

 

Data hold after

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tRHDX

0

-

0

 

-

 

ns

 

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data float after

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tRHDZ

-

38

-

 

2tCLCL-12

ns

 

RD

 

 

 

 

 

 

 

 

 

 

 

ALE to valid data in

 

tLLDV

-

150

-

 

8tCLCL-50

ns

 

Address to valid data in

 

tAVDV

-

150

-

 

9tCLCL-75

ns

 

ALE to

 

 

 

or

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tLLWL

60

90

3tCLCL-15

 

3tCLCL+15

ns

 

WR

RD

 

 

 

 

 

 

 

 

 

 

 

 

Address valid to

 

 

 

 

 

 

 

or

 

 

 

tAVWL

70

-

4tCLCL-30

 

-

 

ns

 

WR

RD

 

 

 

 

 

 

 

 

 

or

 

high to ALE high

 

tWHLH

10

40

tCLCL-15

 

tCLCL+15

ns

 

 

WR

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data valid to

 

 

 

 

 

 

transition

 

tQVWX

5

-

tCLCL-20

 

-

 

ns

 

WR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data setup before

 

 

 

 

 

 

 

 

 

 

tQVWH

125

-

7tCLCL-50

 

-

 

ns

 

WR

 

 

 

 

 

Data hold after

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tWHQX

5

-

tCLCL-20

 

-

 

ns

 

WR

 

 

 

 

 

 

Address float after

 

 

 

 

 

 

 

 

tRLAZ

-

0

-

 

0

 

ns

 

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Advance Information (40MHz)

 

 

 

 

 

 

 

 

 

 

 

External Clock Drive

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Variable Oscillator

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

Symbol

 

 

(Freq. = 3.5 to 40MHz)

 

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Min.

 

 

Max.

 

 

 

 

 

 

 

 

 

<