HP ADCS-2021, ADCS-1021 Datasheet

Agilent ADCS-1021, ADCS-2021

CMOS Image Sensors

Data Sheet

Description

The ADCS-1021 and ADCS-2021 CMOS Image Sensors capture high quality, low noise images while consuming very low power. These parts integrate a highly sensitive active pixel photodiode array with timing control and onboard A/D conversion. Available in either VGA (640x480) or CIF (352x288) resolution image arrays, the devices are ideally suited for a wide variety of applications.

The ADCS-2021 and ADCS-1021, when coupled with compatible image processors from either Agilent or selected Agilent partners, provide a complete imaging system to enable rapid end-product development. Designed for low-cost consumer electronic applications, the ADCS-2021 and ADCS-1021 sensors deliver unparalleled performance for mainstream imaging applications.

ADCS-2021 (VGA) and ADCS-1021 (CIF) are CMOS active pixel image sensors with integrated A/D conversion and full timing control. They provide random access of sensor pixels, which allows windowing and panning capabilities. The sensor is designed for video conferencing

applications and still image capabilities. The ADCS family achieves excellent image quality with very low dark current, high sensitivity, and superior antiblooming characteristics. The devices operate from a single DC bias voltage, are easy to configure and control, and feature low power consumption.

Programmable Features

•Programmable window size ranging from the full array down to a 4 x 4 pixel window

•Programmable panning capability which allows a specified window (minimum 4x4 pixels) to be located anywhere on the sensor array

•Integrated programmable gain amplifiers with independent gain control for each color (R, G, B)

•Internal register set programmable via either the UART or Synchronous serial interface

•Integrated timing controller with rolling electronic shutter, row/ column addressing, and operating mode selection with programmable exposure control, frame rate, and data rate

•Programmable horizontal, vertical, and shutter synchronization signals

•Programmable horizontal and vertical blanking intervals

Key Specifications and Features

•High quality, low cost CMOS image sensors

•Industry-standard 32-pin CLCC package

•VGA resolution (640H x 480V)– ADCS-2021

•CIF resolution (352H x 288V)– ADCS-1021

•High frame rates for digital video

VGA: 15 frames/second CIF: 30 frames/second

•High sensitivity, low noise design ideal for capturing high-quality images in a variety of lighting conditions

•Integrated analog-to-digital converters:

VGA (ADCS-2021): 10 bit, programmable CIF (ADCS-1021): 8 bit, fixed

•Parallel and serial output

•Automated, dark response compensation

•Automatic subtraction of column fixed pattern noise

•Still image capability

•Synchronous serial or UART interface

•Integrated voltage references

Applications

•Digital still camera

•PC camera

•Handheld computers

•Cellular phones

•Notebook computers

•Toys

Brief Introduction

The Agilent ADCS-2021 and Agilent ADCS-1021 image sensors act as normal CMOS digital devices from the outside. Internal circuits are a combination of sensitive analog and timing circuits. Therefore, the designer must pay attention to the PC board layout and power supply design. Writing to registers via an I2C compatible two-wire interface provides control of the sensor. Sensor data is normally output via an 8 or 10 bit parallel interface (serial data output is also available). Once the registers are programmed the sensor is selfclocking and all timing is internally generated. On chip programmable amplifiers provide a way to separately adjust the red green and blue pixels for a good white balance. Analog to digital conversion is also on chip and 8 or 10 bit digital data is output. A data ready pulse follows each valid pixel output. An end of row signal follows each row and an end of frame signal follows each frame.

PCB Layout

Analog Vdd and analog ground need to be routed separately from digital Vdd and digital ground. Noisy circuits or ICs should not be placed on the opposite side of the PC board. Heat producing circuits such as microprocessors or LCD displays should not be placed next to or opposite from the sensor to reduce noise in the image.

Power Supply

The sensor operates at 3.3 VDC. There are two power supplies for the sensor. Analog Vdd and Digital Vdd. The two supplies and grounds must be kept separate. Two separate regulators provide the best isolation. Any noise on the analog supply will result in noise in the image. Analog and digital ground should be tied together at a single point of lowest impedance and noise.

Master Clock

The part requires a 50% duty cycle master clock. Maximum clock rates are 25 MHz for ADCS-2021 and 32 MHZ for ADCS-1021.

Reset

A hard reset is required before the sensor will function properly. Once the master clock is running, assert nRST_nSTBY for 40 clock cycles.

Register Communication

Communication (read/write) to the sensor registers is via a two wire serial interface—either a synchronous I2C compatible or half duplex UART (9600 baud default). nTristate (pin 3 ADCS-1021 only) must be pulled high for normal operation. The ADCS-2021 does not have nTristate.

Parallel Data Output

8 or 10 bit parallel data is output from the sensor. A data ready line (DRDY) is asserted when the data is valid. The sensor acts as a master in the way it outputs data. There is no flow control or data received handshake. Once the RUN bit (CONTROL register) is set, the image processor must be ready to accept data at the sensor rate and when the data is presented.

Serial Data Output

In this mode, output data lines D0 and D1 (the lower two bits of the parallel data port) act as a two wire serial interface.

Handshaking

At the end of one row of data, the nROW line is asserted. At the end of one frame of data, the nFRAME_nSYNC line is asserted.

Registers

On the next page is a table of sample register settings (see Figure 1). These values are a good starting point.

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Table 1. Register Set Declaration for Agilent ADCS-1021 and ADCS-2021 Image Sensors.

Register Name	Mnemonic	Address (hex)	Sample Value (hex)
Identifications Register	IDENT	0x00
Status Register	STATUS	0x01	0x7F
Interrupt Mask Register	IMASK	0x02	0x00
Pad Control Register	PCTRL	0x03	0x03
Pad Drive Control Register	PDRV	0x04	0x00
Interface Control Register	ICTRL	0x05	0x20
Interface Timing Register	ITMG	0x06	0x00
Baud Fraction Register	BFRAC	0x07	0x00
Baud Rate Register	BRATE	0x08	0x00
ADC Control Register	ADCCTRL	0x09	0x08
First Window Row Register	FWROW	0x0A	0x00
First Window Column Register	FWCOL	0x0B	0x07
Last Window Row Register	LWROW	0x0C	0x79
Last Window Column Register	LWCOL	0x0D	0xA8
Timing Control Register	TCTRL	0x0E	0x04
PGA Gain Register: Green	ERECPGA	0x0F	0x00
PGA Gain Register: Red	EROCPGA	0x10	0x00
PGA Gain Register: Blue	ORECPGA	0x11	0x00
PGA Gain Register: Green	OROCPGA	0x12	0x00
Row Exposure Low Register	ROWEXPL	0x13	0x00
Row Exposure High Register	ROWEXPH	0x14	0x02
Sub-Row Exposure Register	SROWEXP	0x15	0x00
Error Control Register	ERROR	0x16	0x00
Interface Timing 2 Register	ITMG2	0x17	0x4B
Interface Control 2 Register	ICTRL2	0x18	0x00
Horizontal Blank Register	HBLANK	0x19	0x00
Vertical Blank Register	VBLANK	0x1A	0x00
Configuration Register	CONFIG	0x1B	0x0C
Control Register	CONTROL	0x1C	0x04
Reserved		0x1D	—
Reserved		0x1E	—
Reserved		0x1F	—
Reserved		0x20	—

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