Hitachi k3377 Diagram

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DATA SHEET

MOS FIELD EFFECT TRANSISTOR

2SK3377

SWITCHING

N-CHANNEL POWER MOS FET

INDUSTRIAL USE

DESCRIPTION

The 2SK3377 is N-Channel MOS Field Effect Transistor designed for high current switching applications.

FEATURES

Low On-state Resistance

RDS(on)1 = 44 mΩ MAX. (VGS = 10 V, ID = 10 A)

RDS(on)2 = 78 mΩ MAX. (VGS = 4.0 V, ID = 10 A)

Low Ciss : Ciss = 760 pF TYP.

Built-in Gate Protection Diode

TO-251/TO-252 package

ORDERING INFORMATION

PART NUMBER

PACKAGE

 

 

2SK3377

TO-251

 

 

2SK3377-Z

TO-252

 

 

(TO-251)

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)

 

Drain to Source Voltage

VDSS

60

V

 

 

Gate to Source Voltage

VGSS

±20

V

 

 

Drain Current (DC)

ID(DC)

±20

A

 

 

Drain Current (Pulse) Note1

ID(pulse)

±50

A

 

 

Total Power Dissipation (TC = 25°C)

P T

30

W

(TO-252)

 

 

 

Total Power Dissipation (TA = 25°C)

P T

1.0

W

 

 

Channel Temperature

Tch

150

°C

 

 

Storage Temperature

Tstg

–55 to +150

°C

 

 

Single Avalanche Current Note2

IAS

15

A

 

 

Single Avalanche Energy Note2

EAS

23

mJ

 

Notes 1. PW 10 μs, Duty cycle 1 %

2. Starting Tch = 25 °C, R G = 25 Ω, VGS = 20 V 0 V

THERMAL RESISTANCE

Channel to Case

Rth(ch-C)

4.17

°C/W

Channel to Ambient

Rth(ch-A)

125

°C/W

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. D14328EJ1V0DS00 (1st edition) Date Published January 2000 NS CP(K) Printed in Japan

The mark shows major revised points.

©

1999,2000

 

Hitachi k3377 Diagram

2SK3377

ELECTRICAL CHARACTERISTICS (TA = 25 °C)

CHARACTERISTICS

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

 

 

 

 

 

 

 

Drain to Source On-state Resistance

RDS(on)1

VGS = 10 V, ID = 10 A

 

35

44

mΩ

 

 

 

 

 

 

 

 

RDS(on)2

VGS = 4.0 V, ID = 10 A

 

54

78

mΩ

 

 

 

 

 

 

 

Gate to Source Cut-off Voltage

VGS(off)

VDS = 10 V, ID = 1 mA

1.5

2.0

2.5

V

 

 

 

 

 

 

 

Forward Transfer Admittance

| yfs |

VDS = 10 V, ID = 10 A

5

10

 

S

 

 

 

 

 

 

 

Drain Leakage Current

IDSS

VDS = 60 V, VGS = 0 V

 

 

10

μA

 

 

 

 

 

 

 

Gate to Source Leakage Current

IGSS

VGS = ±20 V, VDS = 0 V

 

 

±10

μA

 

 

 

 

 

 

 

Input Capacitance

Ciss

VDS = 10 V

 

760

 

pF

 

 

 

 

 

 

 

Output Capacitance

Coss

VGS = 0 V

 

150

 

pF

 

 

 

 

 

 

 

Reverse Transfer Capacitance

Crss

f = 1 MHz

 

71

 

pF

 

 

 

 

 

 

 

Turn-on Delay Time

td(on)

ID = 10 A

 

13

 

ns

 

 

 

 

 

 

 

Rise Time

tr

VGS(on) = 10 V

 

170

 

ns

 

 

 

 

 

 

 

Turn-off Delay Time

td(off)

VDD = 30 V

 

43

 

ns

 

 

RG = 10 Ω

 

 

 

 

Fall Time

tf

 

34

 

ns

 

 

 

 

 

 

 

Total Gate Charge

QG

ID = 20 A

 

17

 

nC

 

 

 

 

 

 

 

Gate to Source Charge

QGS

VDD = 48 V

 

3.0

 

nC

 

 

 

 

 

 

 

Gate to Drain Charge

QGD

VGS(on) = 10 V

 

4.7

 

nC

 

 

 

 

 

 

 

Body Diode Forward Voltage

VF(S-D)

IF = 20 A, VGS = 0 V

 

1.0

 

V

 

 

 

 

 

 

 

Reverse Recovery Time

trr

IF = 20 A, VGS = 0 V

 

39

 

ns

 

 

di/dt = 100 A/μs

 

 

 

 

Reverse Recovery Charge

Qrr

 

62

 

nC

 

 

 

 

 

 

 

TEST CIRCUIT 1 AVALANCHE CAPABILITY

TEST CIRCUIT 2 SWITCHING TIME

 

 

 

D.U.T.

 

 

 

 

 

 

 

RG = 25 Ω

L

 

D.U.T.

 

 

 

 

 

 

 

 

VGS

 

 

 

PG.

 

 

 

RL

 

 

90 %

 

 

 

VGS

 

 

VGS(on)

50 Ω

VDD

 

 

10 %

 

 

 

RG

Wave Form

 

 

 

VGS = 20 0 V

 

 

VDD

0

 

 

 

 

 

PG.

 

 

 

 

 

 

 

 

 

ID

90 %

 

90 %

 

BVDSS

 

 

 

 

 

ID

IAS

VGS

ID

0 10 %

 

10 %

 

VDS

 

 

 

0

 

 

 

ID

 

Wave Form

 

 

 

 

 

 

 

 

 

 

 

 

 

 

td(on)

tr

td(off)

tf

VDD

 

 

τ

 

 

 

 

τ = 1 μs

 

 

ton

 

toff

 

 

 

 

 

 

 

 

Starting Tch

 

Duty Cycle 1 %

 

 

 

 

 

TEST CIRCUIT 3 GATE CHARGE

 

D.U.T.

 

 

IG = 2 mA

RL

 

 

PG.

50 Ω

VDD

2

Data Sheet D14328EJ1V0DS00

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