HM628512B Series
4 M SRAM (512-kword × 8-bit)
ADE-203-903D (Z)
Rev. 3.0
Aug. 24, 1999
Description
The Hitachi HM628512B is a 4-Mbit static RAM organized 512-kword × 8-bit. It realizes higher density, higher performance and low power consumption by employing 0.35 µm Hi-CMOS process technology. The device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II or 600-mil plastic DIP, is available for high density mounting. The HM628512B is suitable for battery backup system.
Features
•Single 5 V supply
•Access time: 55/70 ns (max)
•Power dissipation
Active: 50 mW/MHz (typ)
Standby: 10 µW (typ)
•Completely static memory. No clock or timing strobe required
•Equal access and cycle times
•Common data input and output: Three state output
•Directly TTL compatible: All inputs and outputs
•Battery backup operation
HM628512B Series
Ordering Information
Type No. |
Access time |
Package |
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HM628512BLP-5 |
55 ns |
600-mil 32-pin plastic DIP (DP-32) |
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HM628512BLP-7 |
70 ns |
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HM628512BLP-5SL |
55 ns |
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HM628512BLP-7SL |
70 ns |
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HM628512BLP-5UL |
55 ns |
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HM628512BLP-7UL |
70 ns |
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HM628512BLFP-5 |
55 ns |
525-mil 32-pin plastic SOP (FP-32D) |
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HM628512BLFP-7 |
70 ns |
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HM628512BLFP-5SL |
55 ns |
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HM628512BLFP-7SL |
70 ns |
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HM628512BLFP-5UL |
55 ns |
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HM628512BLFP-7UL |
70 ns |
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HM628512BLTT-5 |
55 ns |
400-mil 32-pin plastic TSOP II (TTP-32D) |
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HM628512BLTT-7 |
70 ns |
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HM628512BLTT-5SL |
55 ns |
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HM628512BLTT-7SL |
70 ns |
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HM628512BLTT-5UL |
55 ns |
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HM628512BLTT-7UL |
70 ns |
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HM628512BLRR-5 |
55 ns |
400-mil 32-pin plastic TSOP II reverse (TTP-32DR) |
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HM628512BLRR-7 |
70 ns |
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HM628512BLRR-5SL |
55 ns |
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HM628512BLRR-7SL |
70 ns |
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HM628512BLRR-5UL |
55 ns |
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HM628512BLRR-7UL |
70 ns |
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2
HM628512B Series
Pin Arrangement
HM628512BLP Series
HM628512BLFP Series
A18 |
1 |
32 |
VCC |
A16 |
2 |
31 |
A15 |
A14 |
3 |
30 |
A17 |
A12 |
4 |
29 |
WE |
A7 |
5 |
28 |
A13 |
A6 |
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27 |
A8 |
A5 |
7 |
26 |
A9 |
A4 |
8 |
25 |
A11 |
A3 |
9 |
24 |
OE |
A2 |
10 |
23 |
A10 |
A1 |
11 |
22 |
CS |
A0 |
12 |
21 |
I/O7 |
I/O0 |
13 |
20 |
I/O6 |
I/O1 |
14 |
19 |
I/O5 |
I/O2 |
15 |
18 |
I/O4 |
VSS |
16 |
17 |
I/O3 |
(Top view)
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HM628512BLTT Series |
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A18 |
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1 |
32 |
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VCC |
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A16 |
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2 |
31 |
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A15 |
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A14 |
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3 |
30 |
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A17 |
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A12 |
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4 |
29 |
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WE |
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A7 |
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5 |
28 |
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A13 |
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A6 |
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6 |
27 |
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A8 |
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A5 |
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7 |
26 |
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A9 |
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A4 |
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8 |
25 |
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A11 |
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A3 |
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9 |
24 |
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OE |
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A2 |
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10 |
23 |
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A10 |
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A1 |
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11 |
22 |
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CS |
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A0 |
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12 |
21 |
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I/O7 |
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I/O0 |
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13 |
20 |
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I/O6 |
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I/O1 |
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14 |
19 |
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I/O5 |
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I/O2 |
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18 |
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I/O4 |
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VSS |
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16 |
17 |
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I/O3 |
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(Top view) |
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HM628512BLRR Series |
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VCC |
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32 |
1 |
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A18 |
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A15 |
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31 |
2 |
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A16 |
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A17 |
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30 |
3 |
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A14 |
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WE |
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29 |
4 |
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A12 |
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A13 |
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28 |
5 |
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A7 |
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A8 |
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27 |
6 |
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A6 |
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A9 |
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26 |
7 |
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A5 |
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A11 |
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25 |
8 |
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A4 |
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OE |
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24 |
9 |
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A3 |
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A10 |
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23 |
10 |
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A2 |
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CS |
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22 |
11 |
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A1 |
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I/O7 |
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21 |
12 |
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A0 |
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I/O6 |
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20 |
13 |
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I/O0 |
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I/O5 |
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19 |
14 |
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I/O1 |
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I/O4 |
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18 |
15 |
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I/O2 |
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I/O3 |
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17 |
16 |
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VSS |
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(Top view)
Pin Description
Pin name |
Function |
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A0 to A18 |
Address input |
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I/O0 to I/O7 |
Data input/output |
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CS |
Chip select |
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OE |
Output enable |
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WE |
Write enable |
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VCC |
Power supply |
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VSS |
Ground |
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3
HM628512B Series
Block Diagram
A18 |
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V CC |
A16 |
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V SS |
A1 |
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A0 |
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• |
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• |
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A2 |
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Memory Matrix |
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• |
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Row |
1,024 × 4,096 |
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• |
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A12 |
Decoder |
• |
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A14 |
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A3 |
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A7 |
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A6 |
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I/O0 |
• |
Column I/O |
• |
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• |
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Input |
Column Decoder |
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Data |
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Control |
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I/O7 |
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A13A17A15A8 A9 A11A10A4 A5 |
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• |
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• |
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CS |
Timing Pulse Generator |
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WE |
Read/Write Control |
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OE |
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HM628512B Series |
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Function Table |
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WE |
CS |
OE |
Mode |
VCC current |
Dout pin |
Ref. cycle |
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× |
H |
× |
Not selected |
ISB, ISB1 |
High-Z |
— |
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H |
L |
H |
Output disable |
ICC |
High-Z |
— |
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H |
L |
L |
Read |
ICC |
Dout |
Read cycle |
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L |
L |
H |
Write |
ICC |
Din |
Write cycle (1) |
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L |
L |
L |
Write |
ICC |
Din |
Write cycle (2) |
Note: ×: H or L
Absolute Maximum Ratings
Parameter |
Symbol |
Value |
Unit |
Power supply voltage |
VCC |
–0.5 to +7.0 |
V |
Voltage on any pin relative to VSS |
VT |
–0.5*1 to VCC + 0.3*2 |
V |
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Power dissipation |
PT |
1.0 |
W |
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Operating temperature |
Topr |
–20 to +70 |
°C |
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Storage temperature |
Tstg |
–55 to +125 |
°C |
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Storage temperature under bias |
Tbias |
–20 to +85 |
°C |
Notes: 1. –3.0 V for pulse half-width ≤ 30 ns 2. Maximum voltage is 7.0 V
Recommended DC Operating Conditions (Ta = –20 to +70°C)
Parameter |
Symbol |
Min |
Typ |
Max |
Unit |
Supply voltage |
VCC |
4.5 |
5.0 |
5.5 |
V |
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VSS |
0 |
0 |
0 |
V |
Input high voltage |
VIH |
2.2 |
— |
V CC + 0.3 |
V |
Input low voltage |
V |
–0.3*1 |
— |
0.8 |
V |
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IL |
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Note: 1. –3.0 V for pulse half-width ≤ 30 ns
5
HM628512B Series
DC Characteristics (Ta = –20 to +70°C, VCC = 5 V ±10% , VSS = 0 V)
Parameter |
Symbol |
Min |
Typ*1 Max |
Unit |
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Test conditions |
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Input leakage current |
|ILI| |
— |
— |
1 |
A |
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Vin = VSS to VCC |
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Output leakage current |
|ILO| |
— |
— |
1 |
A |
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CS = VIH or OE = VIH or |
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WE = VIL, VI/O = VSS to VCC |
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Operating power supply current: DC |
ICC |
— |
8 |
15 |
mA |
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CS = VIL, |
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others = VIH/VIL, II/O = 0 mA |
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Operating power supply current |
ICC1 |
— |
40 |
60 |
mA |
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Min cycle, duty = 100% |
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CS = VIL, others = VIH/VIL |
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II/O = 0 mA |
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Operating power supply current |
ICC2 |
— |
10 |
20 |
mA |
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Cycle time = 1 s, |
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duty = 100% |
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II/O |
= 0 mA, CS ≤ 0.2 V |
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VIH |
≥ VCC – 0.2 V, VIL ≤ 0.2 V |
Standby power supply current: DC |
ISB |
— |
1 |
3 |
mA |
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CS = VIH |
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Standby power supply current (1): DC |
ISB1 |
— |
2* 2 |
100*2 |
A |
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Vin ≥ 0 V, CS ≥ VCC – 0.2 V |
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— |
2* 3 |
50*3 |
A |
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— |
2* 4 |
20*4 |
A |
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Output low voltage |
VOL |
— |
— |
0.4 |
V |
I |
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OL = 2.1 mA |
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Output high voltage |
VOH |
2.4 |
— |
— |
V |
I |
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OH = –1.0 mA |
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and specified loading, and not guaranteed.
2.This characteristics is guaranteed only for L version.
3.This characteristics is guaranteed only for L-SL version.
4.This characteristics is guaranteed only for L-UL version.
Capacitance (Ta = +25°C, f = 1 MHz)
Parameter |
Symbol |
Typ |
Max |
Unit |
Test conditions |
Input capacitance*1 |
Cin |
— |
8 |
pF |
Vin = 0 V |
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Input/output capacitance*1 |
CI/O |
— |
10 |
pF |
V I/O = 0 V |
Note: 1. This parameter is sampled and not 100% tested.
6