HIT HM628128DLFP-5, HM628128DLFP-5SL, HM628128DLFP-5UL, HM628128DLFP-7, HM628128DLFP-7SL Datasheet

HM628128D Series

1 M SRAM (128-kword × 8-bit)

ADE-203-996 (Z)

Preliminary, Rev. 0.0

Jan. 20, 1999

Description

The Hitachi HM628128D Series is 1-Mbit static RAM organized 131,072-kword × 8-bit. HM628128D Series has realized higher density, higher performance and low power consumption by employing HiCMOS process technology. The HM628128D Series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It has package variations of standard 32-pin plastic DIP, standard 32-pin plastic SOP and standard 32-pin plastic TSOPI.

Features

•Single 5 V supply: 5 V ± 10%

•Access time: 55 ns/70 ns (max)

•Power dissipation

Active: 30 mW/MHz (typ)

Standby: 10 µW (typ)

•Completely static memory.

No clock or timing strobe required

•Equal access and cycle times

•Common data input and output

Three state output

•Directly TTL compatible all inputs

•Battery backup operation

2 chip selection for battery backup

HM628128D Series

Ordering Information

Type No.	Access time	Package
HM628128DLP-5	55 ns	600-mil 32-pin plastic DIP (DP-32)
HM628128DLP-7	70 ns
HM628128DLP-5SL	55 ns
HM628128DLP-7SL	70 ns
HM628128DLP-5UL	55 ns
HM628128DLP-7UL	70 ns
HM628128DLFP-5	55 ns	525-mil 32-pin plastic SOP (FP-32D)
HM628128DLFP-7	70 ns
HM628128DLFP-5SL	55 ns
HM628128DLFP-7SL	70 ns
HM628128DLFP-5UL	55 ns
HM628128DLFP-7UL	70 ns
HM628128DLTS-5	55 ns	8 × 13.4 mm 32-pin plastic TSOP I (TFP-32DC)
HM628128DLTS-7	70 ns
HM628128DLTS-5SL	55 ns
HM628128DLTS-7SL	70 ns
HM628128DLTS-5UL	55 ns
HM628128DLTS-7UL	70 ns
HM628128DLT-5	55 ns	Normal-bend type 8 × 20 mm 32-pin plastic TSOP I (TFP-32D)
HM628128DLT-7	70 ns
HM628128DLT-5SL	55 ns
HM628128DLT-7SL	70 ns
HM628128DLT-5UL	55 ns
HM628128DLT-7UL	70 ns
HM628128DLR-5	55 ns	Reverse-bend type 8 × 20 mm 32-pin plastic TSOP I (TFP-32DR)
HM628128DLR-7	70 ns
HM628128DLR-5SL	55 ns
HM628128DLR-7SL	70 ns
HM628128DLR-5UL	55 ns
HM628128DLR-7UL	70 ns

2

HM628128D Series

Pin Arrangement

	32-pin DIP/SOP
NC	1	32	VCC
A16	2	31	A15
A14	3	30	CS2
A12	4	29	WE
A7	5	28	A13
A6	6	27	A8
A5	7	26	A9
A4	8	25	A11
A3	9	24	OE
A2	10	23	A10
A1	11	22	CS1
A0	12	21	I/O7
I/O0	13	20	I/O6
I/O1	14	19	I/O5
I/O2	15	18	I/O4
VSS	16	17	I/O3

(Top view)

		32-pin TSOP (Normal Type TSOP)
A11		1	32		OE
A9		2	31		A10
A8		3	30		CS1
A13		4	29		I/O7
WE		5	28		I/O6
CS2		6	27		I/O5
A15		7	26		I/O4
VCC		8	25		I/O3
NC		9	24		VSS
A16		10	23		I/O2
A14		11	22		I/O1
A12		12	21		I/O0
A7		13	20		A0
A6		14	19		A1
A5		15	18		A2
A4		16	17		A3

			(Top view)
		32-pin TSOP (Reverse Type TSOP)
OE		32	1		A11
A10		31	2		A9
CS1		30	3		A8
I/O8		29	4		A13
I/O7		28	5		WE
I/O6		27	6		CS2
I/O5		26	7		A15
I/O4		25	8		VCC
VSS		24	9		NC
I/O3		23	10		A16
		22
I/O2			11		A14
		21
I/O1			12		A12
		20
A0			13		A7
		19
A1			14		A6
		18
A2			15		A5
		17
A3			16		A4

(Top View)

Pin Description

Pin name	Function
A0 to A16	Address input
I/O0 to I/O7	Data input/output
CS1	Chip select 1
CS2	Chip select 2
WE	Write enable
OE	Output enable
VCC	Power supply
VSS	Ground
NC	No connection

3

HM628128D Series

Block Diagram

LSB					VCC
A12
A7					VSS
A6
A5		•
		•
A4	Row	•	Memory matrix
		•
A3	decoder	•	512 x 2,048
A2
A1
A0
A10
MSB
I/O0		•	Column I/O		•
					•
		•
	Input		Column decoder
	data
	control
I/O7
		LSB A14 A16 A15 A13 A8		A9 A11	MSB
			•
			•
CS1	Timing pulse generator
CS2
WE	Read/Write control
OE

4

						HM628128D Series
	Operation Table
	CS1	CS2	WE	OE	I/O	Operation
	H	H	×	×	High-Z	Standby
	L	L	×	×	High-Z	Standby
	L	L	×	×	High-Z	Standby
	L	H	H	L	Dout	Read
	L	H	L	H	Din	Write
	L	H	L	L	Din	Write
	L	H	H	H	High-Z	Output disable

Note: H: VIH, L: VIL, ×: VIH or VIL

Absolute Maximum Ratings

Parameter	Symbol	Value	Unit
Power supply voltage relative to VSS	VCC	–0.5 to +7.0	V
Terminal voltage on any pin relative to VSS	VT	–0.5*1 to VCC + 0.3*2	V
Power dissipation	PT	1.0	W
Storage temperature range	Tstg	–55 to +125	°C
Storage temperature range under bias	Tbias	–20 to +85	°C

Notes: 1. VT min: –1.5 V for pulse half-width ≤ 30 ns 2. Maximum voltage is +7.0 V

DC Operating Conditions

Parameter	Symbol	Min	Typ	Max	Unit	Note
Supply voltage	VCC	4.5	5.0	5.5	V
	VSS	0	0	0	V
Input high voltage	VIH	2.2	—	VCC + 0.3	V
Input low voltage	VIL	–0.3	—	0.8	V	1
Ambient temperature range	Ta	–20	—	+70	°C

Note: 1. VIL min: –1.5 V for pulse half-width ≤ 30 ns

5

HM628128D Series

DC Characteristics

Parameter	Symbol	Min	Typ*1	Max	Unit	Test conditions
Input leakage current	|ILI|	—	—	1	A	Vin = VSS to VCC
Output leakage current	|ILO|	—	—	1	A	CS1 = VIH or CS2 = VIL or
						OE = VIH or WE = VIL,
						VI/O = VSS to VCC
Operating current	ICC	—	—	15	mA	CS1 = VIL, CS2 = VIH,
						others = VIH/VIL, II/O = 0 mA
Average operating current	ICC1	—	—	60	mA	Min cycle, duty = 100%
						II/O = 0 mA, CS1 = VIL, CS2
						= VIH, Others = VIH/VIL
	ICC2	—	6	20	mA	Cycle time = 1 s,
						duty = 100%,
						II/O = 0 mA, CS1 ≤ 0.2 V,
						CS2 ≥ VCC – 0.2 V,
						VIH	≥ VCC – 0.2 V,
						VIL	≤ 0.2 V
Standby current	ISB	—	—	2	mA	(1) CS1 = VIH, CS2 = VIH, or
						(2) CS2 = VIL
	ISB1*2	—	2	100	A	0 V ≤ Vin
						(1) 0 V ≤ CS2 ≤ 0.2 V or
						(2) CS1 ≥ VCC – 0.2 V,
							CS2 ≥ VCC – 0.2 V
	ISB1*3	—	2	50	A
	ISB1*4	—	1	20	A
Output high voltage	VOH	2.4	—	—	V	IOH = –1 mA
Output low voltage	VOL	—	—	0.4	V	IOL = 2.1 mA

Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and specified loading, and not guaranteed.

2.This characteristics is guaranteed only for L version.

3.This characteristics is guaranteed only for L-SL version.

4.This characteristics is guaranteed only for L-UL version.

Capacitance (Ta = +25°C, f = 1 MHz)

Parameter	Symbol	Typ	Max	Unit	Test conditions	Note
Input capacitance	Cin	—	8	pF	Vin = 0 V	1
Input/output capacitance	CI/O	—	10	pF	VI/O = 0 V	1

Note: 1. This parameter is sampled and not 100% tested.

6