HM628128D Series
1 M SRAM (128-kword × 8-bit)
ADE-203-996 (Z)
Preliminary, Rev. 0.0
Jan. 20, 1999
Description
The Hitachi HM628128D Series is 1-Mbit static RAM organized 131,072-kword × 8-bit. HM628128D Series has realized higher density, higher performance and low power consumption by employing HiCMOS process technology. The HM628128D Series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It has package variations of standard 32-pin plastic DIP, standard 32-pin plastic SOP and standard 32-pin plastic TSOPI.
Features
•Single 5 V supply: 5 V ± 10%
•Access time: 55 ns/70 ns (max)
•Power dissipation
Active: 30 mW/MHz (typ)
Standby: 10 µW (typ)
•Completely static memory.
No clock or timing strobe required
•Equal access and cycle times
•Common data input and output
Three state output
•Directly TTL compatible all inputs
•Battery backup operation
2 chip selection for battery backup
HM628128D Series
Ordering Information
Type No. |
Access time |
Package |
HM628128DLP-5 |
55 ns |
600-mil 32-pin plastic DIP (DP-32) |
HM628128DLP-7 |
70 ns |
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HM628128DLP-5SL |
55 ns |
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HM628128DLP-7SL |
70 ns |
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HM628128DLP-5UL |
55 ns |
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HM628128DLP-7UL |
70 ns |
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HM628128DLFP-5 |
55 ns |
525-mil 32-pin plastic SOP (FP-32D) |
HM628128DLFP-7 |
70 ns |
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HM628128DLFP-5SL |
55 ns |
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HM628128DLFP-7SL |
70 ns |
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HM628128DLFP-5UL |
55 ns |
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HM628128DLFP-7UL |
70 ns |
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HM628128DLTS-5 |
55 ns |
8 × 13.4 mm 32-pin plastic TSOP I (TFP-32DC) |
HM628128DLTS-7 |
70 ns |
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HM628128DLTS-5SL |
55 ns |
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HM628128DLTS-7SL |
70 ns |
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HM628128DLTS-5UL |
55 ns |
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HM628128DLTS-7UL |
70 ns |
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HM628128DLT-5 |
55 ns |
Normal-bend type 8 × 20 mm 32-pin plastic TSOP I (TFP-32D) |
HM628128DLT-7 |
70 ns |
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HM628128DLT-5SL |
55 ns |
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HM628128DLT-7SL |
70 ns |
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HM628128DLT-5UL |
55 ns |
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HM628128DLT-7UL |
70 ns |
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HM628128DLR-5 |
55 ns |
Reverse-bend type 8 × 20 mm 32-pin plastic TSOP I (TFP-32DR) |
HM628128DLR-7 |
70 ns |
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HM628128DLR-5SL |
55 ns |
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HM628128DLR-7SL |
70 ns |
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HM628128DLR-5UL |
55 ns |
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HM628128DLR-7UL |
70 ns |
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2
HM628128D Series
Pin Arrangement
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32-pin DIP/SOP |
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NC |
1 |
32 |
VCC |
A16 |
2 |
31 |
A15 |
A14 |
3 |
30 |
CS2 |
A12 |
4 |
29 |
WE |
A7 |
5 |
28 |
A13 |
A6 |
6 |
27 |
A8 |
A5 |
7 |
26 |
A9 |
A4 |
8 |
25 |
A11 |
A3 |
9 |
24 |
OE |
A2 |
10 |
23 |
A10 |
A1 |
11 |
22 |
CS1 |
A0 |
12 |
21 |
I/O7 |
I/O0 |
13 |
20 |
I/O6 |
I/O1 |
14 |
19 |
I/O5 |
I/O2 |
15 |
18 |
I/O4 |
VSS |
16 |
17 |
I/O3 |
(Top view)
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32-pin TSOP (Normal Type TSOP) |
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A11 |
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1 |
32 |
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OE |
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A9 |
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2 |
31 |
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A10 |
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A8 |
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3 |
30 |
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CS1 |
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A13 |
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4 |
29 |
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I/O7 |
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WE |
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5 |
28 |
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I/O6 |
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CS2 |
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6 |
27 |
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I/O5 |
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A15 |
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7 |
26 |
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I/O4 |
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VCC |
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8 |
25 |
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I/O3 |
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NC |
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9 |
24 |
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VSS |
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A16 |
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10 |
23 |
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I/O2 |
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A14 |
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11 |
22 |
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I/O1 |
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A12 |
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12 |
21 |
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I/O0 |
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A7 |
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13 |
20 |
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A0 |
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A6 |
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14 |
19 |
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A1 |
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A5 |
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15 |
18 |
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A2 |
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A4 |
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16 |
17 |
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A3 |
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(Top view) |
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32-pin TSOP (Reverse Type TSOP) |
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OE |
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32 |
1 |
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A11 |
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A10 |
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31 |
2 |
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A9 |
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CS1 |
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30 |
3 |
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A8 |
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I/O8 |
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29 |
4 |
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A13 |
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I/O7 |
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28 |
5 |
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WE |
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I/O6 |
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27 |
6 |
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CS2 |
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I/O5 |
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26 |
7 |
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A15 |
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I/O4 |
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25 |
8 |
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VCC |
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VSS |
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24 |
9 |
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NC |
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I/O3 |
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23 |
10 |
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A16 |
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22 |
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I/O2 |
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11 |
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A14 |
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21 |
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I/O1 |
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12 |
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A12 |
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20 |
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A0 |
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13 |
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A7 |
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19 |
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A1 |
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14 |
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A6 |
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18 |
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A2 |
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15 |
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A5 |
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17 |
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A3 |
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16 |
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A4 |
(Top View)
Pin Description
Pin name |
Function |
A0 to A16 |
Address input |
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I/O0 to I/O7 |
Data input/output |
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CS1 |
Chip select 1 |
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CS2 |
Chip select 2 |
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WE |
Write enable |
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OE |
Output enable |
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VCC |
Power supply |
VSS |
Ground |
NC |
No connection |
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3
HM628128D Series
Block Diagram
LSB |
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VCC |
A12 |
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A7 |
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VSS |
A6 |
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A5 |
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• |
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• |
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A4 |
Row |
• |
Memory matrix |
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• |
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A3 |
decoder |
• |
512 x 2,048 |
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A2 |
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A1 |
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A0 |
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A10 |
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MSB |
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I/O0 |
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• |
Column I/O |
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• |
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• |
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• |
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Input |
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Column decoder |
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data |
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control |
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I/O7 |
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LSB A14 A16 A15 A13 A8 |
A9 A11 |
MSB |
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• |
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• |
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CS1 |
Timing pulse generator |
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CS2 |
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WE |
Read/Write control |
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OE |
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4
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HM628128D Series |
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Operation Table |
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CS1 |
CS2 |
WE |
OE |
I/O |
Operation |
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H |
H |
× |
× |
High-Z |
Standby |
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L |
L |
× |
× |
High-Z |
Standby |
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L |
L |
× |
× |
High-Z |
Standby |
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L |
H |
H |
L |
Dout |
Read |
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L |
H |
L |
H |
Din |
Write |
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L |
H |
L |
L |
Din |
Write |
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L |
H |
H |
H |
High-Z |
Output disable |
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Note: H: VIH, L: VIL, ×: VIH or VIL
Absolute Maximum Ratings
Parameter |
Symbol |
Value |
Unit |
Power supply voltage relative to VSS |
VCC |
–0.5 to +7.0 |
V |
Terminal voltage on any pin relative to VSS |
VT |
–0.5*1 to VCC + 0.3*2 |
V |
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Power dissipation |
PT |
1.0 |
W |
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Storage temperature range |
Tstg |
–55 to +125 |
°C |
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Storage temperature range under bias |
Tbias |
–20 to +85 |
°C |
Notes: 1. VT min: –1.5 V for pulse half-width ≤ 30 ns 2. Maximum voltage is +7.0 V
DC Operating Conditions
Parameter |
Symbol |
Min |
Typ |
Max |
Unit |
Note |
Supply voltage |
VCC |
4.5 |
5.0 |
5.5 |
V |
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|
VSS |
0 |
0 |
0 |
V |
|
Input high voltage |
VIH |
2.2 |
— |
VCC + 0.3 |
V |
|
Input low voltage |
VIL |
–0.3 |
— |
0.8 |
V |
1 |
Ambient temperature range |
Ta |
–20 |
— |
+70 |
°C |
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Note: 1. VIL min: –1.5 V for pulse half-width ≤ 30 ns
5
HM628128D Series
DC Characteristics
Parameter |
Symbol |
Min |
Typ*1 |
Max |
Unit |
Test conditions |
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Input leakage current |
|ILI| |
— |
— |
1 |
A |
Vin = VSS to VCC |
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Output leakage current |
|ILO| |
— |
— |
1 |
A |
CS1 = VIH or CS2 = VIL or |
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OE = VIH or WE = VIL, |
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VI/O = VSS to VCC |
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Operating current |
ICC |
— |
— |
15 |
mA |
CS1 = VIL, CS2 = VIH, |
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others = VIH/VIL, II/O = 0 mA |
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Average operating current |
ICC1 |
— |
— |
60 |
mA |
Min cycle, duty = 100% |
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II/O = 0 mA, CS1 = VIL, CS2 |
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= VIH, Others = VIH/VIL |
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ICC2 |
— |
6 |
20 |
mA |
Cycle time = 1 s, |
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duty = 100%, |
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II/O = 0 mA, CS1 ≤ 0.2 V, |
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CS2 ≥ VCC – 0.2 V, |
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VIH |
≥ VCC – 0.2 V, |
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VIL |
≤ 0.2 V |
Standby current |
ISB |
— |
— |
2 |
mA |
(1) CS1 = VIH, CS2 = VIH, or |
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(2) CS2 = VIL |
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ISB1*2 |
— |
2 |
100 |
A |
0 V ≤ Vin |
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(1) 0 V ≤ CS2 ≤ 0.2 V or |
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(2) CS1 ≥ VCC – 0.2 V, |
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CS2 ≥ VCC – 0.2 V |
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ISB1*3 |
— |
2 |
50 |
A |
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ISB1*4 |
— |
1 |
20 |
A |
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Output high voltage |
VOH |
2.4 |
— |
— |
V |
IOH = –1 mA |
|
Output low voltage |
VOL |
— |
— |
0.4 |
V |
IOL = 2.1 mA |
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and specified loading, and not guaranteed.
2.This characteristics is guaranteed only for L version.
3.This characteristics is guaranteed only for L-SL version.
4.This characteristics is guaranteed only for L-UL version.
Capacitance (Ta = +25°C, f = 1 MHz)
Parameter |
Symbol |
Typ |
Max |
Unit |
Test conditions |
Note |
Input capacitance |
Cin |
— |
8 |
pF |
Vin = 0 V |
1 |
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Input/output capacitance |
CI/O |
— |
10 |
pF |
VI/O = 0 V |
1 |
Note: 1. This parameter is sampled and not 100% tested.
6