HIT HA16138PS Datasheet

HA16138PS
AC/DC Switching Converter Controller IC
With High-Voltage Power MOS FET
ADE-204-032 (Z)
Preliminary
1st Edition
MAY 2000
Description
The HA16138PS includes an energy-saving mode for holding down power consumption when on standby (no load). When the energy-saving mode is entered, the operating frequency is reduced to 1/4 the normal frequency, reducing power consumption. A starter circuit is also provided on-chip, eliminating the need for the external start-up resistance needed with previous controller ICs. The starter circuit in this IC is turned off automatically after the IC starts up, enabling the start-up resistance power consumption to be decreased.
The HA16138PS includes a soft start circuit, OVP circuit, and remote on/off circuit, making it possible to configure a simple protection circuit with fewer external parts than previously. Also provided are a current sense resistance and a leading edge blanking circuit that masks spike noise on current sense input, making noise reduction in a power supply set comparatively easy.
The HA16138PS is equipped with an error amp circuit inverting input (FB) pin and output (COMP) pin, enabling special-purpose design for both flyback system secondary-side output voltage detection and primary-side back-up transformer output voltage detection types.
Features
Built-in high-voltage power MOS FET
Energy-saving mode (power saving through reduction of operating frequency to 1/4 normal frequency
when on standby)
Built-in starter circuit, reducing power loss of start-up resistance when on standby (external start-up
resistance not necessary)
Built-in soft start circuit, eliminating need for external connection
Remote on/off function, enabling power saving by halting PWM output without turning off power
supply
Built-in current sense resistance and leading edge blanking circuit, for sense-resistance-less and noise-
cancellation-filter-less implementation
Built-in over voltage protection circuit
Built-in over temperature protection circuit
HA16138PS
Pin Arrangement
1DRAIN
2DRAIN
3VDD
4FB
DILP-8
(DP-8)
(Top view)
SOURCE
8
SGND
7
CT
6
COMP
5
Pin Functions
Pin No. Pin Name Pin Function
1 DRAIN On-chip power MOS FET drain pin / starter circuit input pin 2 DRAIN On-chip power MOS FET drain pin / starter circuit input pin 3 VDD Power supply voltage input pin 4 FB Error amplifier inverting input pin / OVP latch circuit input pin 5 COMP Error amplifier output pin 6 CT Timing capacitance connection pin / on/off circuit input pin 7 SGND Primary-side common connection pin 8 SOURCE On-chip power MOS FET source pin
2
Block Diagram
HA16138PS
VDD
CT
FB
Oscillator
VDD
Vref
+
E-AMP
VDD
RSQ
+
OVP Latch
+
ON/OFF Comp.
1/4 Divider
+
Frequency Down Comp.
TSD
COMP
Vref Generator
CK
DQ
1/3 Attenuator
UVL
UVL
FF
Vref
+
Soft Start
UVL
CS Comp.
Leading Edge Blanking
+
Delay
Starter
Driver
DRAIN
SOURCE
Rcs
3
HA16138PS
Absolute Maximum Ratings (Ta = 25°C)
Item Symbol Rating Unit
Power MOS FET block Drain-source voltage V
Maximum drain current I
Controller block Power supply voltage V
CT pin voltage V FB pin voltage V COMP pin voltage V
DS
DS
DD
CT
FB
COMP
Overall Operating temperature Topr 20 to +85 °C
Junction temperature Tjmax +150 °C Storage temperature Tstg 55 to +150 °C
0.3 to 700 V
0.5 A 0 to 15 V 0 to V
DD
0 to V
DD
0 to 5 V
V V
4
HA16138PS
Electrical Characteristics (Tj = 25°C, VDD = 12 V, fosc1 = 100 kHz)
Item Symbol Min Typ Max Unit Test Conditions
Power Drain-source voltage BV MOS FET Drain-source on resistance R Starter Start-up start drain voltage V circuit Start-up charge current I UVL circuit Operation start power supply
V
DS(on)
DRN
CHG
TH
voltage Operation stop power supply
V
TL
voltage Operating power supply current I
DD
Oscillation Normal mode operating frequency fosc1 88 100 112 kHz CT = 220 pF circuit F-down mode operating frequency fosc2 22 25 28 kHz CT = 220 pF, V
Maximum on duty Dumax 70 %
Error Open-loop voltage gain A
V
amplifier Unity gain bandwidth BW 550 kHz Rcomp = 220 k
Output high voltage 1 V Output high voltage 2 V Output low voltage V
Non-inverting input voltage V Power Output rise time t MOS FET Output fall time t gate drive Output high voltage V circuit Output low voltage V Current Current sense voltage gain A
COMPH1
COMPH2
COMPL
(+)EA
r
f
OH
OL
VCS
sense Current sense response time tpdcs 200 ns Vcomp = 5.0 V circuit Leading edge blanking time t
BL
OVP latch OVP latch set voltage Vovp 4.2 5.0 5.8 V Vovp: FB pin voltage circuit OVP latch reset voltage Vovpr 4.0 V Vovpr: VDD pin voltage
OVP latch current dissipation Iovp 1.1 1.7 mA VFB = 6.0 V Remote
Off mode start voltage Voff 3.6 3.8 4.0 V Voff: CT pin voltage on/off circuit
Soft start
Soft start time tst (1.0) 2.0 (3.0) ms Time from start-up to circuit
f-down
F-down mode start voltage Vfdcp 0.7 0.85 1.0 V comparator
Over temperature
Over temperature protection start
temperature
TSD 150 °C TSD: Power MOS FET
protection circuit
700 V
DSS
12 20 ID = 0.4 A 55 75 95 V 125 250 500 µA 10 11 12 V
789V
2.5 4.0 mA
50 65 dB Rcomp = 220 k
4.5 5.0 V Iosource = 0 µA
4.3 4.8 V Iosource = 100 µA 0.50 0.75 V Iosink = 0 µA
3.4 3.8 4.2 V
100 ns CL = 1000 pF  80 ns CL = 1000 pF  10 V Iosource = 25 mA 0.5 V Iosink = 25 mA 3.0 V/V
300 ns
COMP
max. duty
junction temperature
= 0 V
5
HA16138PS
Functional Description
Note: Unless specified otherwise, characteristic values in the text and figures are typical values or design
values.
Starter Circuit
When power is turned on, the starter circuit operates during standby mode, and a constant current is supplied from the drain pins to the VDD pin. This constant current supplies the external capacitance charge current for charging up the VDD pin and the standby current consumed by the IC itself while on standby.
Therefore, the start-up bleeder resistance required by previous products with no on-chip starter circuit is no longer necessary. The starter circuit detects both the drain voltage and the VDD pin voltage, and controls VDD so that the IC does not start up if the drain voltage is less than 75 V.
Vb+
0
DRAIN
75V
0
Istart
VDD
CT
COMP
DC OUTPUT
0
11V
8V
0
0
0
0
Figure 1 Start-Up Timing
UVL Circuit
The UVL circuit is a function that monitors the VDD voltage, and stops IC operation if VDD is low. The VDD detection voltage has a hysteresis characteristic; the operating start VDD voltage is 11 V, and the operation stop voltage, 8 V.
6
HA16138PS
Error Amplifier
The error amplifier comprises a constant-current source type Pch top differential amplifier. As the inverting input (FB) pin and output (COMP) pin are provided as external pins, use for both a simple flyback power supply back-up voltage feedback type and a high-precision secondary voltage detection type is possible.
Current Sense Circuit
This is a 200 ns high-speed comparator circuit suitable for current mode control. The current sense controller reference voltage depends on the COMP pin voltage, being always 1/3 of the COMP pin voltage.
Power MOS FET
Current sense resistance
Osc.
+
Error amplifier
FF
+
Current sense comparator
2R
R
Driver
300 ns
Delay circuit
Leading edge blanking
1/3 attenuator
Figure 2 Current Sense Peripheral Circuitry
Leading Edge Blanking Circuit
The on-chip leading edge blanking circuit masks the current sense comparator input signal for a period of 300 ns after the power MOS FET gate voltage goes high. This reduces the erroneous operation due to spike-shaped noise caused by discharge of various capacitance components when the power MOS FET is turned on.
7
HA16138PS
Oscillation Circuit
The oscillator generates a triangular voltage waveform through the discharge of the timing capacitance CT. With a 220 pF CT connected, the oscillator operates at 100 kHz.
The triangular voltage waveform has a discharge time ratio of 3:1, with the charge side set to PWM on­pulses, and the discharge side to dead-band pulses. The maximum PWM on duty can be controlled up to 70%.
CT
DB pulse (IC internal waveform)
1/3COMP (IC internal waveform)
CS (IC internal waveform)
Power MOS FET Gate voltage (IC internal waveform)
Power MOS FET Drain voltage
Figure 3 Oscillation Circuit Peripheral Waveform Timing
OVP Latch Circuit
When the FB pin voltage reaches 5 V or above, the OVP latch circuit operates and forcibly stops PWM output and the reference voltage generation circuit. While OVP latching is stopped, the starter circuit is also stopped. Latch resetting can be performed by driving power supply voltage VDD to 4 V or below.
DRAIN
0
CT
0
FB
0
Vref (IC internal waveform)
5V
5V
0
Figure 4 OVP Latch Operation Timing
8
HA16138PS
Remote On/Off Circuit
When the CT pin voltage is pulled up to 3.8 V or above, the remote on/off circuit operates and PWM output can be stopped without turning off the power supply. When stoppage is executed by means of the on/off circuit, PWM output and the starter circuit are stopped, and the soft start circuit is reset, but the reference voltage generation circuit does not stop.
DRAIN
0
CT
Vref (IC internal waveform)
5V
3.8V
Figure 5 Remote On/Off Operation Timing
Soft Start Circuit
This circuit implements a soft start function with a 2 ms time constant without the use of external parts. During a soft start, the PWM output pulse width gradually increases. The soft start time is defined as the time from the point at which the UVL circuit start voltage is exceeded to the point at which PWM output reaches its maximum duty.
9
HA16138PS
f-down Comparator
An "energy-saving mode" is provided to hold down power consumption during standby, with the operating frequency in the unloaded state reduced to 1/4 of its steady operation value.
The f-down comparator detects the COMP pin voltage, and if it falls to 0.85 V or below, switches to energy-saving mode. As COMP pin voltage detection is performed pulse-by-pulse, a skip mode comes into effect in the vicinity of the threshold voltage according to the timing.
V
CT
V
COMP
V
DRAIN
Normal
mode
Energy-
saving
mode
Normal
mode
Energy-
saving
mode
Figure 6 Energy-Saving Mode Switching Waveform Timing
Over Temperature Protection Circuit
If the power MOS FET junction temperature reaches +150°C, the over temperature protection circuit operates, shutting down the IC. The over temperature protection circuit is coupled to the OVP latch circuit, so that the latch is reset if the power supply voltage is driven to 4 V or below while the junction temperature is lower than the overheating protection start temperature.
10
Main Characteristics
HA16138PS
1000
300
100
fosc (kHz)
30
10
500 450 400
350 300
250 200
Idrain (µA)
150 100
50
Operating Frequency vs. Timing Capacitance
normal mode operating frequency
f-down mode operating frequency
100
Start-up Current (Charge Current + Standby Current)
0
0 10203040506070
200
300 400 500 1000
(pF)
C
T
vs. Drain Voltage
Vdrain (V)
80
12
10
8
6
VDD (V)
4
2
0
0 1020304050607080
Power Supply Voltage vs. Drain Voltage
Vdrain (V)
11
HA16138PS
Error Amplifier Output High Voltage vs. Output Source Current
6.0
5.0
4.0
(V)
3.0
OH
V
2.0
1.0
0
0 100 200 300 400 500 600 700 800
Iosource (µA)
Error Amplifier Output Low Voltage vs. Output Sink Current
2.5
2.0
1.5
(V)
OL
V
1.0
0.5
0
0 1000400 800200 600
Iosink (µA)
12
Operating Frequency (Normal Mode) vs. Ambient Temperature
110 108 106 104 102 100
98
fosc (kHz)
96 94 92 90
25 10025 75050 Ta (°C)
Operating Start/Stop Power Supply Voltage vs. Ambient Temperature
13
HA16138PS
12
V
TH
11
(V)
10
TL
, V
9
TH
V
8
V
TL
7 6
25 10025 75050 Ta (°C)
13
HA16138PS
Thermal Resistance θj-a and Maximum Power Dissipation vs.
Printed Circuit Board Copper Heat Sink Perimeter Length
120
2.5
100
80
60
θj-a (°C/W)
40
20
05020 4010 30
Length of copper, L (mm)
2.0 oz copper heat sink
Pt(max) for Ta = +85°C
θj-a
Pin holes
L
2.0
1.5
1.0
0.5 Maximum power dissipation (W)
0
Glass-epoxy printed circuit board
L
14
Wiring pattern
Figure 7 Sample Printed Circuit Board Copper Heat Sink Pattern
HA16138PS
Application Circuit Examples 1
The application circuit example shown here detects the secondary-side output voltage of a flyback power supply. Secondary-side output voltage detection and feedback are performed by a shunt regulator and photocoupler.
When the OVP latch function is used for secondary-side output voltage overvoltage protection, the FB pin should be pulled up to VDD by the shunt regulator and photocoupler.
Transformer P: 90T / 1.43mH
AC INPUT
0.1µ
Line Filter
: Primary GND
: Secondary GND
100µ 400V
2200p
+
VR 260V
S: 6T / 8.1µH B: 14T / 30.8µH
PS
51k
B
HA16138PS
SBD HRW26F
560µ
OVP detection circuit (7.4V)
15µ
+
+
180µ
25V
25V
K A
HA17431VP
R3 330
R4
1.8k C4
0.022µ
R5
3.3k
REF
R6
4.7k
R7
2.4k
R8 330
R9
1.8k C5
3.3µ
K
REF
A
HA17431VP
R10
3.3k
+
R11
2.4k
DC OUTPUT 5V/2A
R12
2.4k
DRAIN
1
DRAIN
2
OVP feedback circuit
C1
+
47µ VR 15V
R12
20V
R1 120k
The secondary-side output voltage is stabilized at a
*
value determined by the bleeder resistance of the secondary-side shunt regulator.
R11 + R12
VOUT(reg) = Vref(shunt)
= 2.5V ×
= 5.0V
×
2.4k + 2.4k
2.4k
VDD
3
FB
4
SOURCE
8
SGND
7
CT
6
COMP
5
C2
R2
2200pC3220p
15k
When the OVP latch function is used, the secondary-side voltage is detected by the shunt regulator, and feedback to the FB pin is performed by the photocoupler. The OVP detection level is determined by the following formula.
VOUT(ovp) = Vref(shunt) ×
= 2.5V ×
= 7.4V
Photo coupler
R6 + R7
R7
4.7k + 2.4k
2.4k
Units R:
C: F
15
HA16138PS
Application Circuit Examples 2
The application circuit example shown here detects the primary-side back-up output voltage of a flyback power supply. As the back-up output voltage, VDD is resistance-divided and feedback is performed to the FB pin. The back-up output voltage and secondary-side output voltage are proportional to the ratio of transformer windings. Using this characteristic enables the system to be configured with simple circuitry as shown in the figure below.
The VDD-to-FB feedback resistance can also be used as the back-up output voltage OVP detection resistance.
Transformer P: 90T / 1.43mH
AC INPUT
0.1µ
Line Filter
: Primary GND
100µ 400V
2200p +
VR 260V
S: 6T / 8.1µH B: 14T / 30.8µH
PS
51k
B
SBD HRW26F
560µ
25V
15µ
+
+
180µ
25V
+
DC OUTPUT 5V/1A
: Secondary GND
HA16138PS
DRAIN
1
R1 240k
C1
+
47µ
VR
R2 120k
If feedback resistance R1 = 240 k and R2 = 120 kΩ,
*
feedback is performed so that the FB pin voltage is non-inverting input voltage V is stabilized.
VDD(reg) = V
= 3.8V ×
= 11.4V
R1 + R2
×
(+)EA
240k + 120k
R2
120k
20V
15V
, and the VDD voltage
(+)EA
2 3 4
DRAIN VDD FB
SOURCE
8
SGND
7 6
CT
5
COMP
C2 0.1µ
R3 1M
When the FB pin voltage reaches OVP latch set voltage Vovp, the OVP latch circuit operates, shutting down the IC. The VDD voltage in this case is given by the following formula.
VDD(ovp) = Vovp ×
R4 15k
= 5.0V ×
= 15V
C3
C4
2200p
220p
Units R:
C: F
R1 + R2
R2
240k + 120k
120k
16
HA16138PS
Application Circuit Examples 3
As this IC is provided with a remote on/off function, it is possible to implement power management without turning off the power supply. Using a remote on/off control circuit as shown in the figure below, the CT pin voltage is pulled up to the off mode start voltage or above, and the IC is stopped. In the off mode, control of PWM output stoppage, soft start resistance resetting, and starter circuit stoppage is performed without stopping the internal reference voltage generation circuit. With this function, also, latch operation is not performed, and an auto-restart is executed as soon as the CT pin voltage falls below the off mode start voltage. It is recommended that the remote on/off control signal be controlled by a microcomputer or other logic signal.
Remote ON/OFF control circuit
R2 43k
HA16138PS
2SA1029
1 2 3 4
DRAIN DRAIN VDD FB
SOURCE
SGND
CT
COMP
8 7 6 5
CT 220p
R1 10k
2SC458
R3 130k
R4
10k
ON/OFF
H: OFF L: ON
Units R:
C: F
17
HA16138PS
Laser Marking Specifications
Product code
HA16138
Lot indication and Management code
PS
123
Lot Indication and Management Code Contents
: The last digit of the production year.
1
: Production month code
2
: Management code
3
Production month 1 2 3 4 5 6 7 8 9 10 11 12 Month code A B C D E F G H J K L M
18
Package Dimensions
0.89
10.6 Max
1
HA16138PS
Unit: mm
9.6
58
6.3
7.4 Max
4
1.3
2.54 ± 0.25
1.27 Max
0.48 ± 0.10
5.06 Max
0.1 Min
2.54 Min 0° – 15°
Hitachi Code JEDEC EIAJ Weight
7.62
+ 0.10
0.25
– 0.05
(reference value)
DP-8 Conforms Conforms
0.54 g
19
HA16138PS
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail­safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.
Hitachi, Ltd.
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Copyright ' Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.
20
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