* Input limit of VRI is more than 12dB on Vo max, and not variable range.
Rev.3, Jun. 1997, page 16 of 73
PB Mode (1 kHz NR-OFF)
E. VOLREC EQ
DOLBY - NR
0dBs = 775mVrms
Rev.3, Jun. 1997, page 17 of 73
Power Supply Range
HA12167FB/HA12169FB are designed to operate on either single supply or split supply.
The operating range of the supply voltage is shown in table 1.
Table 1Supply Voltage
Type No.Single SupplySplit Supply
HA12167FB12 V to 15 V±6.0 V to 7.5 V
HA12169FB11 V to 15 V±6.0 V to 7.5 V
The lower limit of supply voltage depends on the line output reference level.
The minimum value of the overload margin is specified as 12 dB by Dolby Laboratories. HA12167 series
are provided with two line output level, which will permit an optimum overload margin for power supply
For the single supply operation these devices provide the reference voltage of half the supply voltage that is
the signal grounds. As the peculiarity of these devices, the capacitor for the ripple filter is very small about
1/100 compared with their usual value. The Reference voltage are provided for the left channel and the
right channel separately. The block diagram is shown as figure 1.
Figure 1 The Block Diagram of Reference Voltage Supply
Rev.3, Jun. 1997, page 18 of 73
Operating Mode Control
HA12167FB/HA12169FB provides fully electronic switching circuits. All switches are controlled by serial
Table 2Threshold Voltage (VTH)
42–0.2 to 1.53.5 to 5.3V
39, 40, 41–0.2 to 1.04.0 to 5.3V
Notes: 1. Voltages shown above are determined by internal circuits of LSI when take pin 47 (DGND pin) as
reference pin. On split supply use, same VTH can be offered by connecting DGND pin to GND
This means that it can be controlled directly by micro processor.
2. Each pins are on pulled down with 100 kΩ internal resistor .
Therefore, it will be low-level when each pins are open.
3. Note on serial data inputting
(a)The clock frequency on CLK must be less than 500 kHz.
(b)Over shoot level and under shoot level of input signal must be the value shown below.
When connecting microcomputer or Logic-IC with HA12167FB/HA12169FB directly, there is
apprehension of rash-current under some transition timming of raising voltag e or falling voltage at V
For this countermeasure, connect 10 kΩ to 20 kΩ resistor with each pins. It is shown in test circuit on this
In case of changing NR-ON/OFF at the C-mode, for the countermeasure of the noise of pop, perform the
In case of changing NR-OFF to NR-ON at C-mode. C-mode, NR-OFF → B-mode, NR-OFF → B-mode,
NR-ON → C-mode, NR-ON.
In case of changing NR-ON to NR-OFF at C-mode. C-mode, NR-ON → B-mode, NR-ON → B-mode,
NR-OFF → C-mode, NR-OFF.
Under 5.3 V
Within –0.2 V
Figure 2 Input Level
Rev.3, Jun. 1997, page 19 of 73
Serial Data Formatting
14 bit shift register is employed.
CLK and data are stored during STB being high and data is latched when STB goes high to low.
Reset goes reset a state when reset low and high releasles reset. (High fixed at use time)
Attention Point of Serial Interface
• Reset goes low condition when a power supply is ON or OFF.
• Characteristics select of Bias DAC is connected with equalizer tape selector.
• Bias DAC register is all low when a time of tape select.
• Bias DAC register is all low and Bias DAC out is dropped low level at compulsion by force.
• Input pin select, REC/PB select and Input volume gain select does not select at the same time.
• Input volume must go mute condition when selected of RPI is input pin select.
Figure 3 Serial Data Timming Chart Figure
Figure 4 Bias DAC Output Circuit
Latch of data
Rev.3, Jun. 1997, page 20 of 73
Serial Data Formatting
Bit Mode ControlInput VoltageEaqualizer VoltageBasic DAC
6REC/PBH PB mode selectionHR
8MPXH ONLI-bit 2 LE-bit 2 LB-bit 2 L
9NRH ONLI-bit 3 LE-bit 3 LB-bit 3 L
10 B/CH CLI-bit 4 LE-bit 4 LB-bit 4 L
11 ———I-bit 5 H——B-bit 5 L
bit 1 HL
H Hi speed selectionLI-bit 2 LE-bit 2 LB-bit 2 L
L Normal speed selection
H Meter sensitivity 20 dBupLI-bit 3 LE-bit 3 LB-bit 3 L
L Meter sensitinity normal
bit 5 HL
L REC mode selection
H PB mode volume gain HI-bit 1 LE-bit 1 LB-bit 1 L
L Rec mode volume gain
bit 13 HL
HBias DACInput volume
LEqualizer volume Mode control
LI-bit 1 LE-bit 1 LB-bit 1 L
LI=bit 4 LE-bit 4 LB-bit 4 L
LI-bit 5 H——B-bit 5 L
I-bit 0 LL
I-bit 0 LR
E-bit 0 LL
E-bit 0 LR
B-bit o L
Rev.3, Jun. 1997, page 21 of 73
Input Volume Register
I-bit 5I-bit 4I-bit 3I-bit 2I-bit 1I-bit 0Gain
Equalizer Volume Register
E-bit 4E-bit 3E-bit 2E-bit 1E-bit 0Gain
Bias DAC Register
B-bit 5B-bit 4B-bit 3B-bit 2B-bit 1B-bit 0Bias
Rev.3, Jun. 1997, page 22 of 73
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