HIT BB305C Datasheet

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BB305C

Build in Biasing Circuit MOS FET IC

UHF/VHF RF Amplifier

ADE-208-608C (Z) 4th. Edition May 1998

Features

Build in Biasing Circuit; To reduce using parts cost & PC board space.

Superior cross modulation characteristics.

High gain; (PG = 28 dB typ. at f = 200 MHz)

Wide supply voltage range;

Applicable with 5 V to 9 V supply voltage.

Withstanding to ESD;

Build in ESD absorbing diode. Withstand up to 200V at C = 200 pF, Rs = 0 conditions.

Provide mini mold packages; CMPAK-4 (SOT-343mod)

Outline

CMPAK-4

2

3

1

4 1. Source

2. Gate1

3. Gate2

4. Drain

Note: 1. Marking is “EW–”.

2. BB305C is individual type number of HITACHI BBFET.

BB305C

Absolute Maximum Ratings (Ta = 25°C)

Item

Symbol

 

 

 

 

 

 

 

 

 

 

 

 

Ratings

Unit

Drain to source voltage

VDS

12

V

Gate1 to source voltage

VG1S

+10

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

–0

 

 

 

 

 

Gate2 to source voltage

VG2S

+10

V

Drain current

ID

25

mA

 

 

 

 

Channel power dissipation

Pch

100

mW

 

 

 

 

Channel temperature

Tch

150

°C

Storage temperature

Tstg

 

 

 

 

 

 

 

 

 

 

 

 

–55 to +150

°C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

BB305C

Electrical Characteristics (Ta = 25°C)

Item

Symbol

Min

 

Typ

Max

Unit

 

Test Conditions

Drain to source breakdown

V(BR)DSS

12

 

V

I

D = 200µA, VG1S = VG2S = 0

voltage

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Gate1 to source breakdown

V(BR)G1SS

+10

 

V

I

G1 = +10µA, VG2S = VDS = 0

voltage

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Gate2 to source breakdown

V(BR)G2SS

±10

 

V

I

G2 = ±10µA, VG1S = VDS = 0

voltage

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Gate1 to source cutoff current

IG1SS

+100

 

 

nA

V

G1S = +9V, VG2S = VDS = 0

Gate2 to source cutoff current

IG2SS

±100

nA

 

VG2S = ±9V, VG1S = VDS = 0

Gate1 to source cutoff voltage VG1S(off)

0.4

 

1.0

 

 

 

 

V

V DS = 5V, VG2S = 4V, ID = 100µA

 

 

 

 

 

 

 

 

 

 

 

Gate2 to source cutoff voltage VG2S(off)

0.4

 

1.0

 

 

 

 

V

V DS = 5V, VG1S = 5V, ID = 100µA

 

 

 

 

 

 

 

 

 

 

 

 

 

Input capacitance

Ciss

2.3

2.8

 

 

 

3.5

 

pF

 

VDS = 5V, VG1

= 5V

Output capacitance

Coss

1.1

1.5

 

 

 

1.9

 

pF

 

VG2S =4V, RG = 82kΩ

Reverse transfer capacitance

Crss

0.017

0.04

 

pF

f = 1MHz

 

Drain current

ID(op) 1

10

15

 

 

 

 

20

 

 

 

mA

 

VDS = 5V, VG1

= 5V, VG2S = 4V,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RG = 82kΩ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ID(op) 2

13

 

 

 

 

 

mA

V

DS = 9V, VG1

= 9V, VG2S =6V,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RG = 220kΩ

 

 

 

 

 

 

 

 

 

 

 

 

 

Forward transfer admittance

|yfs|1

23

28

 

 

 

 

mS

V DS = 5V, VG1

= 5V, VG2S =4V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RG =82kΩ, f = 1kHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

|yfs|2

28

 

 

 

 

 

mS

V

DS = 9V, VG1

= 9V, VG2S =6V,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RG = 220kΩ, f = 1kHz

 

 

 

 

 

 

 

 

 

 

 

 

Power gain

PG1

24

28

 

 

 

 

dB

V DS = 5V, VG1

= 5V, VG2S =4V,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RG = 82kΩ, f = 200MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PG2

28

 

 

 

 

 

dB

V

DS = 9V, VG1

= 9V, VG2S =6V,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RG = 220kΩ, f = 200MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Noise figure

NF1

1.3

 

 

 

 

1.8

 

 

 

 

dB

V DS = 5V, VG1

= 5V, VG2S =4V,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RG = 82kΩ, f = 200MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NF2

1.3

 

 

 

 

dB

V

DS = 9V, VG1

= 9V, VG2S =6V,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RG = 220kΩ, f = 200MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

HIT BB305C Datasheet

BB305C

Main Characteristics

Test Circuit for Operating Items (I D(op) , |yfs|, Ciss, Coss, Crss, NF, PG)

VG2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VG1

 

 

 

 

 

 

 

 

 

 

 

 

 

R G

 

 

 

 

 

 

Gate 2

 

 

 

 

 

 

 

Gate 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Drain

 

 

 

Source

 

 

A

I D

Power Gain, Noise Figure Test Circuit

V T

 

VG2

 

 

 

V T

1000p

 

1000p

 

 

 

1000p

 

1000p

47k

BBFET

 

 

47k

47k

 

 

L2

1000p

Output(50Ω)

 

 

 

Input(50Ω)

 

 

 

 

 

 

L1

 

 

 

 

 

10p max

1000p

 

1000p

RFC

 

 

 

 

 

 

1SV70

 

36p

1SV70

R G

82k

 

 

 

 

 

 

 

1000p

 

 

 

 

 

 

V D= V G1

Unit

Resistance

(Ω)

 

 

 

 

 

Capacitance

(F)

L1 : φ1mm Enameled Copper Wire,Inside dia 10mm, 2Turns

L2 : φ1mm Enameled Copper Wire,Inside dia 10mm, 2Turns

RFC : φ1mm Enameled Copper Wire,Inside dia 5mm, 2Turns

4

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