GSI GS882Z36BD-133I, GS882Z36BD-133, GS882Z36BB-250I, GS882Z36BB-250, GS882Z36BB-225I Datasheet

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Rev: 1.00b 12/2002 1/33 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
GS882Z18/36BB/D-250/225/200/166/150/133
9Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz133 MHz
2.5 V or 3.3 V V
2.5 V or 3.3 V I/O
119 and 165 BGA
Commercial Temp
Industrial Temp
Features
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high
/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip parity encoding and error detection
• LBO
pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 18M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119-bump BGA and 165-bump FPBGA
packages
Functional Description
The GS882Z18/36B is a 9Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO
) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS882Z18/36B may be configured by the user to operate
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, in addition to the rising-edge-triggered
registers that capture input signals, the device incorporates a
rising edge triggered output register. For read cycles, pipelined
SRAM output data is temporarily stored by the edge-triggered
output register during the access cycle and then released to the
output drivers at the next rising edge of clock.
The GS882Z18/36B is implemented with GSI's high
performance CMOS technology and is available in JEDEC-
standard 119-bump BGA and 165-bump FPBGA packages.
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
t
KQ
tCycle
2.5
4.0
2.7
4.4
3.0
5.0
3.4
6.0
3.8
6.7
4.0
7.5
ns
ns
3.3 V
Curr
(x18)
Curr
(x32/x36)
280
330
255
300
230
270
200
230
185
215
165
190
mA
mA
2.5 V
Curr
(x18)
Curr
(x32/x36)
275
320
250
295
230
265
195
225
180
210
165
185
mA
mA
Flow
Through
2-1-1-1
t
KQ
tCycle
5.5
5.5
6.0
6.0
6.5
6.5
7.0
7.0
7.5
7.5
8.5
8.5
ns
ns
3.3 V
Curr
(x18)
Curr
(x32/x36)
175
200
165
190
160
180
150
170
145
165
135
150
mA
mA
2.5 V
Curr
(x18)
Curr
(x32/x36)
175
200
165
190
160
180
150
170
145
165
135
150
mA
mA
ABCDEF
RWRWRW
Q
A
D
B
Q
C
D
D
Q
E
Q
A
D
B
Q
C
D
D
Q
E
Clock
Address
Read/Write
Flow Through
Data I/O
Pipelined
Data I/O
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Rev: 1.00b 12/2002 2/33 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882Z18/36BB/D-250/225/200/166/150/133
GS882Z36B Pad Out
119 Bump BGA
Top View (Package B)
1234567
A V
DDQ
A
6
A
7
NC A
8
A
9
V
DDQ
B NC E
2
A
4
ADV A
15
E
3
NC
C NC A
5
A
3
V
DD
A
14
A
16
NC
D DQ
C4
DQ
C9
V
SS
ZQ V
SS
DQ
B9
DQ
B4
E DQ
C3
DQ
C8
V
SS
E
1
V
SS
DQ
B8
DQ
B3
F V
DDQ
DQ
C7
V
SS
G V
SS
DQ
B7
V
DDQ
G
DQ
C2
DQ
C6
B
C
A
17
B
B
DQ
B6
DQ
B2
H DQ
C1
DQ
C5
V
SS
W V
SS
DQ
B5
DQ
B1
J
V
DDQ
V
DD
NC V
DD
NC V
DD
V
DDQ
K DQ
D1
DQ
D5
V
SS
CK V
SS
DQ
A5
DQ
A1
L DQ
D2
DQ
D6
B
D
NC B
A
DQ
A6
DQ
A2
M V
DDQ
DQ
D7
V
SS
CKE V
SS
DQ
A7
V
DDQ
N DQ
D3
DQ
D8
V
SS
A
1
V
SS
DQ
A8
DQ
A3
P DQ
D4
DQ
D9
V
SS
A
0
V
SS
DQ
A9
DQ
A4
R
NC A
2
LBO V
DD
FT A
13
PE
T
NC NC A
10
A
11
A
12
NC ZZ
U V
DDQ
TMS TDI TCK TDO NC V
DDQ
Rev: 1.00b 12/2002 3/33 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882Z18/36BB/D-250/225/200/166/150/133
GS882Z18B Pad Out
119 Bump BGA
Top View (Package B)
1234567
A V
DDQ
A
6
A
7
NC A
8
A
9
V
DDQ
B
NC E
2
A
4
ADV A
15
E
3
NC
C
NC A
5
A
3
V
DD
A
14
A
16
NC
D DQ
B1
NC V
SS
ZQ V
SS
DQ
A9
NC
E NC DQ
B2
V
SS
E
1
V
SS
NC DQ
A8
F V
DDQ
NC V
SS
G V
SS
DQ
A7
V
DDQ
G
NC DQ
B3
B
B
A
17
NC NC DQ
A6
H
DQ
B4
NC V
SS
W V
SS
DQ
A5
NC
J V
DDQ
V
DD
NC V
DD
NC V
DD
V
DDQ
K NC DQ
B5
V
SS
CK V
SS
NC DQ
A4
L
DQ
B6
NC NC NC B
A
DQ
A3
NC
M V
DDQ
DQ
B7
V
SS
CKE V
SS
NC V
DDQ
N
DQ
B8
NC V
SS
A
1
V
SS
DQ
A2
NC
P NC DQ
B9
V
SS
A
0
V
SS
NC DQ
A1
R NC A
2
LBO V
DD
FT A
13
PE
T
NC A
10
A
11
NC A
12
A
18
ZZ
U
V
DDQ
TMS TDI TCK TDO NC V
DDQ
Rev: 1.00b 12/2002 4/33 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882Z18/36BB/D-250/225/200/166/150/133
165 Bump BGA—x18 Commom I/O—Top View (Package D)
123456 7891011
ANC
AE1BB NC E3
CKE
ADV A17 A
A18
A
BNC
AE2NCBACK W G NC ANC B
CNCNC
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC DQA C
DNC
DQB V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC DQA D
ENC
DQB V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC DQA E
FNC
DQB V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC DQA F
GNC
DQB V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC DQA G
HFT
MCH NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC ZQ ZZ H
J
DQB NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA NC J
K
DQB NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA NC K
L
DQB NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA NC L
M
DQB NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA NC M
N
DQB DNU V
DDQ
V
SS
NC NC NC V
SS
V
DDQ
NC NC N
PNCNC
A ATDIA1 TDO A A ANC P
RLBO
NC A ATMSA0 TCK A A A AR
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.00b 12/2002 5/33 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882Z18/36BB/D-250/225/200/166/150/133
165 Bump BGA—x36 Common I/O—Top View (Package D)
123456 7891011
ANC
AE1BC BB E3 CKE ADV A17 A
NC
A
BNC
AE2BDBA CK W G NC ANC B
C
DQC NC V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC DQB C
D
DQC DQC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB DQB D
E
DQC DQC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB DQB E
F
DQC DQC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB DQB F
G
DQC DQC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB DQB G
HFT
MCH NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC ZQ ZZ H
J
DQD DQD V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA DQA J
K
DQD DQD V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA DQA K
L
DQD DQD V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA DQA L
M
DQD DQD V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA DQA M
N
DQD DNU V
DDQ
V
SS
NC NC NC V
SS
V
DDQ
NC DQA N
PNCNC
A ATDIA1 TDO A A ANC P
RLBO
NC A ATMSA0 TCK A A A AR
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.00b 12/2002 6/33 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882Z18/36BB/D-250/225/200/166/150/133
GS882Z18/36B BGA Pin Description
Symbol Type Description
A
0
, A
1
I Address field LSBs and Address Counter Preset Inputs
An I Address Inputs
A
17,
A
18
I Address Inputs
DQ
A1
–DQ
A9
DQ
B1
–DQ
B9
DQ
C1
–DQ
C9
DQ
D1
–DQ
D9
I/O Data Input and Output pins
B
A
, B
B
, B
C
, B
D
I Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D
I/Os; active low
NC No Connect
CK I Clock Input Signal; active high
CKE
I Clock Enable; active low
W
I Write Enable; active low
E
1
I Chip Enable; active low
E
3 I Chip Enable; active low
E
2 I Chip Enable; active high
G
I Output Enable; active low
ADV I Burst address counter advance enable; active high
ZZ I Sleep mode control; active high
FT
I Flow Through or Pipeline mode; active low
LBO
I Linear Burst Order mode; active low
ZQ I
FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low
Drive])
TMS
I Scan Test Mode Select
TDI
I Scan Test Data In
TDO
O Scan Test Data Out
TCK
I Scan Test Clock
MCH
Must Connect High
DNU
—Do Not Use
V
DD
I Core power supply
V
SS
I I/O and Core Ground
V
DDQ
I Output driver power supply
Rev: 1.00b 12/2002 7/33 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882Z18/36BB/D-250/225/200/166/150/133
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load
pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E
1
, E
2,
and E
3
). Deassertion of any one of the Enable
inputs will deactivate the device.
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE
is asserted low, all three
chip enables (E
1
, E
2,
and E
3
) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.
The Byte Write Enable inputs (B
A
, B
B
, B
C,
and B
D
) determine which bytes will be written. All or none may be activated. A write
cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Function W
B
A
B
B
B
C
B
D
Read H X X X X
Write Byte “a” L L H H H
Write Byte “b” L H L H H
Write Byte “c” L H H L H
Write Byte “d” L H H H L
Write all Bytes L L L L L
Write Abort/NOP L H H H H
Rev: 1.00b 12/2002 8/33 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882Z18/36BB/D-250/225/200/166/150/133
Synchronous Truth Table
Operation Type Address E
1
E
2
E
3
ZZ ADV W Bx G CKE CK DQ Notes
Deselect Cycle, Power Down D None H X X L L X X X L L-H High-Z
Deselect Cycle, Power Down D None X X H L L X X X L L-H High-Z
Deselect Cycle, Power Down D None X L X L L X X X L L-H High-Z
Deselect Cycle, Continue D None X X X L H X X X L L-H High-Z 1
Read Cycle, Begin Burst R External L H L L L H X L L L-H Q
Read Cycle, Continue Burst B Next X X X L H X X L L L-H Q 1,10
NOP/Read, Begin Burst R External L H L L L H X H L L-H High-Z 2
Dummy Read, Continue Burst B Next X X X L H X X H L L-H High-Z 1,2,10
Write Cycle, Begin Burst W External L H L L L L L X L L-H D 3
Write Cycle, Continue Burst B Next X X X L H X L X L L-H D 1,3,10
NOP/Write Abort, Begin Burst W None L H L L L L H X L L-H High-Z 2,3
Write Abort, Continue Burst B Next X X X L H X H X L L-H High-Z 1,2,3,10
Clock Edge Ignore, Stall Current X X X L X X X X H L-H - 4
Sleep Mode None X X X H X X X X X X High-Z
Notes:
1. Continue Burst cycles, whether Read or Write, use the same control inputs. A Deselect continue cycle can only be entered into if a
Deselect cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin
is sampled low but no Byte Write pins are active, so no write operation is performed.
3. G
can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write
cycles.
4. If CKE
High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx
= High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals
are Low
6. All inputs, except G
and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE
high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.00b 12/2002 9/33 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882Z18/36BB/D-250/225/200/166/150/133
Deselect
New Read New Write
Burst Read Burst Write
W
R
B
R
B
W
DD
B
B
W
R
D
B
W
R
D
D
Pipelined and Flow Through Read Write Control State Diagram
Current State (n)
Next State (n+1)
Transition
ƒ
Input Command Code
Key Notes
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Synchronous Truth Table.
Clock (CK)
Command
Current State Next State
ƒ
n n+1 n+2 n+3
ƒƒƒ
Current State and Next State Definition for Pipelined and Flow through Read/Write Control State Diagram
W
R
Rev: 1.00b 12/2002 10/33 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882Z18/36BB/D-250/225/200/166/150/133
Intermediate Intermediate
Intermediate
Intermediate
Intermediate
Intermediate
High Z
(Data In)
Data Out
(Q Valid)
High Z
B
W
B
R
B
D
R
W
R
W
D
D
Pipeline Mode Data I/O State Diagram
Current State (n) Next State (n+2)
Transition
ƒ
Input Command Code
Key
Transition
Intermediate State (N+1)
Notes
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Clock (CK)
Command
Current State
Intermediate
ƒ
n n+1 n+2 n+3
ƒƒƒ
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Next State
State
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