GSI GS88219AB-150, GS88219AB-133I, GS88219AB-133, GS88219AB-250I, GS88219AB-250 Datasheet

Revision: 5/17/02

GS88219/37AB

Datasheet Errata

Base datasheet:

GS88219/37AB, Rev.1.00, 3/2002

Product(s) covered in this supplement:

GS88219/37AB-250/225/200/166/150/133

Product specification(s) addressed by this supplement:

Bump R5

Note: The specifications cited in the base datasheet for the products addressed by this errata remain in force except where superseded by the information in this errata.

1/5

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Revision: 5/17/02

GS88219/37AB

Datasheet Errata

GS88237A Pad Out

119 Bump BGA—Top View

1

2

3

4

5

6

7

A

VDDQ

A6

A7

A8

A9

VDDQ

ADSP

B

NC

NC

A4

A15

A17

NC

ADSC

C

NC

A5

A3

VDD

A14

A16

NC

D

DQC4

DQC9

VSS

ZQ

VSS

DQB9

DQB4

E

DQC3

DQC8

VSS

1

VSS

DQB8

DQB3

E

F

VDDQ

DQC7

VSS

VSS

DQB7

VDDQ

G

G

DQC2

DQC6

C

B

DQB6

DQB2

B

ADV

B

H

DQC1

DQC5

VSS

VSS

DQB5

DQB1

GW

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

DQD1

DQD5

VSS

CK

VSS

DQA5

DQA1

L

DQD2

DQD6

D

SCD

A

DQA6

DQA2

B

B

M

VDDQ

DQD7

VSS

VSS

DQA7

VDDQ

BW

N

DQD3

DQD8

VSS

A1

VSS

DQA8

DQA3

P

DQD4

DQD9

VSS

A0

VSS

DQA9

DQA4

R

VDDQ/

A13

NC

A2

LBO

VDD

PE

DNU

T

NC

NC

A10

A11

A12

NC

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

2/5

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Revision: 5/17/02

GS88219/37AB

Datasheet Errata

GS88219A Pad Out

119 Bump BGA—Top View

1

2

3

4

5

6

7

A

VDDQ

A6

A7

A8

A9

VDDQ

ADSP

B

NC

NC

A4

A15

A17

NC

ADSC

C

NC

A5

A3

VDD

A14

A16

NC

D

DQB1

NC

VSS

ZQ

VSS

DQA9

NC

E

NC

DQB2

VSS

1

VSS

NC

DQA8

E

F

VDDQ

NC

VSS

VSS

DQA7

VDDQ

G

G

NC

DQB3

B

NC

NC

DQA6

B

ADV

H

DQB4

NC

VSS

VSS

DQA5

NC

GW

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

NC

DQB5

VSS

CK

VSS

NC

DQA4

L

DQB6

NC

NC

SCD

A

DQA3

NC

B

M

VDDQ

DQB7

VSS

VSS

NC

VDDQ

BW

N

DQB8

NC

VSS

A1

VSS

DQA2

NC

P

NC

DQB9

VSS

A0

VSS

NC

DQA1

R

VDDQ/

NC

A2

LBO

VDD

A13

PE

DNU

T

NC

A10

A11

NC

A12

A18

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

3/5

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Revision: 5/17/02

GS88219/37AB

Datasheet Errata

GS88219/37A BGA Pin Description

Pin Location

Symbol

Type

Description

P4, N4

A0, A1

I

Address field LSBs and Address Counter Preset Inputs

A2, A3, A5, A6, B3, B5, C2, C3, C5,

An

I

Address Inputs

C6, R2, R6, T3, T5

T4

An

I

Address Input (x36 Versions)

T2, T6

NC

—

No Connect (x36 Versions)

T2, T6

An

I

Address Input (x18 Version)

K7, L7, N7, P7, K6, L6, M6, N6, P6

DQA1–DQA9

H7, G7, E7, D7, H6, G6, F6, E6, D6

DQB1–DQB9

I/O

Data Input and Output pins (x36 Versions)

H1, G1, E1, D1, H2, G2, F2, E2, D2

DQC1–DQC9

K1, L1, N1, P1, K2, L2, M2, N2, P2

DQD1–DQD9

L5, G5, G3, L3

A,

B,

C,

D

I

Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low (x36 Version)

B

B

B

B

P7, N6, L6, K7, H6, G7, F6, E7, D6

DQA1–DQA9

I/O

Data Input and Output pins (x18 Version)

D1, E2, G2, H1, K2, L1, M2, N1, P2

DQB1–DQB9

L5, G3

A,

B

I

Byte Write Enable for DQA, DQB I/Os; active low (x18 Version)

B

B

B1, B2, C1, R1, T1, U6, B7, C7, J3,

NC

—

No Connect

J5

P6, N7, M6, L7, K6, H7, G6, E6, D7,

D2, E1, F2, G1, H2, K1, L2, N2, P1,

NC

—

No Connect (x18 Version)

G5, L3, T4

K4

CK

I

Clock Input Signal; active high

M4

I

Byte Write—Writes all enabled bytes; active low

BW

H4

I

Global Write Enable—Writes all bytes; active low

GW

E4

1

I

Chip Enable; active low

E

F4

I

Output Enable; active low

G

G4

I

Burst address counter advance enable; active low

ADV

A4, B4

I

Address Strobe (Processor, Cache Controller); active low

ADSP,

ADSC

T7

ZZ

I

Sleep Mode control; active high

R3

I

Linear Burst Order mode; active low

LBO

L4

SCD

I

Single Cycle Deselect/Dual Cycle Deselect Mode Control

R7

I

Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode)

PE

D4

ZQ

I

FLXDrive Output Impedance Control

(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

U2

TMS

I

Scan Test Mode Select

4/5

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Revision: 5/17/02

GS88219/37AB

Datasheet Errata

GS88219/37A BGA Pin Description

	Pin Location	Symbol	Type	Description
	U3	TDI	I	Scan Test Data In
	U5	TDO	O	Scan Test Data Out
	U4	TCK	I	Scan Test Clock
	J2, C4, J4, R4, J6	VDD	I	Core power supply
	D3, E3, F3, H3, K3, M3, N3, P3, D5,	VSS	I	I/O and Core Ground
	E5, F5, H5, K5, M5, N5, P5
	A1, F1, J1, M1, U1, A7, F7, J7, M7,	VDDQ	I	Output driver power supply
	U7
	R5	VDDQ/DNU	—	VDDQ or VDD (must be tied high)
				or
				Do Not Use (must be left floating)

5/5

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88219/37AB-250/225/200/166/150/133

119-Bump BGA

Commercial Temp

Industrial Temp

512K x 18, 256K x 36

9Mb SCD/DCD Sync Burst SRAMs

250 MHz–133MHz

2.5V or 3.3 V VDD

2.5V or 3.3 V I/O

Features

•Single/Dual Cycle Deselect selectable

•IEEE 1149.1 JTAG-compatible Boundary Scan

•ZQ mode pin for user-selectable high/low output drive

•2.5 V or 3.3 V +10%/–10% core power supply

•2.5 V or 3.3 V I/O supply

•LBO pin for Linear or Interleaved Burst mode

•Internal input resistors on mode pins allow floating mode pins

•Default to SCD x18/x36 Interleaved Pipeline mode

•Byte Write (BW) and/or Global Write (GW) operation

•Internal self-timed write cycle

•Automatic power-down for portable applications

•JEDEC-standard 119-bump BGA package

			-250	-225	-200	-166 -150 -133 Unit
	Pipeline	tKQ	2.0	2.2	2.5	2.9	3.3	3.5	ns
	3-1-1-1	tCycle	4.0	4.4	5.0	6.0	6.7	7.5	ns
	3.3 V	Curr (x18)	280	255	230	200	185	165	mA
		Curr (x36)	330	300	270	230	215	190	mA
	2.5 V	Curr (x18)	275	250	230	195	180	165	mA
		Curr (x36)	320	295	265	225	210	185	mA

Functional Description

Applications

The GS88219/37AB is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.

captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS88219/37AB operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible.

Controls

Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge- triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.

SCD and DCD Pipelined Reads

The GS88219/37AB is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been

Rev: 1.00 3/2002

1/36

© 2002, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88219/37AB-250/225/200/166/150/133

GS88237A Pad Out

119 Bump BGA—Top View

1

2

3

4

5

6

7

A

VDDQ

A6

A7

ADSP

A8

A9

VDDQ

B

NC

NC

A4

ADSC

A15

A17

NC

C

NC

A5

A3

VDD

A14

A16

NC

D

DQC4

DQC9

VSS

ZQ

VSS

DQB9

DQB4

E

DQC3

DQC8

VSS

E1

VSS

DQB8

DQB3

F

VDDQ

DQC7

VSS

G

VSS

DQB7

VDDQ

G

DQC2

DQC6

BC

ADV

BB

DQB6

DQB2

H

DQC1

DQC5

VSS

GW

VSS

DQB5

DQB1

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

DQD1

DQD5

VSS

CK

VSS

DQA5

DQA1

L

DQD2

DQD6

BD

SCD

BA

DQA6

DQA2

M

VDDQ

DQD7

VSS

BW

VSS

DQA7

VDDQ

N

DQD3

DQD8

VSS

A1

VSS

DQA8

DQA3

P

DQD4

DQD9

VSS

A0

VSS

DQA9

DQA4

R

NC

A2

LBO

VDD

NC

A13

PE

T

NC

NC

A10

A11

A12

NC

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

Rev: 1.00 3/2002

2/36

© 2002, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88219/37AB-250/225/200/166/150/133

GS88219A Pad Out

119 Bump BGA—Top View

1

2

3

4

5

6

7

A

VDDQ

A6

A7

ADSP

A8

A9

VDDQ

B

NC

NC

A4

ADSC

A15

A17

NC

C

NC

A5

A3

VDD

A14

A16

NC

D

DQB1

NC

VSS

ZQ

VSS

DQA9

NC

E

NC

DQB2

VSS

E1

VSS

NC

DQA8

F

VDDQ

NC

VSS

G

VSS

DQA7

VDDQ

G

NC

DQB3

BB

ADV

NC

NC

DQA6

H

DQB4

NC

VSS

GW

VSS

DQA5

NC

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

NC

DQB5

VSS

CK

VSS

NC

DQA4

L

DQB6

NC

NC

SCD

BA

DQA3

NC

M

VDDQ

DQB7

VSS

BW

VSS

NC

VDDQ

N

DQB8

NC

VSS

A1

VSS

DQA2

NC

P

NC

DQB9

VSS

A0

VSS

NC

DQA1

R

NC

A2

LBO

VDD

NC

A13

PE

T

NC

A10

A11

NC

A12

A18

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

BPR1999.05.18

Rev: 1.00 3/2002

3/36

© 2002, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

									Preliminary
									GS88219/37AB-250/225/200/166/150/133
	GS88219/37A BGA Pin Description
	Pin Location				Symbol			Type	Description
			P4, N4		A0, A1			I	Address field LSBs and Address Counter Preset Inputs
	A2, A3, A5, A6, B3, B5, C2, C3, C5,					An		I	Address Inputs
	C6, R2, R6, T3, T5
			T4			An		I	Address Input (x36 Versions)
			T2, T6			NC		—	No Connect (x36 Versions)
			T2, T6			An		I	Address Input (x18 Version)
	K7, L7, N7, P7, K6, L6, M6, N6, P6				DQA1–DQA9
	H7, G7, E7, D7, H6, G6, F6, E6, D6				DQB1–DQB9			I/O	Data Input and Output pins (x36 Versions)
	H1, G1, E1, D1, H2, G2, F2, E2, D2				DQC1–DQC9
	K1, L1, N1, P1, K2, L2, M2, N2, P2				DQD1–DQD9
	L5, G5, G3, L3			BA, BB, BC, BD				I	Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low (x36 Version)
	P7, N6, L6, K7, H6, G7, F6, E7, D6				DQA1–DQA9			I/O	Data Input and Output pins (x18 Version)
	D1, E2, G2, H1, K2, L1, M2, N1, P2				DQB1–DQB9
			L5, G3		BA, BB			I	Byte Write Enable for DQA, DQB I/Os; active low (x18 Version)
	B1, B2, C1, R1, T1, U6, B7, C7, J3,					NC		—	No Connect
			J5, R5
	P6, N7, M6, L7, K6, H7, G6, E6, D7,
	D2, E1, F2, G1, H2, K1, L2, N2, P1,					NC		—	No Connect (x18 Version)
		G5, L3, T4
			K4			CK		I	Clock Input Signal; active high
			M4		BW			I	Byte Write—Writes all enabled bytes; active low
			H4		GW			I	Global Write Enable—Writes all bytes; active low
			E4			E1		I	Chip Enable; active low
			F4			G		I	Output Enable; active low
			G4		ADV			I	Burst address counter advance enable; active low
			A4, B4	ADSP, ADSC				I	Address Strobe (Processor, Cache Controller); active low
			T7			ZZ		I	Sleep Mode control; active high
			R3		LBO			I	Linear Burst Order mode; active low
			L4		SCD			I	Single Cycle Deselect/Dual Cycle Deselect Mode Control
			R7					I	Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode)
						PE
			D4			ZQ		I	FLXDrive Output Impedance Control
									(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

Rev: 1.00 3/2002

4/36

© 2002, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

						Preliminary
						GS88219/37AB-250/225/200/166/150/133
	GS88219/37A BGA Pin Description
	Pin Location			Symbol	Type	Description
			U2	TMS	I	Scan Test Mode Select
			U3	TDI	I	Scan Test Data In
			U5	TDO	O	Scan Test Data Out
			U4	TCK	I	Scan Test Clock
	J2, C4, J4, R4, J6			VDD	I	Core power supply
	D3, E3, F3, H3, K3, M3, N3, P3, D5,			VSS	I	I/O and Core Ground
	E5, F5, H5, K5, M5, N5, P5
	A1, F1, J1, M1, U1, A7, F7, J7, M7,			VDDQ	I	Output driver power supply
			U7

Rev: 1.00 3/2002

5/36

© 2002, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88219/37AB-250/225/200/166/150/133

GS88219/37A (PE = 0) Block Diagram

	Register
A0–An	D	Q
		A0			A0
		D0		Q0	A1
		A1
		D1		Q1
		Counter				A
		Load
LBO						Memory
ADV
CK						Array
ADSC
ADSP						Q	D
GW		Register				36	36
BW		D	Q
BA
		Register
		D	Q
BB
						4		4
		Register
		D	Q
BC						Register Q D	Register D Q		D Q
		Register						Register
		D	Q
BD
		Register					36
		D	Q			36
									36
E1		Register
		D	Q
						36		4	32
		Register						Parity
								Encode
		D	Q
									4
								Parity
1								Compare
G						36
ZZ		Power Down			SCD	DQx1–DQx9		NC	NC
		Control

Note: Only x36 version shown for simplicity.

Rev: 1.00 3/2002

6/36

© 2002, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88219/37A (PE = 1) x32 Mode Block Diagram

Register

A0–An

D Q

A0

A0

D0

Q0

A1

A1

D1

Q1

Counter

Load

LBO

ADV

CK

ADSC

ADSP

Register

GW

BW

D

Q

BA

Register

D

Q

BB

Register

D

Q

BC

Register

D

Q

BD

Register

D

Q

Register

E1

D

Q

Register

1

D

Q

G

SCD

ZZ

Power Down

Control

Note: Only x36 version shown for simplicity.

Rev: 1.00 3/2002

7/36

Preliminary

GS88219/37AB-250/225/200/166/150/133

A

Memory

	Array
Q	D
36	36
	4

Parity

Encode

32

4

Register Q D

Register D Q

36

32

Register

36

D

Q

32

4

32

Register

D

Q

Parity

Encode

4

Parity

Compare

32

DQx1–DQx9

NC

NC

© 2002, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

									Preliminary
								GS88219/37AB-250/225/200/166/150/133
	Mode Pin Functions
	Mode Name				Pin		State	Function
				Name
							L	Linear Burst
	Burst Order Control			LBO
							H	Interleaved Burst
	Power Down Control				ZZ		L or NC	Active
							H	Standby, IDD = ISB
	Single/Dual Cycle Deselect Control			SCD			L	Dual Cycle Deselect
							H or NC	Single Cycle Deselect
	FLXDrive Output Impedance Control				ZQ		L	High Drive (Low Impedance)
							H or NC	Low Drive (High Impedance)

Note:

Thereis a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above tables.

Enable / Disable Parity I/O Pins

This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16, x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Grounding PE deactivates the 9th I/O of each byte.

Burst Counter Sequences

Linear Burst Sequence

	A[1:0]	A[1:0]	A[1:0]	A[1:0]
1st address	00	01	10	11
2nd address	01	10	11	00
3rd address	10	11	00	01
4th address	11	00	01	10

Note: The burst counter wraps to initial state on the 5th clock.

Interleaved Burst Sequence

	A[1:0]	A[1:0]	A[1:0]	A[1:0]
1st address	00	01	10	11
2nd address	01	00	11	10
3rd address	10	11	00	01
4th address	11	10	01	00

Note: The burst counter wraps to initial state on the 5th clock.

BPR 1999.05.18

Rev: 1.00 3/2002

8/36

© 2002, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.