Preliminary
GS88037BT-333/300/275/250/225/200
100-Pin TQFP
Commercial Temp
Industrial Temp
256K x 36
9Mb Sync Burst SRAM
333MHz–200 MHz
2.5V or 3.3 V VDD
2.5V or 3.3 V I/O
Features
•Single Cycle Deselect (SCD) operation
•2.5 V or 3.3 V +10%/–10% core power supply
•2.5 V or 3.3 V I/O supply
•LBO pin for Linear or Interleaved Burst mode
•Internal input resistors on mode pins allow floating mode pins
•Default to Interleaved Pipeline mode
•Byte Write (BW) and/or Global Write (GW) operation
•Internal self-timed write cycle
•Automatic power-down for portable applications
•JEDEC-standard 100-lead TQFP package
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-333 |
-300 |
-275 |
-250 -225 -200 Unit |
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Pipeline |
tKQ |
2.0 |
2.2 |
2.3 |
2.3 |
2.5 |
2.7 |
ns |
3-1-1-1 |
tCycle |
3.0 |
3.3 |
3.6 |
4.0 |
4.4 |
5.0 |
ns |
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3.3 V |
Curr (x36) |
435 |
395 |
360 |
330 |
300 |
270 |
mA |
2.5 V |
Curr (x36) |
435 |
395 |
360 |
330 |
300 |
270 |
mA |
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Functional Description
Applications
The GS88037BT is a 9,437,184-bit (8,388,608-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.
SCD Pipelined Reads
The GS88037BT is a SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS88037BT operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the
internal circuits and are 3.3 V and 2.5 V compatible.
Rev: 1.00b 12/2002 |
1/19 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88037BT-333/300/275/250/225/200
GS88037B 100-Pin TQFP Pinout
DQC9
DQC8
DQC7
VDDQ
VSS
DQC6
DQC5
DQC4
DQC3
VSS
VDDQ
DQC2
DQC1
VDDQ/DNU
VDD
NC
VSS
DQD1
DQD2
VDDQ
VSS
DQD3
DQD4
DQD5
DQD6
VSS
VDDQ
DQD7
DQD8
DQD9
|
A6 |
A7 |
E1 |
E2 |
BD BC BB BA E3 |
V |
V |
CK GW BW |
G |
ADSC |
ADSP |
ADV A8 |
A9 |
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DD |
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SS |
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100 |
99 |
98 |
97 |
96 |
95 |
94 |
93 |
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92 |
91 |
90 |
89 |
88 |
87 |
86 |
85 |
84 |
83 |
82 |
81 |
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1 |
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80 |
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2 |
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79 |
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3 |
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78 |
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4 |
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77 |
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5 |
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76 |
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6 |
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75 |
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7 |
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74 |
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8 |
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73 |
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9 |
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256K x 36 |
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72 |
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10 |
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71 |
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Top View |
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11 |
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70 |
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12 |
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69 |
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13 |
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68 |
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14 |
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67 |
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15 |
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66 |
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16 |
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65 |
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17 |
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64 |
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18 |
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63 |
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19 |
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62 |
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20 |
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61 |
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21 |
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60 |
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22 |
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59 |
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23 |
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58 |
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24 |
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57 |
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25 |
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56 |
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26 |
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55 |
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27 |
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54 |
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28 |
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53 |
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29 |
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52 |
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30 |
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51 |
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31 |
32 |
33 |
34 |
35 |
36 |
37 |
38 |
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39 |
40 |
41 |
42 |
43 |
44 |
45 |
46 |
47 |
48 |
49 |
50 |
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LBO A5 |
A4 |
A3 |
A2 |
A1 |
A0 |
NC NC |
|
SS |
|
DD |
NC A17 |
A10 |
A11 |
A12 |
A13 |
A14 |
A15 |
A16 |
|
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|||||||||||||||||||||||||||||||||||||||
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||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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V |
V |
|
|
DQB9
DQB8
DQB7
VDDQ
VSS
DQB6
DQB5
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
DQA5
DQA6
VSS
VDDQ
DQA7
DQA8
DQA9
Rev: 1.00b 12/2002 |
2/19 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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Preliminary |
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GS88037BT-333/300/275/250/225/200 |
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TQFP Pin Description |
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|||||||||||||||||
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Symbol |
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Type |
Description |
||||||||||||||||||
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||||||||||||||||
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A0, A1 |
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I |
Address field LSBs and Address Counter preset Inputs |
||||||||||||||||
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A2–A17 |
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I |
Address Inputs |
|||||||||||||||||
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A18 |
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I |
Address Input |
||||||||||
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|||||||||||||||
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DQA1–DQA9 |
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|||||||||||||||
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DQB1–DQB9 |
|
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I/O |
Data Input and Output pins |
|||||||||||||||||
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DQC1–DQC9 |
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|||||||||||||||||||
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||||||||||||||||
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DQD1–DQD98 |
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|||||||||||||||
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NC |
|
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— |
No Connect |
||||||||||
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I |
Byte Write—Writes all enabled bytes; active low |
||
BW |
|
||||||||||||||||||||||
|
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A, |
|
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B |
|
|
I |
Byte Write Enable for DQA, DQB Data I/Os; active low |
|||||||
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B |
B |
|
||||||||||||||||||
|
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C, |
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D |
|
|
I |
Byte Write Enable for DQC, DQD Data I/Os; active low |
||||||||
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B |
B |
|
||||||||||||||||||
|
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CK |
|
|
I |
Clock Input Signal; active high |
||||||||||
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||||||
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I |
Global Write Enable—Writes all bytes; active low |
|||
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|
GW |
|
||||||||||||||||
|
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1, |
|
|
3 |
|
|
|
I |
Chip Enable; active low |
|||||
|
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|
E |
E |
|
||||||||||||||||||
|
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|
E2 |
|
|
I |
Chip Enable; active high |
|||||||||
|
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||||
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|
I |
Output Enable; active low |
||||
|
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G |
|
||||||||||||
|
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|
I |
Burst address counter advance enable; active low |
||
|
|
|
|
|
ADV |
|
|||||||||||||||||
|
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|
I |
Address Strobe (Processor, Cache Controller); active low |
||
ADSP, |
ADSC |
|
|||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
ZZ |
|
|
I |
Sleep Mode control; active high |
|||||||||
|
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|||||||||||||
|
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|
I |
Linear Burst Order mode; active low |
||||
|
|
|
|
|
LBO |
|
|||||||||||||||||
|
|
|
|
|
VDD |
|
|
I |
Core power supply |
||||||||||||||
|
|
|
|
|
VSS |
|
|
I |
I/O and Core Ground |
||||||||||||||
|
|
|
|
VDDQ |
|
|
I |
Output driver power supply |
|||||||||||||||
|
|
VDDQ/DNU |
|
|
— |
VDDQ or VDD (must be tied high) |
|||||||||||||||||
|
|
|
|
or |
|||||||||||||||||||
|
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|
|
Do Not Use (must be left floating) |
|
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|
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|
|
|
Rev: 1.00b 12/2002 |
3/19 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
|
|
|
|
|
|
|
Preliminary |
|
|
|
|
|
|
GS88037BT-333/300/275/250/225/200 |
|
GS88037B Block Diagram |
|
|
|
|
|
|
|
A0–An |
Register |
|
|
|
|
|
|
D |
Q |
|
|
|
A0 |
|
|
|
|
A0 |
|
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|
|
|
D0 |
|
Q0 |
|
A1 |
|
|
|
A1 |
|
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|
|
|
|
Q1 |
|
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|
|
D1 |
|
|
|
|
|
|
|
Counter |
|
|
A |
|
|
|
|
Load |
|
|
|
|
|
LBO |
|
|
|
|
|
Memory |
|
ADV |
|
|
|
|
|
|
|
CK |
|
|
|
|
|
Array |
|
ADSC |
|
|
|
|
|
|
|
ADSP |
|
Register |
|
|
Q |
D |
|
GW |
|
|
|
|
|
||
BW |
|
D |
Q |
|
|
|
|
|
|
|
|
|
|
|
|
BA |
|
|
|
|
|
|
|
|
|
Register |
|
|
36 |
36 |
|
|
|
D |
Q |
|
|
||
|
|
|
|
|
|
||
BB |
|
|
|
|
|
4 |
|
|
|
Register |
|
|
|
|
|
|
|
D |
Q |
|
|
|
|
BC |
|
|
|
|
|
Register Q D |
Register D Q |
|
|
Register |
|
|
|||
|
|
D |
Q |
|
|
|
|
BD |
|
|
|
|
|
|
|
|
|
Register |
|
|
|
|
|
|
|
D |
Q |
|
|
|
|
E1 |
|
Register |
|
|
|
|
|
|
D |
Q |
|
|
|
|
|
E2 |
|
|
|
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|
|
E3 |
|
|
|
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|
|
Register |
|
|
|
|
|
|
|
D |
Q |
|
|
|
|
1 |
|
|
|
|
|
|
|
G |
|
|
|
|
|
|
|
ZZ |
|
Power Down |
|
|
1 |
DQx1–DQx9 |
|
|
Control |
|
|
|
|
||
|
|
|
|
|
|
|
Note: Only x36 version shown for simplicity.
Rev: 1.00b 12/2002 |
4/19 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88037BT-333/300/275/250/225/200
Mode Pin Functions
Mode Name |
|
Pin |
State |
Function |
||
Name |
||||||
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
L |
Linear Burst |
|
Burst Order Control |
LBO |
|||||
H |
Interleaved Burst |
|||||
|
|
|
|
|||
|
|
|
|
|
|
|
Power Down Control |
|
ZZ |
L or NC |
Active |
||
|
|
|
||||
|
H |
Standby, IDD = ISB |
||||
|
|
|
|
Note:
Thereis a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
|
A[1:0] |
A[1:0] |
A[1:0] |
A[1:0] |
|
|
|
|
|
|
|
|
|
|
1st address |
00 |
01 |
10 |
11 |
|
|
|
|
|
2nd address |
01 |
10 |
11 |
00 |
|
|
|
|
|
3rd address |
10 |
11 |
00 |
01 |
|
|
|
|
|
4th address |
11 |
00 |
01 |
10 |
|
|
|
|
|
Note: The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
|
A[1:0] |
A[1:0] |
A[1:0] |
A[1:0] |
|
|
|
|
|
|
|
|
|
|
1st address |
00 |
01 |
10 |
11 |
|
|
|
|
|
2nd address |
01 |
00 |
11 |
10 |
|
|
|
|
|
3rd address |
10 |
11 |
00 |
01 |
|
|
|
|
|
4th address |
11 |
10 |
01 |
00 |
|
|
|
|
|
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Byte Write Truth Table
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Function |
|
GW |
|
|
BW |
BA |
BB |
|
BC |
|
BD |
Notes |
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
Read |
|
H |
|
|
H |
|
X |
|
X |
|
X |
|
X |
1 |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
Read |
|
H |
|
|
L |
|
H |
|
H |
|
H |
|
H |
1 |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
Write byte a |
|
H |
|
|
L |
|
L |
|
H |
|
H |
|
H |
2, 3 |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
Write byte b |
|
H |
|
|
L |
|
H |
|
L |
|
H |
|
H |
2, 3 |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
Write byte c |
|
H |
|
|
L |
|
H |
|
H |
|
L |
|
H |
2, 3, 4 |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
Write byte d |
|
H |
|
|
L |
|
H |
|
H |
|
H |
|
L |
2, 3, 4 |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
Write all bytes |
|
H |
|
|
L |
|
L |
|
L |
|
L |
|
L |
2, 3, 4 |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
Write all bytes |
|
L |
|
|
X |
|
X |
|
X |
|
X |
|
X |
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Notes:
1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2.Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4.Bytes “C” and “D” are only available on the x32 and x36 versions.
Rev: 1.00b 12/2002 |
5/19 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88037BT-333/300/275/250/225/200
Synchronous Truth Table
|
Address |
State |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Diagram |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DQ4 |
|
Operation |
|
E1 |
|
ADSP |
|
ADSC |
|
ADV |
|
|
|
|
|||||||
|
E2 |
|
|
|
|
W3 |
|||||||||||||
Used |
|
|
|
|
|
||||||||||||||
|
Key5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
Deselect Cycle, Power Down |
None |
X |
|
H |
X |
|
X |
|
L |
|
|
X |
|
|
X |
High-Z |
|||
Deselect Cycle, Power Down |
None |
X |
|
L |
F |
|
L |
|
X |
|
|
X |
|
|
X |
High-Z |
|||
Deselect Cycle, Power Down |
None |
X |
|
L |
F |
|
H |
|
L |
|
|
X |
|
|
X |
High-Z |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Read Cycle, Begin Burst |
External |
R |
|
L |
T |
|
L |
|
X |
|
|
X |
|
|
X |
Q |
|||
Read Cycle, Begin Burst |
External |
R |
|
L |
T |
|
H |
|
L |
|
|
X |
|
|
F |
Q |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
Write Cycle, Begin Burst |
External |
W |
|
L |
T |
|
H |
|
L |
|
|
X |
|
|
T |
D |
|||
|
|
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Read Cycle, Continue Burst |
Next |
CR |
|
X |
X |
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H |
|
H |
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L |
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F |
Q |
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Read Cycle, Continue Burst |
Next |
CR |
|
H |
X |
|
X |
|
H |
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L |
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F |
Q |
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Write Cycle, Continue Burst |
Next |
CW |
|
X |
X |
|
H |
|
H |
|
|
L |
|
|
T |
D |
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Write Cycle, Continue Burst |
Next |
CW |
|
H |
X |
|
X |
|
H |
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|
L |
|
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T |
D |
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Read Cycle, Suspend Burst |
Current |
|
|
X |
X |
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H |
|
H |
|
|
H |
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F |
Q |
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Read Cycle, Suspend Burst |
Current |
|
|
H |
X |
|
X |
|
H |
|
|
H |
|
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F |
Q |
|||
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Write Cycle, Suspend Burst |
Current |
|
|
X |
X |
|
H |
|
H |
|
|
H |
|
|
T |
D |
|||
Write Cycle, Suspend Burst |
Current |
|
|
H |
X |
|
X |
|
H |
|
|
H |
|
|
T |
D |
|||
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Notes:
1.X = Don’t Care, H = High, L = Low
2.E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1
3.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above).
5.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity.
6.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.00b 12/2002 |
6/19 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.