GS841E18AT/B-166/150/133/100
TQFP, BGA
Commercial Temp
Industrial Temp
256K x 18 Sync
Cache Tag
166 MHz–100 MHz
8.5ns–12 ns
3.3V VDD
3.3V and 2.5 V I/O
Features
•3.3 V +10%/–5% core power supply, 2.5 V or 3.3 V I/O supply
•Dual Cycle Deselect (DCD)
•Intergrated data comparator for Tag RAM application
•FT mode pin for flow through or pipeline operation
•LBO pin for Linear or Interleave (PentiumTM and X86) Burst mode
•Synchronous address, data I/O, and control inputs
•Synchronous Data Enable (DE)
•Asynchronous Output Enable (OE)
•Asynchronous Match Output Enable (MOE)
•Byte Write (BWE) and Global Write (GW) operation
•Three chip enable signals for easy depth expansion
•Internal self-timed write cycle
•JTAG Test mode conforms to IEEE standard 1149.1
•JEDEC-standard 100-lead TQFP package and 119-BGA:
T:TQFP or B: BGA
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-166 |
-150 |
-133 |
-100 |
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Pipeline |
tcycle |
6.0 ns |
6.6 ns |
7.5 ns |
10 ns |
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tKQ |
3.5 ns |
3.8 ns |
4.0 ns |
4.5 ns |
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3-1-1-1 |
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IDD |
310 mA |
275 mA |
250 mA |
190 mA |
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Flow |
tKQ |
8.5 ns |
10 ns |
11 ns |
12 ns |
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Through |
tcycle |
10 ns |
10 ns |
15 ns |
15 ns |
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2-1-1-1 |
IDD |
190 mA |
190 mA |
140 mA |
140 mA |
Functional Description
The GS841E18A is a 256K x 18 high performance synchronous DCD SRAM with integrated Tag RAM comparator. A 2-bit burst counter is included to provide burst
interface with PentiumTM and other high performance CPUs. It is designed to be used as a Cache Tag SRAM, as well as data SRAM. Addresses, data IOs, match output, chip enables (CE1, CE2, CE3), address control inputs (ADSP, ADSC, ADV), and write control inputs (BW1, BW2, BWE, GW, DE) are synchronous and are controlled by a positive-edge-triggered clock (CLK).
Output Enable (OE), Match Output Enable, and power down control (ZZ) are asynchronous. Burst can be initiated with either ADSP or ADSC inputs. Subsequent burst addresses are generated internally and are controlled by ADV. The burst
sequence is either interleave order (PentiumTM or x86) or linear order, and is controlled by LBO.
Output registers and the Match output register are provided and controlled by the FT mode pin (Pin 14). Through use of the FT mode pin, I/O registers can be programmed to perform pipeline or flow through operation. Flow Through mode reduces latency.
Byte write operation is performed by using Byte Write Enable (BWE) input combined with two individual byte write signals BW1-2. In addition, Global Write (GW) is available for writing all bytes at one time.
Compare cycles begin as a read cycle with output disabled so that compare data can be loaded into the data input register. The comparator compares the read data with the registered input data and a match signal is generated. The match output can be either in Pipeline or Flow Through modes controlled by the FT signal.
Low power (Standby mode) is attained through the assertion of the ZZ signal, or by stopping the clock (CLK). Memory data is retained during Standby mode.
JTAG boundary scan interface is provided using IEEE standard 1149.1 protocol. Four pins—Test Data In (TDI), Test Data Out (TDO), Test Clock (TCK) and Test Mode Select (TMS)—are used to perform JTAG function.
The GS841E18A operates on a 3.3 V power supply and all inputs/outputs are 3.3 V- or 2.5 V-LVTTL-compatible. Separate output (VDDQ) pins are used to allow both 3.3 V or 2.5 V IO interface.
Dual Cycle Deselect (DCD)
The GS841E18A is a DCD pipelines synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. DCD SRAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of the clock.
* Pentium is a trademark of Intel Corp.
Rev: 1.00 10/2001 |
1/29 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Trademark Notice (if any) Trademark of Giga Semiconductor, Inc. (GSI Technology).
GS841E18AT/B-166/150/130/100
Pin Configuration
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A6 |
A7 |
CE1 |
CE2 |
NC |
NC |
BW2 |
BW1 |
CE3 |
V |
V |
CLK |
GW |
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BWE |
OE |
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ADSC |
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ADSP |
ADV |
A8 |
A9 |
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DD |
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SS |
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NC |
100 |
99 |
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97 |
96 |
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93 |
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1 |
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80 |
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NC |
2 |
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79 |
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NC |
3 |
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78 |
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VDDQ |
4 |
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77 |
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VSS |
5 |
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76 |
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NC |
6 |
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75 |
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NC |
7 |
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74 |
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DQ9 |
8 |
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73 |
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DQ10 |
9 |
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256K x 18 |
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72 |
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VSS |
10 |
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71 |
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Top View |
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VDDQ |
11 |
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70 |
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DQ11 |
12 |
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69 |
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DQ12 |
13 |
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68 |
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FT |
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67 |
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VDD |
15 |
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
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|
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|
|
|
|
|
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|
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|
|
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|
|
|
66 |
|
|
|||
|
|
|
|
|
|
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|
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||||||
|
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|
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|
|
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|
|
|
|
|
||||||
NC |
16 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
|
65 |
|
|
|||
|
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|
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|
|
|
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|
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|
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|
|
|
|
|
||||||
VSS |
17 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
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|
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|
|
|
|
|
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|
|
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|
|
|
64 |
|
|
|||
|
|
|
|
|
|
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|
|
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|
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|
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|
||||||
|
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|
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|
|
|
|
||||||
DQ13 |
18 |
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
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|
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|
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|
|
|
63 |
|
|
|||
|
|
|
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|
|
|
|
|
|
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|
|
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|
||||||
DQ14 |
19 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
|
62 |
|
|
|||
|
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|
|
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|
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|
||||||
|
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|
|
|
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|
|
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|
|
|
|
||||||
VDDQ |
20 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
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|
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|
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|
|
|
61 |
|
|
|||
|
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|
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|
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|
||||||
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
VSS |
21 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
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|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
60 |
|
|
|||
|
|
|
|
|
|
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|
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|
||||||
|
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|
|
|
|
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|
|
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|
|
|
|
|
|
|
|
|
||||||
DQ15 |
22 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
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|
|
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|
|
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|
|
|
59 |
|
|
|||
|
|
|
|
|
|
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|
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|
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|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
DQ16 |
23 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
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|
|
|
|
|
|
|
58 |
|
|
|||
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
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|
|
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|
||||||
|
|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
DQP2 |
24 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
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|
|
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|
|
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|
|
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|
|
|
|
|
|
|
57 |
|
|
|||
|
|
|
|
|
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|
|
|
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|
|
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|
|
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|
||||||
|
|
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|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
||||||
NC |
25 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
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|
|
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|
|
|
|
|
|
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|
|
|
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|
|
|
|
|
|
56 |
|
|
|||
|
|
|
|
|
|
|
|
|
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|
|
|
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|
||||||
|
|
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|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
VSS |
26 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
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|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
55 |
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
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|
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|
|
|
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|
||||||
|
|
|
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|
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|
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|
|
|
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|
|
|
|
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|
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|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
VDDQ |
27 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
54 |
|
|
|||
|
|
|
|
|
|
|
|
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|
|
|
|
|
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|
|
|
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|
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|
|
|
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|
||||||
|
|
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|
|
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|
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|
|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
NC |
28 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
53 |
|
|
|||
|
|
|
|
|
|
|
|
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|
|
|
|
|
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|
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|
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|
|
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|
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|
||||||
|
|
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|
|
|
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|
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|
|
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|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
NC |
29 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
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|
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|
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|
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|
|
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|
|
|
|
|
|
52 |
|
|
|||
|
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|
|
|
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|
|
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|
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|
||||||
|
|
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|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
NC |
30 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
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|
|
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|
|
|
|
|
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|
|
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|
|
|
|
|
|
51 |
|
|
|||
|
|
|
|
|
|
|
|
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|
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|
|
|
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|
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|
|
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|
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|
||||||
|
|
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|
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|
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|
|
|
|
|
|
|
|
|
||||||
|
31 |
32 |
|
33 |
34 |
35 |
36 |
37 |
38 |
|
39 |
40 |
41 |
42 |
43 |
|
44 |
|
45 |
|
46 |
|
47 |
48 |
49 |
50 |
|
|
||||||||||||||||||||||||||||||
|
|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
LBO |
A5 |
A4 |
A3 |
|
A2 |
|
A1 |
|
A0 |
|
TMS |
TDI |
V |
|
V |
TDO |
TCK |
A15 |
A14 |
A13 |
A12 |
|
A11 |
|
A16 |
|
A17 |
|
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SS |
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DD |
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A10
NC
NC
VDDQ
VSS
NC
DQP1 DQ8 DQ7
VSS
VDDQ DQ6 DQ5
VSS
NC
VDD
ZZ
DQ4
DQ3
VDDQ
VSS
DQ2
DQ1
NC
NC
VSS
VDDQ
MATCH
DE
MOE
Rev: 1.00 10/2001 |
2/29 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-166/150/130/100
841E18A PadOut
119-Bump BGA—Top View
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1 |
2 |
3 |
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4 |
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6 |
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7 |
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A |
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VDDQ |
A6 |
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A7 |
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ADSP |
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A8 |
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A9 |
VDDQ |
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B |
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NC |
E2 |
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A4 |
ADSC |
A15 |
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E3 |
NC |
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C |
NC |
A5 |
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A3 |
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VDD |
A14 |
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A16 |
NC |
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D |
DQB1 |
NC |
VSS |
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NC |
VSS |
DQP1 |
NC |
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E |
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NC |
DQB2 |
VSS |
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E1 |
VSS |
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NC |
DQA8 |
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F |
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VDDQ |
NC |
VSS |
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G |
VSS |
DQA7 |
VDDQ |
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G |
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NC |
DQB3 |
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BB |
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ADV |
NC |
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NC |
DQA6 |
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H |
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DQB4 |
NC |
VSS |
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GW |
VSS |
DQA5 |
NC |
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J |
VDDQ |
VDD |
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NC |
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VDD |
NC |
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VDD |
VDDQ |
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K |
NC |
DQB5 |
VSS |
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CK |
VSS |
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NC |
DQA4 |
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L |
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DQB6 |
NC |
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NC |
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NC |
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BA |
DQA3 |
NC |
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M |
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VDDQ |
DQB7 |
VSS |
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BW |
VSS |
MATCH |
VDDQ |
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N |
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DQB8 |
NC |
VSS |
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A1 |
VSS |
DQA2 |
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DE |
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P |
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NC |
DQP2 |
VSS |
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A0 |
VSS |
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MOE |
DQA1 |
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R |
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NC |
A2 |
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LBO |
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VDD |
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FT |
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A13 |
NC |
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T |
NC |
A10 |
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A11 |
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NC |
A12 |
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A17 |
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ZZ |
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U |
VDDQ |
TMS |
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TDI |
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NC |
TDO |
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TCK |
VDDQ |
Rev: 1.00 10/2001 |
3/29 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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GS841E18AT/B-166/150/130/100 |
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TQFP Pin Description |
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Pin Location |
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Symbol |
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Description |
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37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 80, 48, |
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A0–A17 |
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Address Input Signals—Inputs are registered and must meet |
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47, 46, 45, 44, 49, 50 |
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setup and hold times, as specified on page 11. |
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89 |
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CLK |
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Clock Input Signal |
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Byte Write Enable Signal—The byte write enable signal |
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87 |
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BWE |
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needs to be combined with one of the four byte write signals |
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for a write operation to occur. |
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93 |
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BW1 |
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Byte Write signal for data outputs 1 thru 8 |
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94 |
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BW2 |
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Byte Write signal for data outputs 9 thru 16 |
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88 |
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GW |
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Global Write Enable |
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92, 97, 98 |
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CE1,CE2, CE3 |
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Chip Enables |
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86 |
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OE |
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Output Enable |
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83 |
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ADV |
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Burst address advance |
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84, 85 |
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ADSP, ADSC |
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Address status signals |
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58, 59, 62 ,63, 68, 69, 72, 73, 8, 9, 12, 13, 18, |
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DQ1–DQ16 |
|
Data Input and Output pins |
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19, 22, 23 |
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74, 24 |
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DQP1–DQP2 |
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Parity Input and Output pins |
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53 |
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MATCH |
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Match Output |
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51 |
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MOE |
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Match Output Enable |
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Data Enable—Data input registers are updated only when DE |
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52 |
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DE |
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is active. |
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64 |
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ZZ |
|
Power down control—Application of ZZ will result in a low |
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standby power consumption. |
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14 |
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FT |
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Flow Through or Pipeline mode |
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31 |
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LBO |
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Linear Order Burst mode |
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38 |
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TMS |
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Test Mode Select |
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39 |
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TDI |
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Test Data In |
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42 |
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TDO |
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Test Data Out |
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43 |
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TCK |
|
Test Clock |
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15, 41, 65, 91 |
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VDD |
|
3.3 V power supply |
|
|||||||||||||||||
|
5,10,17, 21, 26, 40, 55, 60, 67, 71, |
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VSS |
|
Ground |
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|
76, 90 |
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|
4, 11, 20, 27, 54, 61, 70, 77 |
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|
VDDQ |
|
2.5 V/3.3 V output power supply |
|
|||||||||||||||||||
|
1, 2, 3, 6, 7, 16, 25, 28, 29, 30,56, 57, 66, 75, |
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NC |
|
No Connect |
|
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|
78, 79, 95, 96 |
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Rev: 1.00 10/2001 |
4/29 |
|
|
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|
|
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
|
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GS841E18AT/B-166/150/130/100 |
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PBGA Pin Description |
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Pin Location |
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Symbol |
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Description |
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P4, N4, R2, C3, B3, C2, A2, A3, A5, A6, T6, C5, |
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A0–A17 |
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Address Input Signals—Inputs are registered and must meet |
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R6, T5, T2, T3, B5, C6 |
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setup and hold times, as specified on page 11. |
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K4 |
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CLK |
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Clock Input Signal |
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Byte Write Enable Signal—The byte write enable signal needs to |
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M4 |
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BWE |
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be combined with one of the four byte write signals for a write |
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operation to occur. |
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L5 |
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BW1 |
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Byte Write signal for data outputs 1 thru 8 |
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G3 |
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BW2 |
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Byte Write signal for data outputs 9 thru 16 |
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H4 |
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GW |
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Global Write Enable |
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E4, B2, B6 |
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CE1,CE2, CE3 |
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Chip Enables |
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F4 |
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OE |
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Output Enable |
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G4 |
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ADV |
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Burst address advance |
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A4, B4 |
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ADSP, ADSC |
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Address status signals |
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P7, N6, L6, K7, H6, G7, F6, E7, D1, E2, G2, H1, |
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DQ1–DQ16 |
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Data Input and Output pins |
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K2, L1, M2, N1 |
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D6, P2 |
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DQP1–DQP2 |
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Parity Input and Output pins |
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M6 |
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MATCH |
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Match Output |
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P6 |
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MOE |
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Match Output Enable |
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Data Enable—Data input registers are updated only when DE is |
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N7 |
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DE |
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active. |
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T7 |
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ZZ |
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Power down control—Application of ZZ will result in a low |
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standby power consumption. |
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R5 |
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FT |
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Flow Through or Pipeline mode |
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R3 |
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LBO |
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Linear Order Burst mode |
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U2 |
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TMS |
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Test Mode Select |
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U3 |
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TDI |
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Test Data In |
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U5 |
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TDO |
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Test Data Out |
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U4 |
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TCK |
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Test Clock |
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C4, J2, J4, J6, R4 |
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VDD |
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3.3 V power supply |
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D3, D5, E3, E5, F3, F5, H3, H5, K3, K5, M3, M5, |
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VSS |
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Ground |
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N3, N5, P3, P5 |
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A1, A7, F1, F7, J1, J7, M1, M7, U1, U7 |
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VDDQ |
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2.5 V/3.3 V output power supply |
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B1, B7, C1, C7, D2, D4, D7, E1, E6, F2, G1, G5, |
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G6, H2, H7, J3, J5, K1, K6, L2, L3, L4, L7, N2, |
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NC |
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No Connect |
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P1, RR1, R7, T1, T4, U6 |
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Rev: 1.00 10/2001 |
5/29 |
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© 2001, Giga Semiconductor, Inc. |
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-166/150/130/100
Functional Block Diagram
A0-17 |
18 |
REGISTER |
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D |
Q |
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A0 |
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A0 |
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D0 |
Q0 |
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A1 |
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A1 |
BINARY |
18 |
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D1 COUNTER Q1 |
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Load |
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A |
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LBO |
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256K X 18 |
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ADV |
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Memory |
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CLK |
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ADSC |
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Array |
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ADSP |
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Q |
D |
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GW |
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BWE |
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Register |
18 |
18 |
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D |
Q |
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BW1 |
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2 |
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Register |
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D |
Q |
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BW2 |
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Register Q D |
Register D Q |
Register Q D |
DE |
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Register |
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D |
Q |
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CE1 |
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Register |
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CE2 |
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D |
Q |
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CE3 |
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ZZ |
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Powerdown |
Register |
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Control |
D |
Q |
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FT |
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OE |
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MOE |
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18 |
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A, DQ, |
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54 |
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Control |
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Boundary Scan |
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DQ1-16 |
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Match |
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Registers |
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DQP1-2 |
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TDI |
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Bypass Reg |
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always (Ø) |
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TDO |
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ID Reg. |
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Instruction Reg. |
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TMS |
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TAP |
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Controller |
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TCK |
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|
Rev: 1.00 10/2001 6/29 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-166/150/130/100
Mode Pin Function
|
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LBO |
Function |
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L |
Linear Burst |
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H or NC |
Interleaved Burst |
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FT |
Function |
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L |
Flow Through |
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H or NC |
Pipeline |
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Power Down Control
ZZ |
Function |
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L or NC |
Active |
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H |
Standby, IDD = ISB |
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Note:
There are pull up devices on LBO and FT pins and pull down device on ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.
Linear Burst Sequence |
Interleaved Burst Sequence |
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A[1:0] |
A[1:0] |
A[1:0] |
A[1:0] |
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1st address |
00 |
01 |
10 |
11 |
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2nd address |
01 |
10 |
11 |
00 |
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3rd address |
10 |
11 |
00 |
01 |
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4th address |
11 |
00 |
01 |
10 |
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A[1:0] |
A[1:0] |
A[1:0] |
A[1:0] |
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1st address |
00 |
01 |
10 |
11 |
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2nd address |
01 |
00 |
11 |
10 |
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3rd address |
10 |
11 |
00 |
01 |
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4th address |
11 |
10 |
01 |
00 |
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Byte Write Function
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Function |
GW |
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BWE |
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BW1 |
BW2 |
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Read |
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H |
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H |
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X |
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X |
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Read |
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H |
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L |
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H |
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H |
||||
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Write all bytes |
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L |
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X |
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X |
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X |
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Write all bytes |
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H |
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L |
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L |
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L |
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Write byte 1 |
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H |
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L |
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L |
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H |
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Write byte 2 |
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H |
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L |
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H |
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L |
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Note: H = logic high, L = logic low, NC = no connect
Rev: 1.00 10/2001 |
7/29 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-166/150/130/100
Synchronous Truth Table
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Operation |
Address Used |
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CE1 |
CE2 |
CE3 |
ADSP |
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ADSC |
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ADV |
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Write |
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OE |
CLK |
DQ |
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Deselect Cycle, Power Down |
none |
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H |
X |
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X |
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X |
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L |
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X |
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X |
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X |
L-H |
High-Z |
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Deselect Cycle, Power Down |
none |
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L |
L |
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X |
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L |
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X |
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X |
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X |
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X |
L-H |
High-Z |
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Deselect Cycle, Power Down |
none |
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L |
X |
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H |
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L |
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X |
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X |
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X |
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X |
L-H |
High-Z |
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Deselect Cycle, Power Down |
none |
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L |
L |
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X |
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H |
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L |
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X |
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X |
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X |
L-H |
High-Z |
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Deselect Cycle, Power Down |
none |
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L |
X |
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H |
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H |
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L |
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X |
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X |
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X |
L-H |
High-Z |
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Read Cycle, Begin Burst |
external |
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L |
H |
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L |
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L |
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X |
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X |
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X |
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L |
L-H |
Q |
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Read Cycle, Begin Burst |
external |
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L |
H |
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L |
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L |
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X |
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X |
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X |
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H |
L-H |
High-Z |
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Read Cycle, Begin Burst |
external |
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L |
H |
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L |
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H |
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L |
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X |
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H |
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L |
L-H |
Q |
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Read Cycle, Begin Burst |
external |
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L |
H |
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L |
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H |
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L |
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X |
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H |
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H |
L-H |
High-Z |
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Write Cycle, Begin Burst |
external |
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L |
H |
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L |
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H |
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L |
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X |
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L |
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X |
L-H |
D |
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Read Cycle, Continue Burst |
next |
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X |
X |
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X |
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H |
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H |
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L |
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H |
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L |
L-H |
Q |
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Read Cycle, Continue Burst |
next |
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X |
X |
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X |
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H |
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H |
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L |
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H |
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H |
L-H |
High-Z |
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Read Cycle, Continue Burst |
next |
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H |
X |
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X |
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X |
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H |
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L |
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H |
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L |
L-H |
Q |
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Read Cycle, Continue Burst |
next |
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H |
X |
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X |
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X |
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H |
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L |
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H |
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H |
L-H |
High-Z |
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Write Cycle, Continue Burst |
next |
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X |
X |
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X |
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H |
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H |
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L |
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L |
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X |
L-H |
D |
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Write Cycle, Continue Burst |
next |
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H |
X |
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X |
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X |
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H |
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L |
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L |
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X |
L-H |
D |
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Read Cycle, Suspend Burst |
current |
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X |
X |
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X |
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H |
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H |
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H |
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H |
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L |
L-H |
Q |
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Read Cycle, Suspend Burst |
current |
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X |
X |
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X |
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H |
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H |
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H |
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H |
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H |
L-H |
High-Z |
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Read Cycle, Suspend Burst |
current |
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H |
X |
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X |
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X |
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H |
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H |
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H |
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L |
L-H |
Q |
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Read Cycle, Suspend Burst |
current |
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H |
X |
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X |
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X |
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H |
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H |
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H |
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H |
L-H |
High-Z |
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Write Cycle, Suspend Burst |
current |
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X |
X |
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X |
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H |
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H |
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H |
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L |
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X |
L-H |
D |
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Write Cycle, Suspend Burst |
current |
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H |
X |
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X |
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X |
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H |
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H |
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L |
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X |
L-H |
D |
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Notes:
1.X means “don’t care,” H means “logic high,” L means “logic low.”
2.Write is the logic function of GW, BWE, BW1, BW2. See Byte Write Function table for detail.
3.All inputs, except OE, must meet setup and hold on rising edge of CLK.
4.Suspending busrt generates a wait cycle.
5.ADSP LOW along with SRAM being selected always initiates a Read cycle at the L-H edge of the clock (CLK).
6.A Write cycle can only be performed by setting Write low for the clock L-H edge of the subsequent wait cycle. Refer to page 12 for the Write timing diagram.
Rev: 1.00 10/2001 |
8/29 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-166/150/130/100
Truth Table For Read/Write/Compare/Fill Write Operation
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CE |
|
Write |
DE |
MOE |
|
OE |
Match |
DQ |
|||||||
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Read |
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L |
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H |
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X |
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X |
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L |
— |
Q |
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Write |
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L |
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L |
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L |
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X |
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H |
— |
D |
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Compare |
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L |
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H |
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L |
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L |
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H |
Data Out |
D |
|||||
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Fill Write |
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L |
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L |
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H |
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X |
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X |
— |
X |
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Match Deselect |
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H |
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X |
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X |
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L |
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X |
High |
High Z |
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Deselect |
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H |
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X |
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X |
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H |
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X |
High Z |
High Z |
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Notes:
1.X means “don’t care,” H means “logic high,” L means “logic low.”
2.Write is the logic function of GW, BWE, BW1, BW2. See Byte Write Function table for detail.
3.CE is defined as CE1=L, CE2=H and CE3=L
4.All signals are synchronous and are sampled by CLK except OE and MOE. OE and MOE are asynchronous and drive the bus immediately.
Absolute Maximum Ratings (Voltage reference to VSS = 0 V)
Symbol |
Description |
Commerical |
Unit |
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VDD |
Supply Voltage |
–0.5 to 4.6 |
V |
|
VDDQ |
Output Supply Voltage |
–0.5 to VDD |
V |
|
VCLK |
CLK Input Voltage |
–0.5 to 6 |
V |
|
Vin |
Input Voltage |
–0.5 to VDD + 0.5 |
V |
|
(≤ 4.6 V max. ) |
||||
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Vout |
Output Voltage |
–0.5 to VDD + 0.5 |
V |
|
(≤ 4.6 V max. ) |
||||
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Iout |
Output Current per I/O |
+/–20 |
mA |
|
PD |
Power Dissipation |
1.5 |
W |
|
TOPR |
Operating Temperature |
0 to 70 |
oC |
|
TSTG |
Storage Temperature |
–55 to 125 |
oC |
Note: Permanent damage to the device may occur if the Absolute Maximun Ratings are exceeded. Functional operation should be restricted to the recommended operation conditions. Exposure to higher than recommended voltages, for an extended period of time, could effect the performance and reliability of this component.
Rev: 1.00 10/2001 |
9/29 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.